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ppc4xx: Cleanup PLU405 board code

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Some Coding style cleanup (braces, whitespaces, long lines)

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs 2009-07-16 22:13:57 +02:00 • committed by Stefan Roese
parent b209a11482
commit d4d2e79bb4
1 changed files with 62 additions and 56 deletions
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70
board/esd/plu405/plu405.c
View file

@ -27,10 +27,7 @@
#include <command.h> #include <command.h>
#include <malloc.h> #include <malloc.h>
#undef FPGA_DEBUG
#if 0
#define FPGA_DEBUG
#endif
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -48,7 +45,6 @@ const unsigned char fpgadata[] =
*/ */
#include "../common/fpga.c" #include "../common/fpga.c"
/* /*
* include common auto-update code (for esd boards) * include common auto-update code (for esd boards)
*/ */
@ -101,8 +97,6 @@ int board_early_init_f (void)
int misc_init_r(void) int misc_init_r(void)
{ {
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned char *dst; unsigned char *dst;
unsigned char fctr; unsigned char fctr;
ulong len = sizeof(fpgadata); ulong len = sizeof(fpgadata);
@ -115,7 +109,8 @@ int misc_init_r (void)
gd->bd->bi_flashoffset = 0; gd->bd->bi_flashoffset = 0;
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
(uchar *)fpgadata, &len) != 0) {
printf("GUNZIP ERROR - must RESET board to recover\n"); printf("GUNZIP ERROR - must RESET board to recover\n");
do_reset(NULL, 0, 0, NULL); do_reset(NULL, 0, 0, NULL);
} }
@ -180,29 +175,35 @@ int misc_init_r (void)
/* /*
* Reset external DUARTs * Reset external DUARTs
*/ */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
udelay(10); udelay(10);
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
udelay(1000); udelay(1000);
/* /*
* Set NAND-FLASH GPIO signals to default * Set NAND-FLASH GPIO signals to default
*/ */
out_be32((void*)GPIO0_OR, out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); in_be32((void*)GPIO0_OR) &
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
/* /*
* Setup EEPROM write protection * Setup EEPROM write protection
*/ */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); out_be32((void*)GPIO0_OR,
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
out_be32((void*)GPIO0_TCR,
in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
/* /*
* Enable interrupts in exar duart mcr[3] * Enable interrupts in exar duart mcr[3]
*/ */
out_8(duart0_mcr, 0x08); out_8((void *)DUART0_BA + 4, 0x08);
out_8(duart1_mcr, 0x08); out_8((void *)DUART1_BA + 4, 0x08);
/* /*
* Enable auto RS485 mode in 2nd external uart * Enable auto RS485 mode in 2nd external uart
@ -213,7 +214,7 @@ int misc_init_r (void)
out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */ out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
out_8((void *)DUART1_BA + 3, 0); /* write LCR */ out_8((void *)DUART1_BA + 3, 0); /* write LCR */
return (0); return 0;
} }
/* /*
@ -226,11 +227,10 @@ int checkboard (void)
puts("Board: "); puts("Board: ");
if (i == -1) { if (i == -1)
puts("### No HW ID - assuming PLU405"); puts("### No HW ID - assuming PLU405");
} else { else
puts(str); puts(str);
}
putc('\n'); putc('\n');
return 0; return 0;
@ -245,10 +245,12 @@ void ide_set_reset(int on)
*/ */
if (on) { /* assert RESET */ if (on) { /* assert RESET */
out_be16((void *)FPGA_CTRL, out_be16((void *)FPGA_CTRL,
in_be16((void *)FPGA_CTRL) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET); in_be16((void *)FPGA_CTRL) &
~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */ } else { /* release RESET */
out_be16((void *)FPGA_CTRL, out_be16((void *)FPGA_CTRL,
in_be16((void *)FPGA_CTRL) | CONFIG_SYS_FPGA_CTRL_CF_RESET); in_be16((void *)FPGA_CTRL) |
CONFIG_SYS_FPGA_CTRL_CF_RESET);
} }
} }
#endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_IDE_RESET */
@ -282,19 +284,21 @@ int eeprom_write_enable (unsigned dev_addr, int state)
case 1: case 1:
/* Enable write access, clear bit GPIO0. */ /* Enable write access, clear bit GPIO0. */
out_be32((void*)GPIO0_OR, out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); in_be32((void*)GPIO0_OR) &
~CONFIG_SYS_EEPROM_WP);
state = 0; state = 0;
break; break;
case 0: case 0:
/* Disable write access, set bit GPIO0. */ /* Disable write access, set bit GPIO0. */
out_be32((void*)GPIO0_OR, out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); in_be32((void*)GPIO0_OR) |
CONFIG_SYS_EEPROM_WP);
state = 0; state = 0;
break; break;
default: default:
/* Read current status back. */ /* Read current status back. */
state = (0 == (in_be32((void*)GPIO0_OR) & state = ((in_be32((void*)GPIO0_OR) &
CONFIG_SYS_EEPROM_WP)); CONFIG_SYS_EEPROM_WP) == 0);
break; break;
} }
} }
@ -313,21 +317,23 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
puts("Query of write access state failed.\n"); puts("Query of write access state failed.\n");
} else { } else {
printf("Write access for device 0x%0x is %sabled.\n", printf("Write access for device 0x%0x is %sabled.\n",
CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); CONFIG_SYS_I2C_EEPROM_ADDR,
state ? "en" : "dis");
state = 0; state = 0;
} }
} else { } else {
if ('0' == argv[1][0]) { if (argv[1][0] == '0') {
/* Disable write access. */ /* Disable write access. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
0);
} else { } else {
/* Enable write access. */ /* Enable write access. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
1);
} }
if (state < 0) { if (state < 0)
puts("Setup of write access state failed.\n"); puts("Setup of write access state failed.\n");
} }
}
return state; return state;
} }