GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-04-05 05:51:31 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ppc4xx: Cleanup PLU405 board code

Browse source 
Some Coding style cleanup (braces, whitespaces, long lines)

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs 2009-07-16 22:13:57 +02:00 • committed by Stefan Roese
parent b209a11482
commit d4d2e79bb4
1 changed files with 62 additions and 56 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

118
board/esd/plu405/plu405.c
View file

@ -27,10 +27,7 @@
#include <command.h> #include <command.h>
#include <malloc.h> #include <malloc.h>
#undef FPGA_DEBUG
#if 0
#define FPGA_DEBUG
#endif
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -48,7 +45,6 @@ const unsigned char fpgadata[] =
*/ */
#include "../common/fpga.c" #include "../common/fpga.c"
/* /*
* include common auto-update code (for esd boards) * include common auto-update code (for esd boards)
*/ */
@ -68,7 +64,7 @@ int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
/* Prototypes */ /* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *); int gunzip(void *, int, unsigned char *, unsigned long *);
int board_early_init_f (void) int board_early_init_f(void)
{ {
/* /*
* IRQ 0-15 405GP internally generated; active high; level sensitive * IRQ 0-15 405GP internally generated; active high; level sensitive
@ -94,15 +90,13 @@ int board_early_init_f (void)
* EBC Configuration Register: set ready timeout to * EBC Configuration Register: set ready timeout to
* 512 ebc-clks -> ca. 15 us * 512 ebc-clks -> ca. 15 us
*/ */
mtebc (epcr, 0xa8400000); /* ebc always driven */ mtebc(epcr, 0xa8400000); /* ebc always driven */
return 0; return 0;
} }
int misc_init_r (void) int misc_init_r(void)
{ {
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned char *dst; unsigned char *dst;
unsigned char fctr; unsigned char fctr;
ulong len = sizeof(fpgadata); ulong len = sizeof(fpgadata);
@ -115,9 +109,10 @@ int misc_init_r (void)
gd->bd->bi_flashoffset = 0; gd->bd->bi_flashoffset = 0;
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
printf ("GUNZIP ERROR - must RESET board to recover\n"); (uchar *)fpgadata, &len) != 0) {
do_reset (NULL, 0, 0, NULL); printf("GUNZIP ERROR - must RESET board to recover\n");
do_reset(NULL, 0, 0, NULL);
} }
status = fpga_boot(dst, len); status = fpga_boot(dst, len);
@ -152,7 +147,7 @@ int misc_init_r (void)
for (index=0;index<1000;index++) for (index=0;index<1000;index++)
udelay(1000); udelay(1000);
} }
putc ('\n'); putc('\n');
do_reset(NULL, 0, 0, NULL); do_reset(NULL, 0, 0, NULL);
} }
@ -165,7 +160,7 @@ int misc_init_r (void)
printf("%s ", &(dst[index+1])); printf("%s ", &(dst[index+1]));
index += len+3; index += len+3;
} }
putc ('\n'); putc('\n');
free(dst); free(dst);
@ -180,29 +175,35 @@ int misc_init_r (void)
/* /*
* Reset external DUARTs * Reset external DUARTs
*/ */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
udelay(10); udelay(10);
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
udelay(1000); udelay(1000);
/* /*
* Set NAND-FLASH GPIO signals to default * Set NAND-FLASH GPIO signals to default
*/ */
out_be32((void*)GPIO0_OR, out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); in_be32((void*)GPIO0_OR) &
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
/* /*
* Setup EEPROM write protection * Setup EEPROM write protection
*/ */
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); out_be32((void*)GPIO0_OR,
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
out_be32((void*)GPIO0_TCR,
in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
/* /*
* Enable interrupts in exar duart mcr[3] * Enable interrupts in exar duart mcr[3]
*/ */
out_8(duart0_mcr, 0x08); out_8((void *)DUART0_BA + 4, 0x08);
out_8(duart1_mcr, 0x08); out_8((void *)DUART1_BA + 4, 0x08);
/* /*
* Enable auto RS485 mode in 2nd external uart * Enable auto RS485 mode in 2nd external uart
@ -213,26 +214,25 @@ int misc_init_r (void)
out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */ out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
out_8((void *)DUART1_BA + 3, 0); /* write LCR */ out_8((void *)DUART1_BA + 3, 0); /* write LCR */
return (0); return 0;
} }
/* /*
* Check Board Identity: * Check Board Identity:
*/ */
int checkboard (void) int checkboard(void)
{ {
char str[64]; char str[64];
int i = getenv_r ("serial#", str, sizeof(str)); int i = getenv_r("serial#", str, sizeof(str));
puts ("Board: "); puts("Board: ");
if (i == -1) { if (i == -1)
puts ("### No HW ID - assuming PLU405"); puts("### No HW ID - assuming PLU405");
} else { else
puts(str); puts(str);
}
putc ('\n'); putc('\n');
return 0; return 0;
} }
@ -245,10 +245,12 @@ void ide_set_reset(int on)
*/ */
if (on) { /* assert RESET */ if (on) { /* assert RESET */
out_be16((void *)FPGA_CTRL, out_be16((void *)FPGA_CTRL,
in_be16((void *)FPGA_CTRL) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET); in_be16((void *)FPGA_CTRL) &
~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */ } else { /* release RESET */
out_be16((void *)FPGA_CTRL, out_be16((void *)FPGA_CTRL,
in_be16((void *)FPGA_CTRL) | CONFIG_SYS_FPGA_CTRL_CF_RESET); in_be16((void *)FPGA_CTRL) |
CONFIG_SYS_FPGA_CTRL_CF_RESET);
} }
} }
#endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_IDE_RESET */
@ -266,14 +268,14 @@ void reset_phy(void)
#if defined(CONFIG_SYS_EEPROM_WREN) #if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable. /* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state * <state> -1: deliver current state
* 0: disable write * 0: disable write
* 1: enable write * 1: enable write
* Returns: -1: wrong device address * Returns: -1: wrong device address
* 0: dis-/en- able done * 0: dis-/en- able done
* 0/1: current state if <state> was -1. * 0/1: current state if <state> was -1.
*/ */
int eeprom_write_enable (unsigned dev_addr, int state) int eeprom_write_enable(unsigned dev_addr, int state)
{ {
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1; return -1;
@ -282,51 +284,55 @@ int eeprom_write_enable (unsigned dev_addr, int state)
case 1: case 1:
/* Enable write access, clear bit GPIO0. */ /* Enable write access, clear bit GPIO0. */
out_be32((void*)GPIO0_OR, out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); in_be32((void*)GPIO0_OR) &
~CONFIG_SYS_EEPROM_WP);
state = 0; state = 0;
break; break;
case 0: case 0:
/* Disable write access, set bit GPIO0. */ /* Disable write access, set bit GPIO0. */
out_be32((void*)GPIO0_OR, out_be32((void*)GPIO0_OR,
in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); in_be32((void*)GPIO0_OR) |
CONFIG_SYS_EEPROM_WP);
state = 0; state = 0;
break; break;
default: default:
/* Read current status back. */ /* Read current status back. */
state = (0 == (in_be32((void*)GPIO0_OR) & state = ((in_be32((void*)GPIO0_OR) &
CONFIG_SYS_EEPROM_WP)); CONFIG_SYS_EEPROM_WP) == 0);
break; break;
} }
} }
return state; return state;
} }
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
int query = argc == 1; int query = argc == 1;
int state = 0; int state = 0;
if (query) { if (query) {
/* Query write access state. */ /* Query write access state. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) { if (state < 0) {
puts ("Query of write access state failed.\n"); puts("Query of write access state failed.\n");
} else { } else {
printf ("Write access for device 0x%0x is %sabled.\n", printf("Write access for device 0x%0x is %sabled.\n",
CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); CONFIG_SYS_I2C_EEPROM_ADDR,
state ? "en" : "dis");
state = 0; state = 0;
} }
} else { } else {
if ('0' == argv[1][0]) { if (argv[1][0] == '0') {
/* Disable write access. */ /* Disable write access. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
0);
} else { } else {
/* Enable write access. */ /* Enable write access. */
state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
} 1);
if (state < 0) {
puts ("Setup of write access state failed.\n");
} }
if (state < 0)
puts("Setup of write access state failed.\n");
} }
return state; return state;