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ddr: marvell: a38x: allow board specific clock out setup
DDR clock out might be unrelated to the number of active chip-select. For example, the board might have two DDR components, but only one chip-select. The clk_enable mask allows the board to enable DDR clocks regardless of active chip-selects. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
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parent
c7819d409a
commit
d67b98ed47
2 changed files with 11 additions and 2 deletions
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@ -280,8 +280,14 @@ int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
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{
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u32 data, addr_hi, data_high;
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u32 mem_index;
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u32 clk_enable;
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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if (tm->clk_enable & (1 << cs_num))
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clk_enable = 1;
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else
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clk_enable = enable;
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if (enable == 1) {
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data = (tm->interface_params[if_id].bus_width ==
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MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1;
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@ -316,13 +322,13 @@ int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
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case 2:
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CHECK_STATUS(ddr3_tip_if_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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DUNIT_CTRL_LOW_REG, (enable << (cs_num + 11)),
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DUNIT_CTRL_LOW_REG, (clk_enable << (cs_num + 11)),
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1 << (cs_num + 11)));
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break;
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case 3:
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CHECK_STATUS(ddr3_tip_if_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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DUNIT_CTRL_LOW_REG, (enable << 15), 1 << 15));
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DUNIT_CTRL_LOW_REG, (clk_enable << 15), 1 << 15));
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break;
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}
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@ -124,6 +124,9 @@ struct mv_ddr_topology_map {
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/* electrical parameters */
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unsigned int electrical_data[MV_DDR_EDATA_LAST];
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/* Clock enable mask */
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u32 clk_enable;
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};
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enum mv_ddr_iface_mode {
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