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mtd: spinand: Sync GigaDevice GD5F1GQ4UExxG with latest Linux version
This patch sync's the U-Boot SPI NAND GigaDevice GD5F1GQ4UExxG support with the latest Linux version (v5.0-rc3) plus the chip supported posted on the MTD list. Only the currently in U-Boot available chip is supported with this sync. The changes for the GD5F1GQ4UExxG are: - Name of NAND device changed to better reflect the real part - OOB layout changed to only reserve 1 byte for BBT - Use ECC caps 8bits/512bytes instead of 8bits/2048bytes - Enhanced ecc_get_status() function to determine and report a more fine grained bit error status Signed-off-by: Stefan Roese <sr@denx.de> Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Stefan Roese
Jagan Teki
parent
7eece32812
commit
d67fb265d1
1 changed files with 46 additions and 31 deletions
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@ -12,12 +12,11 @@
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#endif
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_GIGADEVICE 0xc8
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#define SPINAND_MFR_GIGADEVICE 0xC8
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#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
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#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
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#define GIGADEVICE_STATUS_ECC_MASK GENMASK(5, 4)
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#define GIGADEVICE_STATUS_ECC_NO_BITFLIPS (0 << 4)
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#define GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS (1 << 4)
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#define GIGADEVICE_STATUS_ECC_8_BITFLIPS (3 << 4)
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#define GD5FXGQ4XEXXG_REG_STATUS2 0xf0
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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@ -35,8 +34,8 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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static int gd5f1gq4u_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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static int gd5fxgq4xexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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@ -47,38 +46,49 @@ static int gd5f1gq4u_ooblayout_ecc(struct mtd_info *mtd, int section,
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return 0;
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}
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static int gd5f1gq4u_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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static int gd5fxgq4xexxg_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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/* Reserve 2 bytes for the BBM. */
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region->offset = 2;
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region->length = 62;
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/* Reserve 1 bytes for the BBM. */
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region->offset = 1;
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region->length = 63;
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return 0;
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}
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static const struct mtd_ooblayout_ops gd5f1gq4u_ooblayout = {
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.ecc = gd5f1gq4u_ooblayout_ecc,
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.free = gd5f1gq4u_ooblayout_free,
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};
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static int gd5f1gq4u_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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if (status)
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debug("%s (%d): status=%02x\n", __func__, __LINE__, status);
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u8 status2;
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struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4XEXXG_REG_STATUS2,
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&status2);
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int ret;
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switch (status & GIGADEVICE_STATUS_ECC_MASK) {
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switch (status & STATUS_ECC_MASK) {
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case STATUS_ECC_NO_BITFLIPS:
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return 0;
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case GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS:
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return 7;
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case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
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/*
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* Read status2 register to determine a more fine grained
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* bit error status
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*/
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ret = spi_mem_exec_op(spinand->slave, &op);
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if (ret)
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return ret;
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case GIGADEVICE_STATUS_ECC_8_BITFLIPS:
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/*
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* 4 ... 7 bits are flipped (1..4 can't be detected, so
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* report the maximum of 4 in this case
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*/
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/* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */
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return ((status & STATUS_ECC_MASK) >> 2) |
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((status2 & STATUS_ECC_MASK) >> 4);
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case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
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return 8;
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case STATUS_ECC_UNCOR_ERROR:
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@ -91,16 +101,21 @@ static int gd5f1gq4u_ecc_get_status(struct spinand_device *spinand,
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return -EINVAL;
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}
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static const struct mtd_ooblayout_ops gd5fxgq4xexxg_ooblayout = {
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.ecc = gd5fxgq4xexxg_ooblayout_ecc,
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.free = gd5fxgq4xexxg_ooblayout_free,
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};
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static const struct spinand_info gigadevice_spinand_table[] = {
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SPINAND_INFO("GD5F1GQ4UC", 0xd1,
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SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
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NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 2048),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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0,
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SPINAND_ECCINFO(&gd5f1gq4u_ooblayout,
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gd5f1gq4u_ecc_get_status)),
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SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout,
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gd5fxgq4xexxg_ecc_get_status)),
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};
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static int gigadevice_spinand_detect(struct spinand_device *spinand)
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@ -109,8 +124,8 @@ static int gigadevice_spinand_detect(struct spinand_device *spinand)
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int ret;
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/*
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* Gigadevice SPI NAND read ID need a dummy byte,
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* so the first byte in raw_id is dummy.
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* For GD NANDs, There is an address byte needed to shift in before IDs
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* are read out, so the first byte in raw_id is dummy.
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*/
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if (id[1] != SPINAND_MFR_GIGADEVICE)
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return 0;
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