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dt-bindings: clock: rk3328: sync from upstream Linux kernel
This syncs the rk3328 clock header file from Linux kernel next-20200324,
to support newer hardware blocks when syncing the device tree files.
The last non-merge commit to touch it was
0dc14b013f79 ("clk: rockchip: add clock id for watchdog pclk on rk3328")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Chen-Yu Tsai
Kever Yang
parent
32fd6169a1
commit
d751b0c000
1 changed files with 106 additions and 106 deletions
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
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* Author: Elaine <zhangqing@rock-chips.com>
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*/
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
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@ -90,119 +91,118 @@
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#define SCLK_MAC2IO_EXT 102
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#define SCLK_MAC2IO_EXT 102
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/* dclk gates */
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/* dclk gates */
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#define DCLK_LCDC 180
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#define DCLK_LCDC 120
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#define DCLK_HDMIPHY 181
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#define DCLK_HDMIPHY 121
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#define HDMIPHY 182
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#define HDMIPHY 122
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#define USB480M 183
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#define USB480M 123
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#define DCLK_LCDC_SRC 184
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#define DCLK_LCDC_SRC 124
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/* aclk gates */
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/* aclk gates */
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#define ACLK_AXISRAM 190
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#define ACLK_AXISRAM 130
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#define ACLK_VOP_PRE 191
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#define ACLK_VOP_PRE 131
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#define ACLK_USB3OTG 192
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#define ACLK_USB3OTG 132
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#define ACLK_RGA_PRE 193
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#define ACLK_RGA_PRE 133
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#define ACLK_DMAC 194
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#define ACLK_DMAC 134
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#define ACLK_GPU 195
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#define ACLK_GPU 135
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#define ACLK_BUS_PRE 196
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#define ACLK_BUS_PRE 136
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#define ACLK_PERI_PRE 197
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#define ACLK_PERI_PRE 137
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#define ACLK_RKVDEC_PRE 198
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#define ACLK_RKVDEC_PRE 138
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#define ACLK_RKVDEC 199
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#define ACLK_RKVDEC 139
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#define ACLK_RKVENC 200
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#define ACLK_RKVENC 140
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#define ACLK_VPU_PRE 201
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#define ACLK_VPU_PRE 141
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#define ACLK_VIO_PRE 202
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#define ACLK_VIO_PRE 142
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#define ACLK_VPU 203
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#define ACLK_VPU 143
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#define ACLK_VIO 204
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#define ACLK_VIO 144
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#define ACLK_VOP 205
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#define ACLK_VOP 145
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#define ACLK_GMAC 206
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#define ACLK_GMAC 146
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#define ACLK_H265 207
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#define ACLK_H265 147
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#define ACLK_H264 208
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#define ACLK_H264 148
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#define ACLK_MAC2PHY 209
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#define ACLK_MAC2PHY 149
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#define ACLK_MAC2IO 210
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#define ACLK_MAC2IO 150
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#define ACLK_DCF 211
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#define ACLK_DCF 151
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#define ACLK_TSP 212
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#define ACLK_TSP 152
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#define ACLK_PERI 213
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#define ACLK_PERI 153
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#define ACLK_RGA 214
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#define ACLK_RGA 154
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#define ACLK_IEP 215
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#define ACLK_IEP 155
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#define ACLK_CIF 216
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#define ACLK_CIF 156
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#define ACLK_HDCP 217
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#define ACLK_HDCP 157
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/* pclk gates */
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/* pclk gates */
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#define PCLK_GPIO0 300
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#define PCLK_GPIO0 200
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#define PCLK_GPIO1 301
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#define PCLK_GPIO1 201
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#define PCLK_GPIO2 302
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#define PCLK_GPIO2 202
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#define PCLK_GPIO3 303
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#define PCLK_GPIO3 203
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#define PCLK_GRF 304
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#define PCLK_GRF 204
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#define PCLK_I2C0 305
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#define PCLK_I2C0 205
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#define PCLK_I2C1 306
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#define PCLK_I2C1 206
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#define PCLK_I2C2 307
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#define PCLK_I2C2 207
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#define PCLK_I2C3 308
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#define PCLK_I2C3 208
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#define PCLK_SPI 309
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#define PCLK_SPI 209
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#define PCLK_UART0 310
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#define PCLK_UART0 210
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#define PCLK_UART1 311
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#define PCLK_UART1 211
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#define PCLK_UART2 312
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#define PCLK_UART2 212
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#define PCLK_TSADC 313
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#define PCLK_TSADC 213
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#define PCLK_PWM 314
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#define PCLK_PWM 214
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#define PCLK_TIMER 315
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#define PCLK_TIMER 215
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#define PCLK_BUS_PRE 316
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#define PCLK_BUS_PRE 216
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#define PCLK_PERI_PRE 317
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#define PCLK_PERI_PRE 217
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#define PCLK_HDMI_CTRL 318
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#define PCLK_HDMI_CTRL 218
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#define PCLK_HDMI_PHY 319
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#define PCLK_HDMI_PHY 219
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#define PCLK_GMAC 320
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#define PCLK_GMAC 220
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#define PCLK_H265 321
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#define PCLK_H265 221
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#define PCLK_MAC2PHY 322
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#define PCLK_MAC2PHY 222
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#define PCLK_MAC2IO 323
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#define PCLK_MAC2IO 223
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#define PCLK_USB3PHY_OTG 324
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#define PCLK_USB3PHY_OTG 224
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#define PCLK_USB3PHY_PIPE 325
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#define PCLK_USB3PHY_PIPE 225
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#define PCLK_USB3_GRF 326
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#define PCLK_USB3_GRF 226
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#define PCLK_USB2_GRF 327
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#define PCLK_USB2_GRF 227
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#define PCLK_HDMIPHY 328
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#define PCLK_HDMIPHY 228
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#define PCLK_DDR 329
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#define PCLK_DDR 229
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#define PCLK_PERI 330
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#define PCLK_PERI 230
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#define PCLK_HDMI 331
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#define PCLK_HDMI 231
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#define PCLK_HDCP 332
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#define PCLK_HDCP 232
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#define PCLK_DCF 333
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#define PCLK_DCF 233
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#define PCLK_SARADC 334
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#define PCLK_SARADC 234
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#define PCLK_ACODECPHY 235
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#define PCLK_WDT 236
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/* hclk gates */
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/* hclk gates */
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#define HCLK_PERI 408
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#define HCLK_PERI 308
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#define HCLK_TSP 409
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#define HCLK_TSP 309
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#define HCLK_GMAC 410
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#define HCLK_GMAC 310
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#define HCLK_I2S0_8CH 411
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#define HCLK_I2S0_8CH 311
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#define HCLK_I2S1_8CH 413
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#define HCLK_I2S1_8CH 312
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#define HCLK_I2S2_2CH 413
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#define HCLK_I2S2_2CH 313
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#define HCLK_SPDIF_8CH 414
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#define HCLK_SPDIF_8CH 314
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#define HCLK_VOP 415
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#define HCLK_VOP 315
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#define HCLK_NANDC 416
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#define HCLK_NANDC 316
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#define HCLK_SDMMC 417
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#define HCLK_SDMMC 317
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#define HCLK_SDIO 418
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#define HCLK_SDIO 318
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#define HCLK_EMMC 419
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#define HCLK_EMMC 319
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#define HCLK_SDMMC_EXT 420
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#define HCLK_SDMMC_EXT 320
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#define HCLK_RKVDEC_PRE 421
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#define HCLK_RKVDEC_PRE 321
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#define HCLK_RKVDEC 422
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#define HCLK_RKVDEC 322
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#define HCLK_RKVENC 423
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#define HCLK_RKVENC 323
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#define HCLK_VPU_PRE 424
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#define HCLK_VPU_PRE 324
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#define HCLK_VIO_PRE 425
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#define HCLK_VIO_PRE 325
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#define HCLK_VPU 426
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#define HCLK_VPU 326
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#define HCLK_VIO 427
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#define HCLK_BUS_PRE 328
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#define HCLK_BUS_PRE 428
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#define HCLK_PERI_PRE 329
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#define HCLK_PERI_PRE 429
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#define HCLK_H264 330
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#define HCLK_H264 430
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#define HCLK_CIF 331
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#define HCLK_CIF 431
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#define HCLK_OTG_PMU 332
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#define HCLK_OTG_PMU 432
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#define HCLK_OTG 333
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#define HCLK_OTG 433
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#define HCLK_HOST0 334
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#define HCLK_HOST0 434
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#define HCLK_HOST0_ARB 335
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#define HCLK_HOST0_ARB 435
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#define HCLK_CRYPTO_MST 336
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#define HCLK_CRYPTO_MST 436
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#define HCLK_CRYPTO_SLV 337
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#define HCLK_CRYPTO_SLV 437
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#define HCLK_PDM 338
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#define HCLK_PDM 438
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#define HCLK_IEP 339
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#define HCLK_IEP 439
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#define HCLK_RGA 340
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#define HCLK_RGA 440
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#define HCLK_HDCP 341
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#define HCLK_HDCP 441
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#define CLK_NR_CLKS (HCLK_HDCP + 1)
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#define CLK_NR_CLKS (HCLK_HDCP + 1)
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#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
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/* soft-reset indices */
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/* soft-reset indices */
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#define SRST_CORE0_PO 0
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE1_PO 1
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