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fu740: Add flush_dcache_range function
Signed-off-by: TekkamanV <tekkamanv@starfivetech.com>
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2 changed files with 48 additions and 0 deletions
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@ -38,3 +38,18 @@ config SIFIVE_FU740
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imply DM_I2C
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imply SYS_I2C_OCORES
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imply SPL_I2C
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config SIFIVE_FU740_L2CC_FLUSH
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bool "Support Level 2 Cache Controller Flush operation of SiFive fu740"
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if SIFIVE_FU740_L2CC_FLUSH
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config SIFIVE_FU740_L2CC_FLUSH_START
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hex "Level 2 Cache Flush operation start"
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default 0x80000000
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config SIFIVE_FU740_L2CC_FLUSH_SIZE
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hex "Level 2 Cache Flush operation size"
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default 0x800000000
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endif # SIFIVE_FU740_L2CC_FLUSH
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@ -57,3 +57,36 @@ int cache_enable_ways(void)
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mb();
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return 0;
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}
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#if CONFIG_IS_ENABLED(SIFIVE_FU740_L2CC_FLUSH)
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#define L2_CACHE_FLUSH64 0x200
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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fdt_addr_t base;
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unsigned long line;
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volatile unsigned long *flush64;
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/* make sure the address is in the range */
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if(start > end ||
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start < CONFIG_SIFIVE_FU740_L2CC_FLUSH_START ||
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end > (CONFIG_SIFIVE_FU740_L2CC_FLUSH_START +
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CONFIG_SIFIVE_FU740_L2CC_FLUSH_SIZE))
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return;
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base = l2cc_get_base_addr();
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if (base == FDT_ADDR_T_NONE)
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return;
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flush64 = (volatile unsigned long *)(base + L2_CACHE_FLUSH64);
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/* memory barrier */
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mb();
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for (line = start; line < end; line += CONFIG_SYS_CACHELINE_SIZE)
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(*flush64) = line;
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/* memory barrier */
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mb();
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return;
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}
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#endif //SIFIVE_FU740_L2CC_FLUSH
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