GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-21 06:31:31 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

Browse source 
The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Shengzhou Liu 2016-05-04 10:20:21 +08:00 • committed by York Sun
parent 8b528709c5
commit d8e5163ad8
1 changed files with 9 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
drivers/ddr/fsl/ctrl_regs.c
View file

@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
/* Per FSL Application Note: AN2805 */
ss_en = 1;
#endif
clk_adjust = popts->clk_adjust;
if (fsl_ddr_get_version(0) >= 0x40701) {
/* clk_adjust in 5-bits on T-series and LS-series */
clk_adjust = (popts->clk_adjust & 0x1F) << 22;
} else {
/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
clk_adjust = (popts->clk_adjust & 0xF) << 23;
}
ddr->ddr_sdram_clk_cntl = (0
| ((ss_en & 0x1) << 31)
| ((clk_adjust & 0xF) << 23)
| clk_adjust
);
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
}