mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
armv7: Move L2CTLR read/write to common
L2CTLR read/write functions are common to armv7 so, move them in to include/asm/armv7.h and use them where ever it need. Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Backed out the change to arch/arm/mach-tegra/cache.c:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
parent
f3f6591ca3
commit
d9a7dcf5b8
2 changed files with 22 additions and 21 deletions
|
@ -61,6 +61,27 @@
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/barriers.h>
|
#include <asm/barriers.h>
|
||||||
|
|
||||||
|
/* read L2 control register (L2CTLR) */
|
||||||
|
static inline uint32_t read_l2ctlr(void)
|
||||||
|
{
|
||||||
|
uint32_t val = 0;
|
||||||
|
|
||||||
|
asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
|
||||||
|
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* write L2 control register (L2CTLR) */
|
||||||
|
static inline void write_l2ctlr(uint32_t val)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Note: L2CTLR can only be written when the L2 memory system
|
||||||
|
* is idle, ie before the MMU is enabled.
|
||||||
|
*/
|
||||||
|
asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
|
||||||
|
isb();
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Workaround for ARM errata # 798870
|
* Workaround for ARM errata # 798870
|
||||||
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
|
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
|
||||||
|
|
|
@ -13,6 +13,7 @@
|
||||||
#include <malloc.h>
|
#include <malloc.h>
|
||||||
#include <ram.h>
|
#include <ram.h>
|
||||||
#include <spl.h>
|
#include <spl.h>
|
||||||
|
#include <asm/armv7.h>
|
||||||
#include <asm/gpio.h>
|
#include <asm/gpio.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/arch/bootrom.h>
|
#include <asm/arch/bootrom.h>
|
||||||
|
@ -80,27 +81,6 @@ u32 spl_boot_mode(const u32 boot_device)
|
||||||
return MMCSD_MODE_RAW;
|
return MMCSD_MODE_RAW;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* read L2 control register (L2CTLR) */
|
|
||||||
static inline uint32_t read_l2ctlr(void)
|
|
||||||
{
|
|
||||||
uint32_t val = 0;
|
|
||||||
|
|
||||||
asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
|
|
||||||
|
|
||||||
return val;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write L2 control register (L2CTLR) */
|
|
||||||
static inline void write_l2ctlr(uint32_t val)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Note: L2CTLR can only be written when the L2 memory system
|
|
||||||
* is idle, ie before the MMU is enabled.
|
|
||||||
*/
|
|
||||||
asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
|
|
||||||
isb();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void configure_l2ctlr(void)
|
static void configure_l2ctlr(void)
|
||||||
{
|
{
|
||||||
uint32_t l2ctlr;
|
uint32_t l2ctlr;
|
||||||
|
|
Loading…
Add table
Reference in a new issue