mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-15 19:51:37 +00:00
Merge branch '2021-01-18-assorted-platform-updates'
- Assorted MediaTek, AST2x00 updates - Assorted driver fixes for various platforms - Keymile platform updates - Add pwm command, mp5416 pmic driver
This commit is contained in:
commit
db0dd72e27
86 changed files with 9442 additions and 305 deletions
|
@ -198,6 +198,9 @@ F: drivers/mmc/ca_dw_mmc.c
|
|||
F: drivers/spi/ca_sflash.c
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||||
F: drivers/i2c/i2c-cortina.c
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||||
F: drivers/i2c/i2c-cortina.h
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||||
F: drivers/mtd/nand/raw/cortina_nand.c
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||||
F: drivers/mtd/nand/raw/cortina_nand.h
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F: configs/cortina_presidio-asic-pnand_defconfig
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||||
|
||||
ARM/CZ.NIC TURRIS MOX SUPPORT
|
||||
M: Marek Behun <marek.behun@nic.cz>
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||||
|
|
1
README
1
README
|
@ -3153,6 +3153,7 @@ i2c - I2C sub-system
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|||
sspi - SPI utility commands
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base - print or set address offset
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printenv- print environment variables
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pwm - control pwm channels
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setenv - set environment variables
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saveenv - save environment variables to persistent storage
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protect - enable or disable FLASH write protection
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|
|
|
@ -960,6 +960,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \
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dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
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dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
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dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
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dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
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|
|
179
arch/arm/dts/ast2600-evb.dts
Normal file
179
arch/arm/dts/ast2600-evb.dts
Normal file
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@ -0,0 +1,179 @@
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// SPDX-License-Identifier: GPL-2.0+
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/dts-v1/;
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#include "ast2600-u-boot.dtsi"
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/ {
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memory {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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};
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chosen {
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stdout-path = &uart5;
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};
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aliases {
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mmc0 = &emmc_slot0;
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mmc1 = &sdhci_slot0;
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mmc2 = &sdhci_slot1;
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spi0 = &fmc;
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spi1 = &spi1;
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spi2 = &spi2;
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ethernet0 = &mac0;
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ethernet1 = &mac1;
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ethernet2 = &mac2;
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ethernet3 = &mac3;
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};
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cpus {
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cpu@0 {
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clock-frequency = <800000000>;
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};
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cpu@1 {
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clock-frequency = <800000000>;
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};
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};
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};
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&uart5 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&sdrammc {
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clock-frequency = <400000000>;
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};
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&wdt1 {
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status = "okay";
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};
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&fmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fmcquad_default>;
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flash@0 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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flash@1 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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flash@2 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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};
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&spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
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&pinctrl_spi1cs1_default &pinctrl_spi1wp_default
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&pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
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flash@0 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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};
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&spi2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
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&pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
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flash@0 {
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compatible = "spi-flash", "sst,w25q256";
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status = "okay";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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};
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&emmc {
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u-boot,dm-pre-reloc;
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timing-phase = <0x700ff>;
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};
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&emmc_slot0 {
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u-boot,dm-pre-reloc;
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status = "okay";
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc_default>;
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sdhci-drive-type = <1>;
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};
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&i2c4 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c5_default>;
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||||
};
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&i2c5 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c6_default>;
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};
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&i2c6 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c7_default>;
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};
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&i2c7 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c8_default>;
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};
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&i2c8 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c9_default>;
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};
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&scu {
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mac0-clk-delay = <0x1d 0x1c
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0x10 0x17
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0x10 0x17>;
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mac1-clk-delay = <0x1d 0x10
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0x10 0x10
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0x10 0x10>;
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mac2-clk-delay = <0x0a 0x04
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0x08 0x04
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0x08 0x04>;
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mac3-clk-delay = <0x0a 0x04
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0x08 0x04
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0x08 0x04>;
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};
|
44
arch/arm/dts/ast2600-u-boot.dtsi
Normal file
44
arch/arm/dts/ast2600-u-boot.dtsi
Normal file
|
@ -0,0 +1,44 @@
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|||
// SPDX-License-Identifier: GPL-2.0+
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#include <dt-bindings/clock/ast2600-clock.h>
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#include <dt-bindings/reset/ast2600-reset.h>
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#include "ast2600.dtsi"
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/ {
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scu: clock-controller@1e6e2000 {
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compatible = "aspeed,ast2600-scu";
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reg = <0x1e6e2000 0x1000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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#reset-cells = <1>;
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uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/
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};
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rst: reset-controller {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2600-reset";
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aspeed,wdt = <&wdt1>;
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#reset-cells = <1>;
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};
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sdrammc: sdrammc@1e6e0000 {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2600-sdrammc";
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reg = <0x1e6e0000 0x100
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0x1e6e0100 0x300
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0x1e6e0400 0x200 >;
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#reset-cells = <1>;
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clocks = <&scu ASPEED_CLK_MPLL>;
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resets = <&rst ASPEED_RESET_SDRAM>;
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};
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ahb {
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u-boot,dm-pre-reloc;
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apb {
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u-boot,dm-pre-reloc;
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};
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};
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};
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|
1946
arch/arm/dts/ast2600.dtsi
Normal file
1946
arch/arm/dts/ast2600.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
@ -52,6 +52,20 @@
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clock-frequency = <400000>;
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};
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nand: nand-controller@f4324000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cortina,ca-nand";
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reg = <0 0xf4324000 0x3b0>, /* NAND controller */
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<0 0xf7001000 0xb4>, /* DMA_GLOBAL */
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<0 0xf7001a00 0x80>; /* DMA channel0 for FLASH */
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status = "okay";
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nand-ecc-mode = "hw";
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nand-ecc-strength = <16>;
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nand-ecc-step-size = <1024>; /* Must be 1024 */
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nand_flash_base_addr = <0xe0000000>;
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};
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sflash: sflash-controller@f4324000 {
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#address-cells = <2>;
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#size-cells = <1>;
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|
|
|
@ -71,16 +71,10 @@
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compatible = "mediatek,timer";
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reg = <0x10004000 0x80>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>;
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clocks = <&infracfg CLK_INFRA_APXGPT_PD>;
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clock-names = "system-clk";
|
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};
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|
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
|
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infracfg: infracfg@10000000 {
|
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compatible = "mediatek,mt7622-infracfg",
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"syscon";
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|
|
|
@ -108,3 +108,13 @@
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&watchdog {
|
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status = "okay";
|
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};
|
||||
|
||||
&usb0 {
|
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status = "okay";
|
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dr_mode = "peripheral";
|
||||
|
||||
usb_con_c: connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -123,6 +123,20 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb0: usb@11100000 {
|
||||
compatible = "mediatek,mt8516-musb",
|
||||
"mediatek,mt8518-musb";
|
||||
reg = <0x11100000 0x1000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "mc";
|
||||
clocks = <&topckgen CLK_TOP_USB_PHY48M>,
|
||||
<&topckgen_cg CLK_TOP_USBIF>,
|
||||
<&topckgen_cg CLK_TOP_USB>,
|
||||
<&topckgen_cg CLK_TOP_USB_1P>;
|
||||
clock-names = "usbpll", "usbmcu", "usb", "icusb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@11005000 {
|
||||
compatible = "mediatek,hsuart";
|
||||
reg = <0x11005000 0x1000>;
|
||||
|
|
0
arch/arm/include/asm/acpi_table.h
Normal file
0
arch/arm/include/asm/acpi_table.h
Normal file
23
arch/arm/include/asm/arch-aspeed/boot0.h
Normal file
23
arch/arm/include/asm/arch-aspeed/boot0.h
Normal file
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) Aspeed Technology Inc.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_BOOT0_H
|
||||
#define _ASM_ARCH_BOOT0_H
|
||||
|
||||
_start:
|
||||
ARM_VECTORS
|
||||
|
||||
.word 0x0 /* key location */
|
||||
.word 0x0 /* start address of image */
|
||||
.word 0xfc00 /* maximum image size: 63KB */
|
||||
.word 0x0 /* signature address */
|
||||
.word 0x0 /* header revision ID low */
|
||||
.word 0x0 /* header revision ID high */
|
||||
.word 0x0 /* reserved */
|
||||
.word 0x0 /* checksum */
|
||||
.word 0x0 /* BL2 secure header */
|
||||
.word 0x0 /* public key or digest offset for BL2 */
|
||||
|
||||
#endif
|
|
@ -13,6 +13,11 @@
|
|||
#define ASPEED_DRAM_BASE 0x80000000
|
||||
#define ASPEED_SRAM_BASE 0x1e720000
|
||||
#define ASPEED_SRAM_SIZE 0x9000
|
||||
#elif defined(CONFIG_ASPEED_AST2600)
|
||||
#define ASPEED_MAC_COUNT 4
|
||||
#define ASPEED_DRAM_BASE 0x80000000
|
||||
#define ASPEED_SRAM_BASE 0x10000000
|
||||
#define ASPEED_SRAM_SIZE 0x10000
|
||||
#else
|
||||
#err "Unrecognized Aspeed platform."
|
||||
#endif
|
||||
|
|
338
arch/arm/include/asm/arch-aspeed/scu_ast2600.h
Normal file
338
arch/arm/include/asm/arch-aspeed/scu_ast2600.h
Normal file
|
@ -0,0 +1,338 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) Aspeed Technology Inc.
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SCU_AST2600_H
|
||||
#define _ASM_ARCH_SCU_AST2600_H
|
||||
|
||||
#define SCU_UNLOCK_KEY 0x1688a8a8
|
||||
|
||||
#define SCU_CLKGATE1_EMMC BIT(27)
|
||||
#define SCU_CLKGATE1_MAC2 BIT(21)
|
||||
#define SCU_CLKGATE1_MAC1 BIT(20)
|
||||
#define SCU_CLKGATE1_USB_HUB BIT(14)
|
||||
#define SCU_CLKGATE1_USB_HOST2 BIT(7)
|
||||
|
||||
#define SCU_CLKGATE2_FSI BIT(30)
|
||||
#define SCU_CLKGATE2_MAC4 BIT(21)
|
||||
#define SCU_CLKGATE2_MAC3 BIT(20)
|
||||
#define SCU_CLKGATE2_SDIO BIT(4)
|
||||
|
||||
#define SCU_DRAM_HDSHK_SOC_INIT BIT(7)
|
||||
#define SCU_DRAM_HDSHK_RDY BIT(6)
|
||||
|
||||
#define SCU_CLKSRC1_ECC_RSA_DIV_MASK GENMASK(27, 26)
|
||||
#define SCU_CLKSRC1_ECC_RSA_DIV_SHIFT 26
|
||||
#define SCU_CLKSRC1_PCLK_DIV_MASK GENMASK(25, 23)
|
||||
#define SCU_CLKSRC1_PCLK_DIV_SHIFT 23
|
||||
#define SCU_CLKSRC1_BCLK_DIV_MASK GENMASK(22, 20)
|
||||
#define SCU_CLKSRC1_BCLK_DIV_SHIFT 20
|
||||
#define SCU_CLKSRC1_ECC_RSA BIT(19)
|
||||
#define SCU_CLKSRC1_MAC_DIV_MASK GENMASK(18, 16)
|
||||
#define SCU_CLKSRC1_MAC_DIV_SHIFT 16
|
||||
#define SCU_CLKSRC1_EMMC_EN BIT(15)
|
||||
#define SCU_CLKSRC1_EMMC_DIV_MASK GENMASK(14, 12)
|
||||
#define SCU_CLKSRC1_EMMC_DIV_SHIFT 12
|
||||
#define SCU_CLKSRC1_EMMC BIT(11)
|
||||
|
||||
#define SCU_CLKSRC2_RMII12 BIT(19)
|
||||
#define SCU_CLKSRC2_RMII12_DIV_MASK GENMASK(18, 16)
|
||||
#define SCU_CLKSRC2_RMII12_DIV_SHIFT 16
|
||||
#define SCU_CLKSRC2_UART5 BIT(14)
|
||||
|
||||
#define SCU_CLKSRC4_SDIO_EN BIT(31)
|
||||
#define SCU_CLKSRC4_SDIO_DIV_MASK GENMASK(30, 28)
|
||||
#define SCU_CLKSRC4_SDIO_DIV_SHIFT 28
|
||||
#define SCU_CLKSRC4_MAC_DIV_MASK GENMASK(26, 24)
|
||||
#define SCU_CLKSRC4_MAC_DIV_SHIFT 24
|
||||
#define SCU_CLKSRC4_RMII34_DIV_MASK GENMASK(18, 16)
|
||||
#define SCU_CLKSRC4_RMII34_DIV_SHIFT 16
|
||||
#define SCU_CLKSRC4_PCLK_DIV_MASK GENMASK(11, 9)
|
||||
#define SCU_CLKSRC4_PCLK_DIV_SHIFT 9
|
||||
#define SCU_CLKSRC4_SDIO BIT(8)
|
||||
#define SCU_CLKSRC4_UART6 BIT(5)
|
||||
#define SCU_CLKSRC4_UART4 BIT(3)
|
||||
#define SCU_CLKSRC4_UART3 BIT(2)
|
||||
#define SCU_CLKSRC4_UART2 BIT(1)
|
||||
#define SCU_CLKSRC4_UART1 BIT(0)
|
||||
|
||||
#define SCU_CLKSRC5_UART13 BIT(12)
|
||||
#define SCU_CLKSRC5_UART12 BIT(11)
|
||||
#define SCU_CLKSRC5_UART11 BIT(10)
|
||||
#define SCU_CLKSRC5_UART10 BIT(9)
|
||||
#define SCU_CLKSRC5_UART9 BIT(8)
|
||||
#define SCU_CLKSRC5_UART8 BIT(7)
|
||||
#define SCU_CLKSRC5_UART7 BIT(6)
|
||||
#define SCU_CLKSRC5_HUXCLK_MASK GENMASK(5, 3)
|
||||
#define SCU_CLKSRC5_HUXCLK_SHIFT 3
|
||||
#define SCU_CLKSRC5_UXCLK_MASK GENMASK(2, 0)
|
||||
#define SCU_CLKSRC5_UXCLK_SHIFT 0
|
||||
|
||||
#define SCU_PINCTRL1_EMMC_MASK GENMASK(31, 24)
|
||||
#define SCU_PINCTRL1_EMMC_SHIFT 24
|
||||
|
||||
#define SCU_PINCTRL16_MAC4_DRIVING_MASK GENMASK(3, 2)
|
||||
#define SCU_PINCTRL16_MAC4_DRIVING_SHIFT 2
|
||||
#define SCU_PINCTRL16_MAC3_DRIVING_MASK GENMASK(1, 0)
|
||||
#define SCU_PINCTRL16_MAC3_DRIVING_SHIFT 0
|
||||
|
||||
#define SCU_HWSTRAP1_CPU_AXI_CLK_RATIO BIT(16)
|
||||
#define SCU_HWSTRAP1_VGA_MEM_MASK GENMASK(14, 13)
|
||||
#define SCU_HWSTRAP1_VGA_MEM_SHIFT 13
|
||||
#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK GENMASK(12, 11)
|
||||
#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT 11
|
||||
#define SCU_HWSTRAP1_CPU_FREQ_MASK GENMASK(10, 8)
|
||||
#define SCU_HWSTRAP1_CPU_FREQ_SHIFT 8
|
||||
#define SCU_HWSTRAP1_MAC2_INTF BIT(7)
|
||||
#define SCU_HWSTRAP1_MAC1_INTF BIT(6)
|
||||
|
||||
#define SCU_EFUSE_DIS_DP BIT(17)
|
||||
#define SCU_EFUSE_DIS_VGA BIT(14)
|
||||
#define SCU_EFUSE_DIS_PCIE_EP BIT(13)
|
||||
#define SCU_EFUSE_DIS_USB BIT(12)
|
||||
#define SCU_EFUSE_DIS_RVAS BIT(10)
|
||||
#define SCU_EFUSE_DIS_VIDEO_DEC BIT(9)
|
||||
#define SCU_EFUSE_DIS_VIDEO BIT(8)
|
||||
#define SCU_EFUSE_DIS_PCIE_RC BIT(7)
|
||||
#define SCU_EFUSE_DIS_CM3 BIT(6)
|
||||
#define SCU_EFUSE_DIS_CA7 BIT(5)
|
||||
|
||||
#define SCU_PLL_RST BIT(25)
|
||||
#define SCU_PLL_BYPASS BIT(24)
|
||||
#define SCU_PLL_OFF BIT(23)
|
||||
#define SCU_PLL_DIV_MASK GENMASK(22, 19)
|
||||
#define SCU_PLL_DIV_SHIFT 19
|
||||
#define SCU_PLL_DENUM_MASK GENMASK(18, 13)
|
||||
#define SCU_PLL_DENUM_SHIFT 13
|
||||
#define SCU_PLL_NUM_MASK GENMASK(12, 0)
|
||||
#define SCU_PLL_NUM_SHIFT 0
|
||||
|
||||
#define SCU_UART_CLKGEN_N_MASK GENMASK(17, 8)
|
||||
#define SCU_UART_CLKGEN_N_SHIFT 8
|
||||
#define SCU_UART_CLKGEN_R_MASK GENMASK(7, 0)
|
||||
#define SCU_UART_CLKGEN_R_SHIFT 0
|
||||
|
||||
#define SCU_HUART_CLKGEN_N_MASK GENMASK(17, 8)
|
||||
#define SCU_HUART_CLKGEN_N_SHIFT 8
|
||||
#define SCU_HUART_CLKGEN_R_MASK GENMASK(7, 0)
|
||||
#define SCU_HUART_CLKGEN_R_SHIFT 0
|
||||
|
||||
#define SCU_MISC_CTRL1_UART5_DIV BIT(12)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct ast2600_scu {
|
||||
uint32_t prot_key1; /* 0x000 */
|
||||
uint32_t chip_id1; /* 0x004 */
|
||||
uint32_t rsv_0x08; /* 0x008 */
|
||||
uint32_t rsv_0x0c; /* 0x00C */
|
||||
uint32_t prot_key2; /* 0x010 */
|
||||
uint32_t chip_id2; /* 0x014 */
|
||||
uint32_t rsv_0x18[10]; /* 0x018 ~ 0x03C */
|
||||
uint32_t modrst_ctrl1; /* 0x040 */
|
||||
uint32_t modrst_clr1; /* 0x044 */
|
||||
uint32_t rsv_0x48; /* 0x048 */
|
||||
uint32_t rsv_0x4C; /* 0x04C */
|
||||
uint32_t modrst_ctrl2; /* 0x050 */
|
||||
uint32_t modrst_clr2; /* 0x054 */
|
||||
uint32_t rsv_0x58; /* 0x058 */
|
||||
uint32_t rsv_0x5C; /* 0x05C */
|
||||
uint32_t extrst_sel1; /* 0x060 */
|
||||
uint32_t sysrst_sts1_1; /* 0x064 */
|
||||
uint32_t sysrst_sts1_2; /* 0x068 */
|
||||
uint32_t sysrst_sts1_3; /* 0x06C */
|
||||
uint32_t extrst_sel2; /* 0x070 */
|
||||
uint32_t sysrst_sts2_1; /* 0x074 */
|
||||
uint32_t sysrst_sts2_2; /* 0x078 */
|
||||
uint32_t stsrst_sts3_2; /* 0x07C */
|
||||
uint32_t clkgate_ctrl1; /* 0x080 */
|
||||
uint32_t clkgate_clr1; /* 0x084 */
|
||||
uint32_t rsv_0x88; /* 0x088 */
|
||||
uint32_t rsv_0x8C; /* 0x08C */
|
||||
uint32_t clkgate_ctrl2; /* 0x090 */
|
||||
uint32_t clkgate_clr2; /* 0x094 */
|
||||
uint32_t rsv_0x98[10]; /* 0x098 ~ 0x0BC */
|
||||
uint32_t misc_ctrl1; /* 0x0C0 */
|
||||
uint32_t misc_ctrl2; /* 0x0C4 */
|
||||
uint32_t debug_ctrl1; /* 0x0C8 */
|
||||
uint32_t rsv_0xCC; /* 0x0CC */
|
||||
uint32_t misc_ctrl3; /* 0x0D0 */
|
||||
uint32_t misc_ctrl4; /* 0x0D4 */
|
||||
uint32_t debug_ctrl2; /* 0x0D8 */
|
||||
uint32_t rsv_0xdc[9]; /* 0x0DC ~ 0x0FC */
|
||||
uint32_t dram_hdshk; /* 0x100 */
|
||||
uint32_t soc_scratch[3]; /* 0x104 ~ 0x10C */
|
||||
uint32_t rsv_0x110[4]; /* 0x110 ~ 0x11C*/
|
||||
uint32_t cpu_scratch_wp; /* 0x120 */
|
||||
uint32_t rsv_0x124[23]; /* 0x124 */
|
||||
uint32_t smp_boot[12]; /* 0x180 */
|
||||
uint32_t cpu_scratch[20]; /* 0x1b0 */
|
||||
uint32_t hpll; /* 0x200 */
|
||||
uint32_t hpll_ext; /* 0x204 */
|
||||
uint32_t rsv_0x208[2]; /* 0x208 ~ 0x20C */
|
||||
uint32_t apll; /* 0x210 */
|
||||
uint32_t apll_ext; /* 0x214 */
|
||||
uint32_t rsv_0x218[2]; /* 0x218 ~ 0x21C */
|
||||
uint32_t mpll; /* 0x220 */
|
||||
uint32_t mpll_ext; /* 0x224 */
|
||||
uint32_t rsv_0x228[6]; /* 0x228 ~ 0x23C */
|
||||
uint32_t epll; /* 0x240 */
|
||||
uint32_t epll_ext; /* 0x244 */
|
||||
uint32_t rsv_0x248[6]; /* 0x248 ~ 0x25C */
|
||||
uint32_t dpll; /* 0x260 */
|
||||
uint32_t dpll_ext; /* 0x264 */
|
||||
uint32_t rsv_0x268[38]; /* 0x268 ~ 0x2FC */
|
||||
uint32_t clksrc1; /* 0x300 */
|
||||
uint32_t clksrc2; /* 0x304 */
|
||||
uint32_t clksrc3; /* 0x308 */
|
||||
uint32_t rsv_0x30c; /* 0x30C */
|
||||
uint32_t clksrc4; /* 0x310 */
|
||||
uint32_t clksrc5; /* 0x314 */
|
||||
uint32_t rsv_0x318[2]; /* 0x318 ~ 0x31C */
|
||||
uint32_t freq_counter_ctrl1; /* 0x320 */
|
||||
uint32_t freq_counter_cmp1; /* 0x324 */
|
||||
uint32_t rsv_0x328[2]; /* 0x328 ~ 0x32C */
|
||||
uint32_t freq_counter_ctrl2; /* 0x330 */
|
||||
uint32_t freq_counter_cmp2; /* 0x334 */
|
||||
uint32_t uart_clkgen; /* 0x338 */
|
||||
uint32_t huart_clkgen; /* 0x33C */
|
||||
uint32_t mac12_clk_delay; /* 0x340 */
|
||||
uint32_t rsv_0x344; /* 0x344 */
|
||||
uint32_t mac12_clk_delay_100M; /* 0x348 */
|
||||
uint32_t mac12_clk_delay_10M; /* 0x34C */
|
||||
uint32_t mac34_clk_delay; /* 0x350 */
|
||||
uint32_t rsv_0x354; /* 0x354 */
|
||||
uint32_t mac34_clk_delay_100M; /* 0x358 */
|
||||
uint32_t mac34_clk_delay_10M; /* 0x35C */
|
||||
uint32_t clkduty_meas_ctrl; /* 0x360 */
|
||||
uint32_t clkduty1; /* 0x364 */
|
||||
uint32_t clkduty2; /* 0x368 */
|
||||
uint32_t clkduty_meas_res; /* 0x36C */
|
||||
uint32_t clkduty_meas_ctrl2; /* 0x370 */
|
||||
uint32_t clkduty3; /* 0x374 */
|
||||
uint32_t rsv_0x378[34]; /* 0x378 ~ 0x3FC */
|
||||
uint32_t pinmux1; /* 0x400 */
|
||||
uint32_t pinmux2; /* 0x404 */
|
||||
uint32_t rsv_0x408; /* 0x408 */
|
||||
uint32_t pinmux3; /* 0x40C */
|
||||
uint32_t pinmux4; /* 0x410 */
|
||||
uint32_t pinmux5; /* 0x414 */
|
||||
uint32_t pinmux6; /* 0x418 */
|
||||
uint32_t pinmux7; /* 0x41C */
|
||||
uint32_t rsv_0x420[4]; /* 0x420 ~ 0x42C */
|
||||
uint32_t pinmux8; /* 0x430 */
|
||||
uint32_t pinmux9; /* 0x434 */
|
||||
uint32_t pinmux10; /* 0x438 */
|
||||
uint32_t rsv_0x43c; /* 0x43C */
|
||||
uint32_t pinmux12; /* 0x440 */
|
||||
uint32_t pinmux13; /* 0x444 */
|
||||
uint32_t rsv_0x448[2]; /* 0x448 ~ 0x44C */
|
||||
uint32_t pinmux14; /* 0x450 */
|
||||
uint32_t pinmux15; /* 0x454 */
|
||||
uint32_t pinmux16; /* 0x458 */
|
||||
uint32_t rsv_0x45c[21]; /* 0x45C ~ 0x4AC */
|
||||
uint32_t pinmux17; /* 0x4B0 */
|
||||
uint32_t pinmux18; /* 0x4B4 */
|
||||
uint32_t pinmux19; /* 0x4B8 */
|
||||
uint32_t pinmux20; /* 0x4BC */
|
||||
uint32_t rsv_0x4c0[5]; /* 0x4C0 ~ 0x4D0 */
|
||||
uint32_t pinmux22; /* 0x4D4 */
|
||||
uint32_t pinmux23; /* 0x4D8 */
|
||||
uint32_t rsv_0x4dc[9]; /* 0x4DC ~ 0x4FC */
|
||||
uint32_t hwstrap1; /* 0x500 */
|
||||
uint32_t hwstrap_clr1; /* 0x504 */
|
||||
uint32_t hwstrap_prot1; /* 0x508 */
|
||||
uint32_t rsv_0x50c; /* 0x50C */
|
||||
uint32_t hwstrap2; /* 0x510 */
|
||||
uint32_t hwstrap_clr2; /* 0x514 */
|
||||
uint32_t hwstrap_prot2; /* 0x518 */
|
||||
uint32_t rsv_0x51c; /* 0x51C */
|
||||
uint32_t rng_ctrl; /* 0x520 */
|
||||
uint32_t rng_data; /* 0x524 */
|
||||
uint32_t rsv_0x528[6]; /* 0x528 ~ 0x53C */
|
||||
uint32_t pwr_save_wakeup_en1; /* 0x540 */
|
||||
uint32_t pwr_save_wakeup_ctrl1; /* 0x544 */
|
||||
uint32_t rsv_0x548[2]; /* 0x548 */
|
||||
uint32_t pwr_save_wakeup_en2; /* 0x550 */
|
||||
uint32_t pwr_save_wakeup_ctrl2; /* 0x554 */
|
||||
uint32_t rsv_0x558[2]; /* 0x558 */
|
||||
uint32_t intr1_ctrl_sts; /* 0x560 */
|
||||
uint32_t rsv_0x564[3]; /* 0x564 */
|
||||
uint32_t intr2_ctrl_sts; /* 0x570 */
|
||||
uint32_t rsv_0x574[7]; /* 0x574 ~ 0x58C */
|
||||
uint32_t otp_ctrl; /* 0x590 */
|
||||
uint32_t efuse; /* 0x594 */
|
||||
uint32_t rsv_0x598[6]; /* 0x598 */
|
||||
uint32_t chip_unique_id[8]; /* 0x5B0 */
|
||||
uint32_t rsv_0x5e0[8]; /* 0x5E0 ~ 0x5FC */
|
||||
uint32_t disgpio_in_pull_down0; /* 0x610 */
|
||||
uint32_t disgpio_in_pull_down1; /* 0x614 */
|
||||
uint32_t disgpio_in_pull_down2; /* 0x618 */
|
||||
uint32_t disgpio_in_pull_down3; /* 0x61C */
|
||||
uint32_t rsv_0x620[4]; /* 0x620 ~ 0x62C */
|
||||
uint32_t disgpio_in_pull_down4; /* 0x630 */
|
||||
uint32_t disgpio_in_pull_down5; /* 0x634 */
|
||||
uint32_t disgpio_in_pull_down6; /* 0x638 */
|
||||
uint32_t rsv_0x63c[5]; /* 0x63C ~ 0x64C */
|
||||
uint32_t sli_driving_strength; /* 0x650 */
|
||||
uint32_t rsv_0x654[107]; /* 0x654 ~ 0x7FC */
|
||||
uint32_t ca7_ctrl1; /* 0x800 */
|
||||
uint32_t ca7_ctrl2; /* 0x804 */
|
||||
uint32_t ca7_ctrl3; /* 0x808 */
|
||||
uint32_t ca7_ctrl4; /* 0x80C */
|
||||
uint32_t rsv_0x810[4]; /* 0x810 ~ 0x81C */
|
||||
uint32_t ca7_parity_chk; /* 0x820 */
|
||||
uint32_t ca7_parity_clr; /* 0x824 */
|
||||
uint32_t rsv_0x828[118]; /* 0x828 ~ 0x9FC */
|
||||
uint32_t cm3_ctrl; /* 0xA00 */
|
||||
uint32_t cm3_base; /* 0xA04 */
|
||||
uint32_t cm3_imem_addr; /* 0xA08 */
|
||||
uint32_t cm3_dmem_addr; /* 0xA0C */
|
||||
uint32_t rsv_0xa10[12]; /* 0xA10 ~ 0xA3C */
|
||||
uint32_t cm3_cache_area; /* 0xA40 */
|
||||
uint32_t cm3_cache_invd_ctrl; /* 0xA44 */
|
||||
uint32_t cm3_cache_func_ctrl; /* 0xA48 */
|
||||
uint32_t rsv_0xa4c[108]; /* 0xA4C ~ 0xBFC */
|
||||
uint32_t pci_cfg[3]; /* 0xC00 */
|
||||
uint32_t rsv_0xc0c[5]; /* 0xC0C ~ 0xC1C */
|
||||
uint32_t pcie_cfg; /* 0xC20 */
|
||||
uint32_t mmio_decode; /* 0xC24 */
|
||||
uint32_t reloc_ctrl_decode[2]; /* 0xC28 */
|
||||
uint32_t rsv_0xc30[4]; /* 0xC30 ~ 0xC3C */
|
||||
uint32_t mbox_decode; /* 0xC40 */
|
||||
uint32_t shared_sram_decode[2]; /* 0xC44 */
|
||||
uint32_t bmc_rev_id; /* 0xC4C */
|
||||
uint32_t rsv_0xc50[5]; /* 0xC50 ~ 0xC60 */
|
||||
uint32_t bmc_device_id; /* 0xC64 */
|
||||
uint32_t rsv_0xc68[102]; /* 0xC68 ~ 0xDFC */
|
||||
uint32_t vga_scratch1; /* 0xE00 */
|
||||
uint32_t vga_scratch2; /* 0xE04 */
|
||||
uint32_t vga_scratch3; /* 0xE08 */
|
||||
uint32_t vga_scratch4; /* 0xE0C */
|
||||
uint32_t rsv_0xe10[4]; /* 0xE10 ~ 0xE1C */
|
||||
uint32_t vga_scratch5; /* 0xE20 */
|
||||
uint32_t vga_scratch6; /* 0xE24 */
|
||||
uint32_t vga_scratch7; /* 0xE28 */
|
||||
uint32_t vga_scratch8; /* 0xE2C */
|
||||
uint32_t rsv_0xe30[52]; /* 0xE30 ~ 0xEFC */
|
||||
uint32_t wr_prot1; /* 0xF00 */
|
||||
uint32_t wr_prot2; /* 0xF04 */
|
||||
uint32_t wr_prot3; /* 0xF08 */
|
||||
uint32_t wr_prot4; /* 0xF0C */
|
||||
uint32_t wr_prot5; /* 0xF10 */
|
||||
uint32_t wr_prot6; /* 0xF18 */
|
||||
uint32_t wr_prot7; /* 0xF1C */
|
||||
uint32_t wr_prot8; /* 0xF20 */
|
||||
uint32_t wr_prot9; /* 0xF24 */
|
||||
uint32_t rsv_0xf28[2]; /* 0xF28 ~ 0xF2C */
|
||||
uint32_t wr_prot10; /* 0xF30 */
|
||||
uint32_t wr_prot11; /* 0xF34 */
|
||||
uint32_t wr_prot12; /* 0xF38 */
|
||||
uint32_t wr_prot13; /* 0xF3C */
|
||||
uint32_t wr_prot14; /* 0xF40 */
|
||||
uint32_t rsv_0xf44; /* 0xF44 */
|
||||
uint32_t wr_prot15; /* 0xF48 */
|
||||
uint32_t rsv_0xf4c[5]; /* 0xF4C ~ 0xF5C */
|
||||
uint32_t wr_prot16; /* 0xF60 */
|
||||
};
|
||||
#endif
|
||||
#endif
|
163
arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
Normal file
163
arch/arm/include/asm/arch-aspeed/sdram_ast2600.h
Normal file
|
@ -0,0 +1,163 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) Aspeed Technology Inc.
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SDRAM_AST2600_H
|
||||
#define _ASM_ARCH_SDRAM_AST2600_H
|
||||
|
||||
/* keys for unlocking HW */
|
||||
#define SDRAM_UNLOCK_KEY 0xFC600309
|
||||
#define SDRAM_VIDEO_UNLOCK_KEY 0x00440003
|
||||
|
||||
/* Fixed priority DRAM Requests mask */
|
||||
#define REQ_PRI_VGA_HW_CURSOR_R 0
|
||||
#define REQ_PRI_VGA_CRT_R 1
|
||||
#define REQ_PRI_SOC_DISPLAY_CTRL_R 2
|
||||
#define REQ_PRI_PCIE_BUS1_RW 3
|
||||
#define REQ_PRI_VIDEO_HIGH_PRI_W 4
|
||||
#define REQ_PRI_CPU_RW 5
|
||||
#define REQ_PRI_SLI_RW 6
|
||||
#define REQ_PRI_PCIE_BUS2_RW 7
|
||||
#define REQ_PRI_USB2_0_HUB_EHCI1_DMA_RW 8
|
||||
#define REQ_PRI_USB2_0_DEV_EHCI2_DMA_RW 9
|
||||
#define REQ_PRI_USB1_1_UHCI_HOST_RW 10
|
||||
#define REQ_PRI_AHB_BUS_RW 11
|
||||
#define REQ_PRI_CM3_DATA_RW 12
|
||||
#define REQ_PRI_CM3_INST_R 13
|
||||
#define REQ_PRI_MAC0_DMA_RW 14
|
||||
#define REQ_PRI_MAC1_DMA_RW 15
|
||||
#define REQ_PRI_SDIO_DMA_RW 16
|
||||
#define REQ_PRI_PILOT_ENGINE_RW 17
|
||||
#define REQ_PRI_XDMA1_RW 18
|
||||
#define REQ_PRI_MCTP1_RW 19
|
||||
#define REQ_PRI_VIDEO_FLAG_RW 20
|
||||
#define REQ_PRI_VIDEO_LOW_PRI_W 21
|
||||
#define REQ_PRI_2D_ENGINE_DATA_RW 22
|
||||
#define REQ_PRI_ENC_ENGINE_RW 23
|
||||
#define REQ_PRI_MCTP2_RW 24
|
||||
#define REQ_PRI_XDMA2_RW 25
|
||||
#define REQ_PRI_ECC_RSA_RW 26
|
||||
|
||||
#define MCR30_RESET_DLL_DELAY_EN BIT(4)
|
||||
#define MCR30_MODE_REG_SEL_SHIFT 1
|
||||
#define MCR30_MODE_REG_SEL_MASK GENMASK(3, 1)
|
||||
#define MCR30_SET_MODE_REG BIT(0)
|
||||
|
||||
#define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_SHIFT) | MCR30_SET_MODE_REG)
|
||||
|
||||
#define MCR34_SELF_REFRESH_STATUS_MASK GENMASK(30, 28)
|
||||
|
||||
#define MCR34_ODT_DELAY_SHIFT 12
|
||||
#define MCR34_ODT_DELAY_MASK GENMASK(15, 12)
|
||||
#define MCR34_ODT_EXT_SHIFT 10
|
||||
#define MCR34_ODT_EXT_MASK GENMASK(11, 10)
|
||||
#define MCR34_ODT_AUTO_ON BIT(9)
|
||||
#define MCR34_ODT_EN BIT(8)
|
||||
#define MCR34_RESETN_DIS BIT(7)
|
||||
#define MCR34_MREQI_DIS BIT(6)
|
||||
#define MCR34_MREQ_BYPASS_DIS BIT(5)
|
||||
#define MCR34_RGAP_CTRL_EN BIT(4)
|
||||
#define MCR34_CKE_OUT_IN_SELF_REF_DIS BIT(3)
|
||||
#define MCR34_FOURCE_SELF_REF_EN BIT(2)
|
||||
#define MCR34_AUTOPWRDN_EN BIT(1)
|
||||
#define MCR34_CKE_EN BIT(0)
|
||||
|
||||
#define MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT 16
|
||||
#define MCR38_RW_MAX_GRANT_CNT_RQ_MASK GENMASK(20, 16)
|
||||
|
||||
/* default request queued limitation mask (0xFFBBFFF4) */
|
||||
#define MCR3C_DEFAULT_MASK \
|
||||
~(REQ_PRI_VGA_HW_CURSOR_R | REQ_PRI_VGA_CRT_R | REQ_PRI_PCIE_BUS1_RW | \
|
||||
REQ_PRI_XDMA1_RW | REQ_PRI_2D_ENGINE_DATA_RW)
|
||||
|
||||
#define MCR50_RESET_ALL_INTR BIT(31)
|
||||
#define SDRAM_CONF_ECC_AUTO_SCRUBBING BIT(9)
|
||||
#define SDRAM_CONF_SCRAMBLE BIT(8)
|
||||
#define SDRAM_CONF_ECC_EN BIT(7)
|
||||
#define SDRAM_CONF_DUALX8 BIT(5)
|
||||
#define SDRAM_CONF_DDR4 BIT(4)
|
||||
#define SDRAM_CONF_VGA_SIZE_SHIFT 2
|
||||
#define SDRAM_CONF_VGA_SIZE_MASK GENMASK(3, 2)
|
||||
#define SDRAM_CONF_CAP_SHIFT 0
|
||||
#define SDRAM_CONF_CAP_MASK GENMASK(1, 0)
|
||||
|
||||
#define SDRAM_CONF_CAP_256M 0
|
||||
#define SDRAM_CONF_CAP_512M 1
|
||||
#define SDRAM_CONF_CAP_1024M 2
|
||||
#define SDRAM_CONF_CAP_2048M 3
|
||||
#define SDRAM_CONF_ECC_SETUP (SDRAM_CONF_ECC_AUTO_SCRUBBING | SDRAM_CONF_ECC_EN)
|
||||
|
||||
#define SDRAM_MISC_DDR4_TREFRESH (1 << 3)
|
||||
|
||||
#define SDRAM_PHYCTRL0_PLL_LOCKED BIT(4)
|
||||
#define SDRAM_PHYCTRL0_NRST BIT(2)
|
||||
#define SDRAM_PHYCTRL0_INIT BIT(0)
|
||||
|
||||
/* MCR0C */
|
||||
#define SDRAM_REFRESH_PERIOD_ZQCS_SHIFT 16
|
||||
#define SDRAM_REFRESH_PERIOD_ZQCS_MASK GENMASK(31, 16)
|
||||
#define SDRAM_REFRESH_PERIOD_SHIFT 8
|
||||
#define SDRAM_REFRESH_PERIOD_MASK GENMASK(15, 8)
|
||||
#define SDRAM_REFRESH_ZQCS_EN BIT(7)
|
||||
#define SDRAM_RESET_DLL_ZQCL_EN BIT(6)
|
||||
#define SDRAM_LOW_PRI_REFRESH_EN BIT(5)
|
||||
#define SDRAM_FORCE_PRECHARGE_EN BIT(4)
|
||||
#define SDRAM_REFRESH_EN BIT(0)
|
||||
|
||||
#define SDRAM_TEST_LEN_SHIFT 4
|
||||
#define SDRAM_TEST_LEN_MASK 0xfffff
|
||||
#define SDRAM_TEST_START_ADDR_SHIFT 24
|
||||
#define SDRAM_TEST_START_ADDR_MASK 0x3f
|
||||
|
||||
#define SDRAM_TEST_EN (1 << 0)
|
||||
#define SDRAM_TEST_MODE_SHIFT 1
|
||||
#define SDRAM_TEST_MODE_MASK (0x3 << SDRAM_TEST_MODE_SHIFT)
|
||||
#define SDRAM_TEST_MODE_WO (0x0 << SDRAM_TEST_MODE_SHIFT)
|
||||
#define SDRAM_TEST_MODE_RB (0x1 << SDRAM_TEST_MODE_SHIFT)
|
||||
#define SDRAM_TEST_MODE_RW (0x2 << SDRAM_TEST_MODE_SHIFT)
|
||||
|
||||
#define SDRAM_TEST_GEN_MODE_SHIFT 3
|
||||
#define SDRAM_TEST_GEN_MODE_MASK (7 << SDRAM_TEST_GEN_MODE_SHIFT)
|
||||
#define SDRAM_TEST_TWO_MODES (1 << 6)
|
||||
#define SDRAM_TEST_ERRSTOP (1 << 7)
|
||||
#define SDRAM_TEST_DONE (1 << 12)
|
||||
#define SDRAM_TEST_FAIL (1 << 13)
|
||||
|
||||
#define SDRAM_AC_TRFC_SHIFT 0
|
||||
#define SDRAM_AC_TRFC_MASK 0xff
|
||||
|
||||
#define SDRAM_ECC_RANGE_ADDR_MASK GENMASK(30, 20)
|
||||
#define SDRAM_ECC_RANGE_ADDR_SHIFT 20
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct ast2600_sdrammc_regs {
|
||||
u32 protection_key; /* offset 0x00 */
|
||||
u32 config; /* offset 0x04 */
|
||||
u32 gm_protection_key; /* offset 0x08 */
|
||||
u32 refresh_timing; /* offset 0x0C */
|
||||
u32 ac_timing[4]; /* offset 0x10 ~ 0x1C */
|
||||
u32 mr01_mode_setting; /* offset 0x20 */
|
||||
u32 mr23_mode_setting; /* offset 0x24 */
|
||||
u32 mr45_mode_setting; /* offset 0x28 */
|
||||
u32 mr6_mode_setting; /* offset 0x2C */
|
||||
u32 mode_setting_control; /* offset 0x30 */
|
||||
u32 power_ctrl; /* offset 0x34 */
|
||||
u32 arbitration_ctrl; /* offset 0x38 */
|
||||
u32 req_limit_mask; /* offset 0x3C */
|
||||
u32 max_grant_len[4]; /* offset 0x40 ~ 0x4C */
|
||||
u32 intr_ctrl; /* offset 0x50 */
|
||||
u32 ecc_range_ctrl; /* offset 0x54 */
|
||||
u32 first_ecc_err_addr; /* offset 0x58 */
|
||||
u32 last_ecc_err_addr; /* offset 0x5C */
|
||||
u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */
|
||||
u32 ecc_test_ctrl; /* offset 0x70 */
|
||||
u32 test_addr; /* offset 0x74 */
|
||||
u32 test_fail_dq_bit; /* offset 0x78 */
|
||||
u32 test_init_val; /* offset 0x7C */
|
||||
u32 req_input_ctrl; /* offset 0x80 */
|
||||
u32 req_high_pri_ctrl; /* offset 0x84 */
|
||||
u32 reserved0[6]; /* offset 0x88 ~ 0x9C */
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_ARCH_SDRAM_AST2600_H */
|
129
arch/arm/include/asm/arch-aspeed/wdt_ast2600.h
Normal file
129
arch/arm/include/asm/arch-aspeed/wdt_ast2600.h
Normal file
|
@ -0,0 +1,129 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2020 Aspeed Technology Inc.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_WDT_AST2600_H
|
||||
#define _ASM_ARCH_WDT_AST2600_H
|
||||
|
||||
#define WDT_BASE 0x1e785000
|
||||
|
||||
/*
|
||||
* Special value that needs to be written to counter_restart register to
|
||||
* (re)start the timer
|
||||
*/
|
||||
#define WDT_COUNTER_RESTART_VAL 0x4755
|
||||
|
||||
/* reset mode */
|
||||
#define WDT_RESET_MODE_SOC 0
|
||||
#define WDT_RESET_MODE_CHIP 1
|
||||
#define WDT_RESET_MODE_CPU 2
|
||||
|
||||
/* bit-fields of WDT control register */
|
||||
#define WDT_CTRL_2ND_BOOT BIT(7)
|
||||
#define WDT_CTRL_RESET_MODE_MASK GENMASK(6, 5)
|
||||
#define WDT_CTRL_RESET_MODE_SHIFT 5
|
||||
#define WDT_CTRL_CLK1MHZ BIT(4)
|
||||
#define WDT_CTRL_RESET BIT(1)
|
||||
#define WDT_CTRL_EN BIT(0)
|
||||
|
||||
/* bit-fields of WDT reset mask1 register */
|
||||
#define WDT_RESET_MASK1_RVAS BIT(25)
|
||||
#define WDT_RESET_MASK1_GPIO1 BIT(24)
|
||||
#define WDT_RESET_MASK1_XDMA2 BIT(23)
|
||||
#define WDT_RESET_MASK1_XDMA1 BIT(22)
|
||||
#define WDT_RESET_MASK1_MCTP2 BIT(21)
|
||||
#define WDT_RESET_MASK1_MCTP1 BIT(20)
|
||||
#define WDT_RESET_MASK1_JTAG1 BIT(19)
|
||||
#define WDT_RESET_MASK1_SD_SDIO1 BIT(18)
|
||||
#define WDT_RESET_MASK1_MAC2 BIT(17)
|
||||
#define WDT_RESET_MASK1_MAC1 BIT(16)
|
||||
#define WDT_RESET_MASK1_GPMCU BIT(15)
|
||||
#define WDT_RESET_MASK1_DPMCU BIT(14)
|
||||
#define WDT_RESET_MASK1_DP BIT(13)
|
||||
#define WDT_RESET_MASK1_HAC BIT(12)
|
||||
#define WDT_RESET_MASK1_VIDEO BIT(11)
|
||||
#define WDT_RESET_MASK1_CRT BIT(10)
|
||||
#define WDT_RESET_MASK1_GCRT BIT(9)
|
||||
#define WDT_RESET_MASK1_USB11_UHCI BIT(8)
|
||||
#define WDT_RESET_MASK1_USB_PORTA BIT(7)
|
||||
#define WDT_RESET_MASK1_USB_PORTB BIT(6)
|
||||
#define WDT_RESET_MASK1_COPROC BIT(5)
|
||||
#define WDT_RESET_MASK1_SOC BIT(4)
|
||||
#define WDT_RESET_MASK1_SLI BIT(3)
|
||||
#define WDT_RESET_MASK1_AHB BIT(2)
|
||||
#define WDT_RESET_MASK1_SDRAM BIT(1)
|
||||
#define WDT_RESET_MASK1_ARM BIT(0)
|
||||
|
||||
/* bit-fields of WDT reset mask2 register */
|
||||
#define WDT_RESET_MASK2_ESPI BIT(26)
|
||||
#define WDT_RESET_MASK2_I3C_BUS8 BIT(25)
|
||||
#define WDT_RESET_MASK2_I3C_BUS7 BIT(24)
|
||||
#define WDT_RESET_MASK2_I3C_BUS6 BIT(23)
|
||||
#define WDT_RESET_MASK2_I3C_BUS5 BIT(22)
|
||||
#define WDT_RESET_MASK2_I3C_BUS4 BIT(21)
|
||||
#define WDT_RESET_MASK2_I3C_BUS3 BIT(20)
|
||||
#define WDT_RESET_MASK2_I3C_BUS2 BIT(19)
|
||||
#define WDT_RESET_MASK2_I3C_BUS1 BIT(18)
|
||||
#define WDT_RESET_MASK2_I3C_GLOBAL BIT(17)
|
||||
#define WDT_RESET_MASK2_I2C BIT(16)
|
||||
#define WDT_RESET_MASK2_FSI BIT(15)
|
||||
#define WDT_RESET_MASK2_ADC BIT(14)
|
||||
#define WDT_RESET_MASK2_PWM BIT(13)
|
||||
#define WDT_RESET_MASK2_PECI BIT(12)
|
||||
#define WDT_RESET_MASK2_LPC BIT(11)
|
||||
#define WDT_RESET_MASK2_MDC_MDIO BIT(10)
|
||||
#define WDT_RESET_MASK2_GPIO2 BIT(9)
|
||||
#define WDT_RESET_MASK2_JTAG2 BIT(8)
|
||||
#define WDT_RESET_MASK2_SD_SDIO2 BIT(7)
|
||||
#define WDT_RESET_MASK2_MAC4 BIT(6)
|
||||
#define WDT_RESET_MASK2_MAC3 BIT(5)
|
||||
#define WDT_RESET_MASK2_SOC BIT(4)
|
||||
#define WDT_RESET_MASK2_SLI2 BIT(3)
|
||||
#define WDT_RESET_MASK2_AHB2 BIT(2)
|
||||
#define WDT_RESET_MASK2_SPI1_SPI2 BIT(1)
|
||||
#define WDT_RESET_MASK2_ARM BIT(0)
|
||||
|
||||
#define WDT_RESET_MASK1_DEFAULT \
|
||||
(WDT_RESET_MASK1_RVAS | WDT_RESET_MASK1_GPIO1 | \
|
||||
WDT_RESET_MASK1_JTAG1 | WDT_RESET_MASK1_SD_SDIO1 | \
|
||||
WDT_RESET_MASK1_MAC2 | WDT_RESET_MASK1_MAC1 | \
|
||||
WDT_RESET_MASK1_HAC | WDT_RESET_MASK1_VIDEO | \
|
||||
WDT_RESET_MASK1_CRT | WDT_RESET_MASK1_GCRT | \
|
||||
WDT_RESET_MASK1_USB11_UHCI | WDT_RESET_MASK1_USB_PORTA | \
|
||||
WDT_RESET_MASK1_USB_PORTB | WDT_RESET_MASK1_COPROC | \
|
||||
WDT_RESET_MASK1_SOC | WDT_RESET_MASK1_ARM)
|
||||
|
||||
#define WDT_RESET_MASK2_DEFAULT \
|
||||
(WDT_RESET_MASK2_I3C_BUS8 | WDT_RESET_MASK2_I3C_BUS7 | \
|
||||
WDT_RESET_MASK2_I3C_BUS6 | WDT_RESET_MASK2_I3C_BUS5 | \
|
||||
WDT_RESET_MASK2_I3C_BUS4 | WDT_RESET_MASK2_I3C_BUS3 | \
|
||||
WDT_RESET_MASK2_I3C_BUS2 | WDT_RESET_MASK2_I3C_BUS1 | \
|
||||
WDT_RESET_MASK2_I3C_GLOBAL | WDT_RESET_MASK2_I2C | \
|
||||
WDT_RESET_MASK2_FSI | WDT_RESET_MASK2_ADC | \
|
||||
WDT_RESET_MASK2_PWM | WDT_RESET_MASK2_PECI | \
|
||||
WDT_RESET_MASK2_LPC | WDT_RESET_MASK2_MDC_MDIO | \
|
||||
WDT_RESET_MASK2_GPIO2 | WDT_RESET_MASK2_JTAG2 | \
|
||||
WDT_RESET_MASK2_SD_SDIO2 | WDT_RESET_MASK2_MAC4 | \
|
||||
WDT_RESET_MASK2_MAC3 | WDT_RESET_MASK2_SOC | \
|
||||
WDT_RESET_MASK2_ARM)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct ast2600_wdt {
|
||||
u32 counter_status;
|
||||
u32 counter_reload_val;
|
||||
u32 counter_restart;
|
||||
u32 ctrl;
|
||||
u32 timeout_status;
|
||||
u32 clr_timeout_status;
|
||||
u32 reset_width;
|
||||
u32 reset_mask1;
|
||||
u32 reset_mask2;
|
||||
u32 sw_reset_ctrl;
|
||||
u32 sw_reset_mask1;
|
||||
u32 sw_reset_mask2;
|
||||
u32 sw_reset_disable;
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _ASM_ARCH_WDT_AST2600_H */
|
|
@ -3,7 +3,8 @@
|
|||
!defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
|
||||
!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
|
||||
!defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \
|
||||
!defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE)
|
||||
!defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \
|
||||
!defined(CONFIG_ARCH_QEMU)
|
||||
#include <asm/arch/gpio.h>
|
||||
#endif
|
||||
#include <asm-generic/gpio.h>
|
||||
|
|
|
@ -9,6 +9,11 @@ config SYS_SOC
|
|||
config SYS_TEXT_BASE
|
||||
default 0x00000000
|
||||
|
||||
choice
|
||||
prompt "Aspeed SoC select"
|
||||
depends on ARCH_ASPEED
|
||||
default ASPEED_AST2500
|
||||
|
||||
config ASPEED_AST2500
|
||||
bool "Support Aspeed AST2500 SoC"
|
||||
depends on DM_RESET
|
||||
|
@ -18,6 +23,21 @@ config ASPEED_AST2500
|
|||
It is used as Board Management Controller on many server boards,
|
||||
which is enabled by support of LPC and eSPI peripherals.
|
||||
|
||||
config ASPEED_AST2600
|
||||
bool "Support Aspeed AST2600 SoC"
|
||||
select CPU_V7A
|
||||
select CPU_V7_HAS_NONSEC
|
||||
select SYS_ARCH_TIMER
|
||||
select SUPPORT_SPL
|
||||
select ENABLE_ARM_SOC_BOOT0_HOOK
|
||||
help
|
||||
The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU.
|
||||
It is used as Board Management Controller on many server boards,
|
||||
which is enabled by support of LPC and eSPI peripherals.
|
||||
|
||||
endchoice
|
||||
|
||||
source "arch/arm/mach-aspeed/ast2500/Kconfig"
|
||||
source "arch/arm/mach-aspeed/ast2600/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
@ -4,3 +4,4 @@
|
|||
|
||||
obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o
|
||||
obj-$(CONFIG_ASPEED_AST2500) += ast2500/
|
||||
obj-$(CONFIG_ASPEED_AST2600) += ast2600/
|
||||
|
|
17
arch/arm/mach-aspeed/ast2600/Kconfig
Normal file
17
arch/arm/mach-aspeed/ast2600/Kconfig
Normal file
|
@ -0,0 +1,17 @@
|
|||
if ASPEED_AST2600
|
||||
|
||||
config SYS_CPU
|
||||
default "armv7"
|
||||
|
||||
config TARGET_EVB_AST2600
|
||||
bool "EVB-AST2600"
|
||||
depends on ASPEED_AST2600
|
||||
help
|
||||
EVB-AST2600 is Aspeed evaluation board for AST2600A0 chip.
|
||||
It has 512M of RAM, 32M of SPI flash, two Ethernet ports,
|
||||
4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot,
|
||||
20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs.
|
||||
|
||||
source "board/aspeed/evb_ast2600/Kconfig"
|
||||
|
||||
endif
|
2
arch/arm/mach-aspeed/ast2600/Makefile
Normal file
2
arch/arm/mach-aspeed/ast2600/Makefile
Normal file
|
@ -0,0 +1,2 @@
|
|||
obj-y += lowlevel_init.o board_common.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
105
arch/arm/mach-aspeed/ast2600/board_common.c
Normal file
105
arch/arm/mach-aspeed/ast2600/board_common.c
Normal file
|
@ -0,0 +1,105 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) Aspeed Technology Inc.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <ram.h>
|
||||
#include <timer.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/timer.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/err.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <asm/arch/scu_ast2600.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* Memory Control registers */
|
||||
#define MCR_BASE 0x1e6e0000
|
||||
#define MCR_CONF (MCR_BASE + 0x004)
|
||||
|
||||
/* bit fields of MCR_CONF */
|
||||
#define MCR_CONF_ECC_EN BIT(7)
|
||||
#define MCR_CONF_VGA_MEMSZ_MASK GENMASK(3, 2)
|
||||
#define MCR_CONF_VGA_MEMSZ_SHIFT 2
|
||||
#define MCR_CONF_MEMSZ_MASK GENMASK(1, 0)
|
||||
#define MCR_CONF_MEMSZ_SHIFT 0
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
int ret;
|
||||
struct udevice *dev;
|
||||
struct ram_info ram;
|
||||
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||
if (ret) {
|
||||
debug("cannot get DRAM driver\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ram_get_info(dev, &ram);
|
||||
if (ret) {
|
||||
debug("cannot get DRAM information\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
gd->ram_size = ram.size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
int i = 0, rc;
|
||||
struct udevice *dev;
|
||||
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
while (1) {
|
||||
rc = uclass_get_device(UCLASS_MISC, i++, &dev);
|
||||
if (rc)
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_add_ram_info(int use_default)
|
||||
{
|
||||
int rc;
|
||||
uint32_t conf;
|
||||
uint32_t ecc, act_size, vga_rsvd;
|
||||
struct udevice *scu_dev;
|
||||
struct ast2600_scu *scu;
|
||||
|
||||
rc = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
|
||||
if (rc) {
|
||||
debug("%s: cannot find SCU device, rc=%d\n", __func__, rc);
|
||||
return;
|
||||
}
|
||||
|
||||
scu = devfdt_get_addr_ptr(scu_dev);
|
||||
if (IS_ERR_OR_NULL(scu)) {
|
||||
debug("%s: cannot get SCU address pointer\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
conf = readl(MCR_CONF);
|
||||
|
||||
ecc = conf & MCR_CONF_ECC_EN;
|
||||
act_size = 0x100 << ((conf & MCR_CONF_MEMSZ_MASK) >> MCR_CONF_MEMSZ_SHIFT);
|
||||
vga_rsvd = 0x8 << ((conf & MCR_CONF_VGA_MEMSZ_MASK) >> MCR_CONF_VGA_MEMSZ_SHIFT);
|
||||
|
||||
/* no VGA reservation if efuse VGA disable bit is set */
|
||||
if (readl(scu->efuse) & SCU_EFUSE_DIS_VGA)
|
||||
vga_rsvd = 0;
|
||||
|
||||
printf(" (capacity:%d MiB, VGA:%d MiB), ECC %s", act_size,
|
||||
vga_rsvd, (ecc) ? "on" : "off");
|
||||
}
|
||||
|
||||
void enable_caches(void)
|
||||
{
|
||||
/* get rid of the warning message */
|
||||
}
|
233
arch/arm/mach-aspeed/ast2600/lowlevel_init.S
Normal file
233
arch/arm/mach-aspeed/ast2600/lowlevel_init.S
Normal file
|
@ -0,0 +1,233 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) ASPEED Technology Inc.
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <asm/armv7.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/arch/scu_ast2600.h>
|
||||
|
||||
/* SCU register offsets */
|
||||
#define SCU_BASE 0x1e6e2000
|
||||
#define SCU_PROT_KEY1 (SCU_BASE + 0x000)
|
||||
#define SCU_PROT_KEY2 (SCU_BASE + 0x010)
|
||||
#define SCU_SMP_BOOT (SCU_BASE + 0x180)
|
||||
#define SCU_HWSTRAP1 (SCU_BASE + 0x510)
|
||||
#define SCU_CA7_PARITY_CHK (SCU_BASE + 0x820)
|
||||
#define SCU_CA7_PARITY_CLR (SCU_BASE + 0x824)
|
||||
#define SCU_MMIO_DEC (SCU_BASE + 0xc24)
|
||||
|
||||
/* FMC SPI register offsets */
|
||||
#define FMC_BASE 0x1e620000
|
||||
#define FMC_CE0_CTRL (FMC_BASE + 0x010)
|
||||
#define FMC_SW_RST_CTRL (FMC_BASE + 0x050)
|
||||
#define FMC_WDT1_CTRL_MODE (FMC_BASE + 0x060)
|
||||
#define FMC_WDT2_CTRL_MODE (FMC_BASE + 0x064)
|
||||
|
||||
/*
|
||||
* The SMP mailbox provides a space with few instructions in it
|
||||
* for secondary cores to execute on and wait for the signal of
|
||||
* SMP core bring up.
|
||||
*
|
||||
* SMP mailbox
|
||||
* +----------------------+
|
||||
* | |
|
||||
* | mailbox insn. for |
|
||||
* | cpuN polling SMP go |
|
||||
* | |
|
||||
* +----------------------+ 0xC
|
||||
* | mailbox ready signal |
|
||||
* +----------------------+ 0x8
|
||||
* | cpuN GO signal |
|
||||
* +----------------------+ 0x4
|
||||
* | cpuN entrypoint |
|
||||
* +----------------------+ SMP_MAILBOX_BASE
|
||||
*/
|
||||
#define SMP_MBOX_BASE (SCU_SMP_BOOT)
|
||||
#define SMP_MBOX_FIELD_ENTRY (SMP_MBOX_BASE + 0x0)
|
||||
#define SMP_MBOX_FIELD_GOSIGN (SMP_MBOX_BASE + 0x4)
|
||||
#define SMP_MBOX_FIELD_READY (SMP_MBOX_BASE + 0x8)
|
||||
#define SMP_MBOX_FIELD_POLLINSN (SMP_MBOX_BASE + 0xc)
|
||||
|
||||
.macro scu_unlock
|
||||
movw r0, #(SCU_UNLOCK_KEY & 0xffff)
|
||||
movt r0, #(SCU_UNLOCK_KEY >> 16)
|
||||
|
||||
ldr r1, =SCU_PROT_KEY1
|
||||
str r0, [r1]
|
||||
ldr r1, =SCU_PROT_KEY2
|
||||
str r0, [r1]
|
||||
.endm
|
||||
|
||||
.macro timer_init
|
||||
ldr r1, =SCU_HWSTRAP1
|
||||
ldr r1, [r1]
|
||||
and r1, #0x700
|
||||
lsr r1, #0x8
|
||||
|
||||
/* 1.2GHz */
|
||||
cmp r1, #0x0
|
||||
movweq r0, #0x8c00
|
||||
movteq r0, #0x4786
|
||||
|
||||
/* 1.6GHz */
|
||||
cmp r1, #0x1
|
||||
movweq r0, #0x1000
|
||||
movteq r0, #0x5f5e
|
||||
|
||||
/* 1.2GHz */
|
||||
cmp r1, #0x2
|
||||
movweq r0, #0x8c00
|
||||
movteq r0, #0x4786
|
||||
|
||||
/* 1.6GHz */
|
||||
cmp r1, #0x3
|
||||
movweq r0, #0x1000
|
||||
movteq r0, #0x5f5e
|
||||
|
||||
/* 800MHz */
|
||||
cmp r1, #0x4
|
||||
movwge r0, #0x0800
|
||||
movtge r0, #0x2faf
|
||||
|
||||
mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ
|
||||
.endm
|
||||
|
||||
|
||||
.globl lowlevel_init
|
||||
|
||||
lowlevel_init:
|
||||
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
|
||||
mov pc, lr
|
||||
#else
|
||||
/* setup ARM arch timer frequency */
|
||||
timer_init
|
||||
|
||||
/* reset SMP mailbox as early as possible */
|
||||
mov r0, #0x0
|
||||
ldr r1, =SMP_MBOX_FIELD_READY
|
||||
str r0, [r1]
|
||||
|
||||
/* set ACTLR.SMP to enable cache use */
|
||||
mrc p15, 0, r0, c1, c0, 1
|
||||
orr r0, #0x40
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
|
||||
/*
|
||||
* we treat cpu0 as the primary core and
|
||||
* put secondary core (cpuN) to sleep
|
||||
*/
|
||||
mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register
|
||||
ands r0, #0xff @; Mask off, leaving the CPU ID field
|
||||
movw r2, #0xab00
|
||||
movt r2, #0xabba
|
||||
orr r2, r0
|
||||
|
||||
beq do_primary_core_setup
|
||||
|
||||
/* hold cpuN until mailbox is ready */
|
||||
poll_mailbox_ready:
|
||||
wfe
|
||||
ldr r0, =SMP_MBOX_FIELD_READY
|
||||
ldr r0, [r0]
|
||||
movw r1, #0xcafe
|
||||
movt r1, #0xbabe
|
||||
cmp r1, r0
|
||||
bne poll_mailbox_ready
|
||||
|
||||
/* parameters for relocated SMP go polling insn. */
|
||||
ldr r0, =SMP_MBOX_FIELD_GOSIGN
|
||||
ldr r1, =SMP_MBOX_FIELD_ENTRY
|
||||
|
||||
/* no return */
|
||||
ldr pc, =SMP_MBOX_FIELD_POLLINSN
|
||||
|
||||
do_primary_core_setup:
|
||||
scu_unlock
|
||||
|
||||
/* MMIO decode setting */
|
||||
ldr r0, =SCU_MMIO_DEC
|
||||
mov r1, #0x2000
|
||||
str r1, [r0]
|
||||
|
||||
/* enable CA7 cache parity check */
|
||||
mov r0, #0
|
||||
ldr r1, =SCU_CA7_PARITY_CLR
|
||||
str r0, [r1]
|
||||
|
||||
mov r0, #0x1
|
||||
ldr r1, =SCU_CA7_PARITY_CHK
|
||||
str r0, [r1]
|
||||
|
||||
/* do not fill FMC50[1] if boot from eMMC */
|
||||
ldr r0, =SCU_HWSTRAP1
|
||||
ldr r1, [r0]
|
||||
ands r1, #0x04
|
||||
bne skip_fill_wip_bit
|
||||
|
||||
/* fill FMC50[1] for waiting WIP idle */
|
||||
mov r0, #0x02
|
||||
ldr r1, =FMC_SW_RST_CTRL
|
||||
str r0, [r1]
|
||||
|
||||
skip_fill_wip_bit:
|
||||
/* disable FMC WDT for SPI address mode detection */
|
||||
mov r0, #0
|
||||
ldr r1, =FMC_WDT1_CTRL_MODE
|
||||
str r0, [r1]
|
||||
|
||||
/* relocate mailbox insn. for cpuN polling SMP go signal */
|
||||
adrl r0, mailbox_insn
|
||||
adrl r1, mailbox_insn_end
|
||||
|
||||
ldr r2, =#SMP_MBOX_FIELD_POLLINSN
|
||||
|
||||
relocate_mailbox_insn:
|
||||
ldr r3, [r0], #0x4
|
||||
str r3, [r2], #0x4
|
||||
cmp r0, r1
|
||||
bne relocate_mailbox_insn
|
||||
|
||||
/* reset SMP go sign */
|
||||
mov r0, #0
|
||||
ldr r1, =SMP_MBOX_FIELD_GOSIGN
|
||||
str r0, [r1]
|
||||
|
||||
/* notify cpuN mailbox is ready */
|
||||
movw r0, #0xCAFE
|
||||
movt r0, #0xBABE
|
||||
ldr r1, =SMP_MBOX_FIELD_READY
|
||||
str r0, [r1]
|
||||
sev
|
||||
|
||||
/* back to arch calling code */
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* insn. inside mailbox to poll SMP go signal.
|
||||
*
|
||||
* Note that as this code will be relocated, any
|
||||
* pc-relative assembly should NOT be used.
|
||||
*/
|
||||
mailbox_insn:
|
||||
/*
|
||||
* r0 ~ r3 are parameters:
|
||||
* r0 = SMP_MBOX_FIELD_GOSIGN
|
||||
* r1 = SMP_MBOX_FIELD_ENTRY
|
||||
* r2 = per-cpu go sign value
|
||||
* r3 = no used now
|
||||
*/
|
||||
poll_mailbox_smp_go:
|
||||
wfe
|
||||
ldr r4, [r0]
|
||||
cmp r2, r4
|
||||
bne poll_mailbox_smp_go
|
||||
|
||||
/* SMP GO signal confirmed, release cpuN */
|
||||
ldr pc, [r1]
|
||||
|
||||
mailbox_insn_end:
|
||||
/* should never reach */
|
||||
b .
|
||||
|
||||
#endif
|
55
arch/arm/mach-aspeed/ast2600/spl.c
Normal file
55
arch/arm/mach-aspeed/ast2600/spl.c
Normal file
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) Aspeed Technology Inc.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <debug_uart.h>
|
||||
#include <dm.h>
|
||||
#include <spl.h>
|
||||
#include <init.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/scu_ast2600.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
spl_early_init();
|
||||
preloader_console_init();
|
||||
timer_init();
|
||||
dram_init();
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return BOOT_DEVICE_RAM;
|
||||
}
|
||||
|
||||
struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
|
||||
{
|
||||
/*
|
||||
* When boot from SPI, AST2600 already remap 0x00000000 ~ 0x0fffffff
|
||||
* to BMC SPI memory space 0x20000000 ~ 0x2fffffff. The next stage BL
|
||||
* has been located in SPI for XIP. In this case, the load buffer for
|
||||
* SPL image loading will be set to the remapped address of the next
|
||||
* BL instead of the DRAM space CONFIG_SYS_LOAD_ADDR
|
||||
*/
|
||||
return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* boot linux */
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
12
board/aspeed/evb_ast2600/Kconfig
Normal file
12
board/aspeed/evb_ast2600/Kconfig
Normal file
|
@ -0,0 +1,12 @@
|
|||
if TARGET_EVB_AST2600
|
||||
|
||||
config SYS_BOARD
|
||||
default "evb_ast2600"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "aspeed"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "evb_ast2600"
|
||||
|
||||
endif
|
6
board/aspeed/evb_ast2600/MAINTAINERS
Normal file
6
board/aspeed/evb_ast2600/MAINTAINERS
Normal file
|
@ -0,0 +1,6 @@
|
|||
EVB AST2600 BOARD
|
||||
M: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
|
||||
S: Maintained
|
||||
F: board/aspeed/evb_ast2600/
|
||||
F: include/configs/evb_ast2600.h
|
||||
F: configs/evb-ast2600_defconfig
|
1
board/aspeed/evb_ast2600/Makefile
Normal file
1
board/aspeed/evb_ast2600/Makefile
Normal file
|
@ -0,0 +1 @@
|
|||
obj-y += evb_ast2600.o
|
5
board/aspeed/evb_ast2600/evb_ast2600.c
Normal file
5
board/aspeed/evb_ast2600/evb_ast2600.c
Normal file
|
@ -0,0 +1,5 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) Aspeed Technology Inc.
|
||||
*/
|
||||
#include <common.h>
|
|
@ -58,8 +58,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
|||
select DM_SERIAL
|
||||
select DM_SPI
|
||||
select DM_SPI_FLASH
|
||||
select USB
|
||||
select USB_EHCI_HCD
|
||||
select USB_EHCI_MARVELL
|
||||
imply CMD_CRAMFS
|
||||
imply CMD_DIAG
|
||||
imply FS_CRAMFS
|
||||
imply CMD_USB
|
||||
|
||||
endif
|
||||
|
|
|
@ -4,8 +4,25 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
if (CONFIG_IS_ENABLED(USB_GADGET)) {
|
||||
ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
|
||||
if (ret) {
|
||||
pr_err("%s: Cannot find USB device\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -928,6 +928,12 @@ config CMD_GPIO
|
|||
help
|
||||
GPIO support.
|
||||
|
||||
config CMD_PWM
|
||||
bool "pwm"
|
||||
depends on DM_PWM
|
||||
help
|
||||
Control PWM channels, this allows invert/config/enable/disable PWM channels.
|
||||
|
||||
config CMD_GPT
|
||||
bool "GPT (GUID Partition Table) command"
|
||||
select EFI_PARTITION
|
||||
|
|
|
@ -120,6 +120,7 @@ endif
|
|||
obj-$(CONFIG_CMD_PINMUX) += pinmux.o
|
||||
obj-$(CONFIG_CMD_PMC) += pmc.o
|
||||
obj-$(CONFIG_CMD_PSTORE) += pstore.o
|
||||
obj-$(CONFIG_CMD_PWM) += pwm.o
|
||||
obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
|
||||
obj-$(CONFIG_CMD_WOL) += wol.o
|
||||
obj-$(CONFIG_CMD_QFW) += qfw.o
|
||||
|
|
117
cmd/pwm.c
Normal file
117
cmd/pwm.c
Normal file
|
@ -0,0 +1,117 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Control PWM channels
|
||||
*
|
||||
* Copyright (c) 2020 SiFive, Inc
|
||||
* author: Pragnesh Patel <pragnesh.patel@sifive.com>
|
||||
*/
|
||||
|
||||
#include <command.h>
|
||||
#include <dm.h>
|
||||
#include <pwm.h>
|
||||
|
||||
enum pwm_cmd {
|
||||
PWM_SET_INVERT,
|
||||
PWM_SET_CONFIG,
|
||||
PWM_SET_ENABLE,
|
||||
PWM_SET_DISABLE,
|
||||
};
|
||||
|
||||
static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
|
||||
const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
|
||||
enum pwm_cmd sub_cmd;
|
||||
struct udevice *dev;
|
||||
u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
|
||||
int ret;
|
||||
|
||||
if (argc < 4)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
str_cmd = argv[1];
|
||||
argc -= 2;
|
||||
argv += 2;
|
||||
|
||||
if (argc > 0) {
|
||||
str_pwm = *argv;
|
||||
argc--;
|
||||
argv++;
|
||||
}
|
||||
|
||||
if (!str_pwm)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
switch (*str_cmd) {
|
||||
case 'i':
|
||||
sub_cmd = PWM_SET_INVERT;
|
||||
break;
|
||||
case 'c':
|
||||
sub_cmd = PWM_SET_CONFIG;
|
||||
break;
|
||||
case 'e':
|
||||
sub_cmd = PWM_SET_ENABLE;
|
||||
break;
|
||||
case 'd':
|
||||
sub_cmd = PWM_SET_DISABLE;
|
||||
break;
|
||||
default:
|
||||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
||||
pwm_dev = simple_strtoul(str_pwm, NULL, 10);
|
||||
ret = uclass_get_device(UCLASS_PWM, pwm_dev, &dev);
|
||||
if (ret) {
|
||||
printf("pwm: '%s' not found\n", str_pwm);
|
||||
return cmd_process_error(cmdtp, ret);
|
||||
}
|
||||
|
||||
if (argc > 0) {
|
||||
str_channel = *argv;
|
||||
channel = simple_strtoul(str_channel, NULL, 10);
|
||||
argc--;
|
||||
argv++;
|
||||
} else {
|
||||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
||||
if (sub_cmd == PWM_SET_INVERT && argc > 0) {
|
||||
str_enable = *argv;
|
||||
pwm_enable = simple_strtoul(str_enable, NULL, 10);
|
||||
ret = pwm_set_invert(dev, channel, pwm_enable);
|
||||
} else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
|
||||
str_period = *argv;
|
||||
argc--;
|
||||
argv++;
|
||||
period_ns = simple_strtoul(str_period, NULL, 10);
|
||||
|
||||
if (argc > 0) {
|
||||
str_duty = *argv;
|
||||
duty_ns = simple_strtoul(str_duty, NULL, 10);
|
||||
}
|
||||
|
||||
ret = pwm_set_config(dev, channel, period_ns, duty_ns);
|
||||
} else if (sub_cmd == PWM_SET_ENABLE) {
|
||||
ret = pwm_set_enable(dev, channel, 1);
|
||||
} else if (sub_cmd == PWM_SET_DISABLE) {
|
||||
ret = pwm_set_enable(dev, channel, 0);
|
||||
} else {
|
||||
printf("PWM arguments missing\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
printf("error(%d)\n", ret);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(pwm, 6, 0, do_pwm,
|
||||
"control pwm channels",
|
||||
"pwm <invert> <pwm_dev_num> <channel> <polarity>\n"
|
||||
"pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns>\n"
|
||||
"pwm <enable/disable> <pwm_dev_num> <channel>\n"
|
||||
"Note: All input values are in decimal");
|
33
configs/cortina_presidio-asic-pnand_defconfig
Normal file
33
configs/cortina_presidio-asic-pnand_defconfig
Normal file
|
@ -0,0 +1,33 @@
|
|||
CONFIG_ARM=y
|
||||
# CONFIG_SYS_ARCH_TIMER is not set
|
||||
CONFIG_TARGET_PRESIDIO_ASIC=y
|
||||
CONFIG_SYS_TEXT_BASE=0x04000000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_IDENT_STRING="Presidio-SoC"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ca-presidio-engboard"
|
||||
CONFIG_SHOW_BOOT_PROGRESS=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="earlycon=serial,0xf4329148 console=ttyS0,115200 root=/dev/ram0"
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SYS_PROMPT="G3#"
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_WDT=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
# CONFIG_NET is not set
|
||||
CONFIG_DM=y
|
||||
CONFIG_CORTINA_GPIO=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_CORTINA_NAND=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_CORTINA_UART=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_CORTINA=y
|
69
configs/evb-ast2600_defconfig
Normal file
69
configs/evb-ast2600_defconfig
Normal file
|
@ -0,0 +1,69 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_ASPEED=y
|
||||
CONFIG_SYS_TEXT_BASE=0x10000
|
||||
CONFIG_ASPEED_AST2600=y
|
||||
CONFIG_TARGET_EVB_AST2600=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x800
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_SIZE_LIMIT=0x10000
|
||||
CONFIG_SPL=y
|
||||
# CONFIG_ARMV7_NONSEC is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb"
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_LEGACY_IMAGE_FORMAT is not set
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="bootm 20100000"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
|
||||
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
|
||||
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_DM_RESET=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SPL_MISC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ASPEED=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_FTGMAC100=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_HEXDUMP=y
|
||||
# CONFIG_SPL_HEXDUMP is not set
|
||||
# CONFIG_EFI_LOADER is not set
|
|
@ -8,7 +8,7 @@ CONFIG_ENV_SIZE=0x2000
|
|||
CONFIG_ENV_OFFSET=0x0
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_ENV_OFFSET_REDUND=0x2000
|
||||
CONFIG_IDENT_STRING="\nKeymile Kirkwood 128M16"
|
||||
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood 128M16"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16"
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
|
@ -17,16 +17,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
|
|||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
|
||||
|
|
|
@ -8,7 +8,7 @@ CONFIG_ENV_SIZE=0x2000
|
|||
CONFIG_ENV_OFFSET=0x0
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_ENV_OFFSET_REDUND=0x2000
|
||||
CONFIG_IDENT_STRING="\nKeymile Kirkwood"
|
||||
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD"
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
|
@ -17,16 +17,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
|
|||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
|
||||
|
|
|
@ -9,7 +9,7 @@ CONFIG_ENV_SIZE=0x2000
|
|||
CONFIG_ENV_OFFSET=0x0
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_ENV_OFFSET_REDUND=0x2000
|
||||
CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI"
|
||||
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood PCI"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI"
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
|
@ -18,16 +18,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
|
|||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
|
||||
|
@ -46,6 +48,7 @@ CONFIG_BOOTCOUNT_RAM=y
|
|||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SF_DEFAULT_SPEED=8100000
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_MVGBE=y
|
||||
CONFIG_MII=y
|
||||
|
|
|
@ -12,7 +12,7 @@ CONFIG_ENV_OFFSET=0xC0000
|
|||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_ENV_OFFSET_REDUND=0xD0000
|
||||
CONFIG_IDENT_STRING="\nKeymile COGE5UN"
|
||||
CONFIG_IDENT_STRING="\nHitachi Power Grids COGE5UN"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN"
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
|
@ -21,16 +21,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
|
|||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
|
||||
|
|
|
@ -12,7 +12,7 @@ CONFIG_ENV_OFFSET=0xC0000
|
|||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_ENV_OFFSET_REDUND=0xD0000
|
||||
CONFIG_IDENT_STRING="\nKeymile NUSA"
|
||||
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA"
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
|
@ -21,16 +21,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
|
|||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
|
||||
|
|
|
@ -13,7 +13,7 @@ CONFIG_ENV_OFFSET=0xC0000
|
|||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_ENV_OFFSET_REDUND=0xD0000
|
||||
CONFIG_IDENT_STRING="\nABB SUSE2"
|
||||
CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="KM_SUSE2"
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
|
@ -22,16 +22,18 @@ CONFIG_AUTOBOOT_STOP_STR=" "
|
|||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_JFFS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);"
|
||||
|
|
|
@ -17,6 +17,7 @@ CONFIG_FIT=y
|
|||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin"
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
|
@ -45,8 +46,13 @@ CONFIG_CMD_PART=y
|
|||
# CONFIG_CMD_SLEEP is not set
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
# CONFIG_NET is not set
|
||||
CONFIG_CLK=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_BUF_ADDR=0x4d000000
|
||||
CONFIG_FASTBOOT_BUF_SIZE=0x4000000
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y
|
||||
# CONFIG_INPUT is not set
|
||||
CONFIG_DM_MMC=y
|
||||
# CONFIG_MMC_QUIRKS is not set
|
||||
|
@ -59,6 +65,13 @@ CONFIG_BAUDRATE=921600
|
|||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_MUSB_GADGET=y
|
||||
CONFIG_USB_MUSB_MT85XX=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x201c
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_MTK=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
@ -58,6 +58,7 @@ CONFIG_CMD_LSBLK=y
|
|||
CONFIG_CMD_MUX=y
|
||||
CONFIG_CMD_OSD=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_PWM=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_REMOTEPROC=y
|
||||
CONFIG_CMD_SPI=y
|
||||
|
|
|
@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware
|
|||
|
||||
Note: builddir is U-Boot build directory (source directory for in-tree builds)
|
||||
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
|
||||
branch: imx_4.19.35_1.0.0
|
||||
branch: imx_5.4.47_2.2.0
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
|
@ -30,10 +30,10 @@ Get the ddr firmware
|
|||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
|
||||
$ chmod +x firmware-imx-8.0.bin
|
||||
$ ./firmware-imx-8.0
|
||||
$ cp firmware-imx-8.0/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
|
||||
$ chmod +x firmware-imx-8.9.bin
|
||||
$ ./firmware-imx-8.9
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
|
|
@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware
|
|||
|
||||
Note: srctree is U-Boot source directory
|
||||
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
|
||||
branch: imx_4.19.35_1.1.0
|
||||
branch: imx_5.4.47_2.2.0
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
|
@ -30,10 +30,10 @@ Get the ddr firmware
|
|||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.5.bin
|
||||
$ chmod +x firmware-imx-8.5.bin
|
||||
$ ./firmware-imx-8.5
|
||||
$ cp firmware-imx-8.5/firmware/ddr/synopsys/ddr4*.bin $(srctree)
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
|
||||
$ chmod +x firmware-imx-8.9.bin
|
||||
$ ./firmware-imx-8.9
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/ddr4*.bin $(srctree)
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
|
|
@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware
|
|||
|
||||
Note: $(srctree) is the U-Boot source directory
|
||||
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
|
||||
branch: imx_5.4.3_2.0.0
|
||||
branch: imx_5.4.47_2.2.0
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
|
@ -30,13 +30,13 @@ Get the ddr firmware
|
|||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin
|
||||
$ chmod +x firmware-imx-8.7.bin
|
||||
$ ./firmware-imx-8.7.bin
|
||||
$ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
|
||||
$ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
|
||||
$ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
|
||||
$ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
|
||||
$ chmod +x firmware-imx-8.9.bin
|
||||
$ ./firmware-imx-8.9.bin
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
|
|
@ -18,7 +18,7 @@ Get and Build the ARM Trusted firmware
|
|||
|
||||
Note: srctree is U-Boot source directory
|
||||
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
|
||||
branch: imx_4.19.35_1.0.0
|
||||
branch: imx_5.4.47_2.2.0
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
|
@ -30,11 +30,11 @@ Get the ddr and hdmi firmware
|
|||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
|
||||
$ chmod +x firmware-imx-7.9.bin
|
||||
$ ./firmware-imx-7.9.bin
|
||||
$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
|
||||
$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
|
||||
$ chmod +x firmware-imx-8.9.bin
|
||||
$ ./firmware-imx-8.9.bin
|
||||
$ cp firmware-imx-8.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
|
|
@ -4,3 +4,4 @@
|
|||
#
|
||||
|
||||
obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o
|
||||
obj-$(CONFIG_ASPEED_AST2600) += clk_ast2600.o
|
||||
|
|
1173
drivers/clk/aspeed/clk_ast2600.c
Normal file
1173
drivers/clk/aspeed/clk_ast2600.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -7,5 +7,6 @@ obj-$(CONFIG_MT8512) += clk-mt8512.o
|
|||
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
|
||||
obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
|
||||
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
|
||||
obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
|
||||
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
|
||||
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
|
||||
|
|
823
drivers/clk/mediatek/clk-mt8183.c
Normal file
823
drivers/clk/mediatek/clk-mt8183.c
Normal file
|
@ -0,0 +1,823 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* MediaTek clock driver for MT8183 SoC
|
||||
*
|
||||
* Copyright (C) 2020 BayLibre, SAS
|
||||
* Copyright (c) 2020 MediaTek Inc.
|
||||
* Author: Fabien Parent <fparent@baylibre.com>
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/io.h>
|
||||
#include <dt-bindings/clock/mt8183-clk.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
|
||||
#define MT8183_PLL_FMAX (3800UL * MHZ)
|
||||
#define MT8183_PLL_FMIN (1500UL * MHZ)
|
||||
|
||||
/* apmixedsys */
|
||||
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, \
|
||||
_pcwibits, _pd_reg, _pd_shift, _pcw_reg, _pcw_shift) { \
|
||||
.id = _id, \
|
||||
.reg = _reg, \
|
||||
.pwr_reg = _pwr_reg, \
|
||||
.en_mask = _en_mask, \
|
||||
.rst_bar_mask = _rst_bar_mask, \
|
||||
.fmax = MT8183_PLL_FMAX, \
|
||||
.fmin = MT8183_PLL_FMIN, \
|
||||
.flags = _flags, \
|
||||
.pcwbits = _pcwbits, \
|
||||
.pcwibits = _pcwibits, \
|
||||
.pd_reg = _pd_reg, \
|
||||
.pd_shift = _pd_shift, \
|
||||
.pcw_reg = _pcw_reg, \
|
||||
.pcw_shift = _pcw_shift, \
|
||||
}
|
||||
|
||||
static const struct mtk_pll_data apmixed_plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL_LL, 0x0200, 0x020C, 0x00000001,
|
||||
HAVE_RST_BAR, BIT(24), 22, 8, 0x0204, 24,
|
||||
0x0204, 0),
|
||||
PLL(CLK_APMIXED_ARMPLL_L, 0x0210, 0x021C, 0x00000001,
|
||||
HAVE_RST_BAR, BIT(24), 22, 8, 0x0214, 24,
|
||||
0x0214, 0),
|
||||
PLL(CLK_APMIXED_CCIPLL, 0x0290, 0x029C, 0x00000001,
|
||||
HAVE_RST_BAR, BIT(24), 22, 8, 0x0294, 24,
|
||||
0x0294, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, 0x0220, 0x022C, 0x00000001,
|
||||
HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24,
|
||||
0x0224, 0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, 0x0230, 0x023C, 0x00000001,
|
||||
HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24,
|
||||
0x0234, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, 0x0250, 0x025C, 0x00000001,
|
||||
0, 0, 22, 8, 0x0254, 24, 0x0254, 0),
|
||||
PLL(CLK_APMIXED_MMPLL, 0x0270, 0x027C, 0x00000001,
|
||||
HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24,
|
||||
0x0274, 0),
|
||||
PLL(CLK_APMIXED_MFGPLL, 0x0240, 0x024C, 0x00000001,
|
||||
0, 0, 22, 8, 0x0244, 24, 0x0244, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, 0x0260, 0x026C, 0x00000001,
|
||||
0, 0, 22, 8, 0x0264, 24, 0x0264, 0),
|
||||
PLL(CLK_APMIXED_APLL1, 0x02A0, 0x02B0, 0x00000001,
|
||||
0, 0, 32, 8, 0x02A0, 1, 0x02A4, 0),
|
||||
PLL(CLK_APMIXED_APLL2, 0x02b4, 0x02c4, 0x00000001,
|
||||
0, 0, 32, 8, 0x02B4, 1, 0x02B8, 0),
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_clk top_fixed_clks[] = {
|
||||
FIXED_CLK(CLK_TOP_CLK26M, CLK_XTAL, 26000000),
|
||||
FIXED_CLK(CLK_TOP_ULPOSC, CLK_XTAL, 250000),
|
||||
FIXED_CLK(CLK_TOP_UNIVP_192M, CLK_TOP_UNIVPLL, 192000000),
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_factor top_fixed_divs[] = {
|
||||
FACTOR(CLK_TOP_CLK13M, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_F26M_CK_D2, CLK_TOP_CLK26M, 1, 2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_CK, CLK_APMIXED_MAINPLL, 1,
|
||||
1, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2, CLK_TOP_SYSPLL_CK, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1,
|
||||
3, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1,
|
||||
5, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1,
|
||||
7, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2_D2, CLK_TOP_SYSPLL_D2, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2_D4, CLK_TOP_SYSPLL_D2, 1,
|
||||
4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2_D8, CLK_TOP_SYSPLL_D2, 1,
|
||||
8, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2_D16, CLK_TOP_SYSPLL_D2, 1,
|
||||
16, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3_D2, CLK_TOP_SYSPLL_D3, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3_D4, CLK_TOP_SYSPLL_D3, 1,
|
||||
4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D3_D8, CLK_TOP_SYSPLL_D3, 1,
|
||||
8, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5_D2, CLK_TOP_SYSPLL_D5, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5_D4, CLK_TOP_SYSPLL_D5, 1,
|
||||
4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D7_D2, CLK_TOP_SYSPLL_D7, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_SYSPLL_D7_D4, CLK_TOP_SYSPLL_D7, 1,
|
||||
4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_CK, CLK_TOP_UNIVPLL, 1, 1, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL_CK, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D2, CLK_TOP_UNIVPLL_D2, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D4, CLK_TOP_UNIVPLL_D2, 1,
|
||||
4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D8, CLK_TOP_UNIVPLL_D2, 1,
|
||||
8, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D2, CLK_TOP_UNIVPLL_D3, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D4, CLK_TOP_UNIVPLL_D3, 1,
|
||||
4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D8, CLK_TOP_UNIVPLL_D3, 1,
|
||||
8, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D2, CLK_TOP_UNIVPLL_D5, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D4, CLK_TOP_UNIVPLL_D5, 1,
|
||||
4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D8, CLK_TOP_UNIVPLL_D5, 1,
|
||||
8, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_CK, CLK_TOP_UNIVP_192M, 1, 1,
|
||||
CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D2, CLK_TOP_UNIVP_192M_CK, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D4, CLK_TOP_UNIVP_192M_CK, 1,
|
||||
4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D8, CLK_TOP_UNIVP_192M_CK, 1,
|
||||
8, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D16, CLK_TOP_UNIVP_192M_CK, 1,
|
||||
16, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVP_192M_D32, CLK_TOP_UNIVP_192M_CK, 1,
|
||||
32, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_APLL1_CK, CLK_APMIXED_APLL1, 1, 1, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_APLL2_CK, CLK_APMIXED_APLL2, 1, 1, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_TVDPLL_CK, CLK_APMIXED_TVDPLL, 1, 1, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL_CK, 1, 2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_TVDPLL_D8, CLK_APMIXED_TVDPLL, 1, 8, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_TVDPLL_D16, CLK_APMIXED_TVDPLL, 1,
|
||||
16, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MMPLL_CK, CLK_APMIXED_MMPLL, 1, 1, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MMPLL_D4, CLK_APMIXED_MMPLL, 1, 4, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MMPLL_D4_D2, CLK_TOP_MMPLL_D4, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_MMPLL_D4_D4, CLK_TOP_MMPLL_D4, 1, 4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_MMPLL_D5, CLK_APMIXED_MMPLL, 1, 5, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MMPLL_D5_D2, CLK_TOP_MMPLL_D5, 1,
|
||||
2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_MMPLL_D5_D4, CLK_TOP_MMPLL_D5, 1,
|
||||
4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_MMPLL_D6, CLK_APMIXED_MMPLL, 1, 6, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MMPLL_D7, CLK_APMIXED_MMPLL, 1, 7, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MFGPLL_CK, CLK_APMIXED_MFGPLL, 1, 1, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MSDCPLL_CK, CLK_APMIXED_MSDCPLL, 1,
|
||||
1, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1,
|
||||
2, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1,
|
||||
4, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1,
|
||||
8, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D16, CLK_APMIXED_MSDCPLL, 1,
|
||||
16, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_AD_OSC_CK, CLK_TOP_ULPOSC, 1, 1, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_OSC_D2, CLK_TOP_ULPOSC, 1, 2, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_OSC_D4, CLK_TOP_ULPOSC, 1, 4, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_OSC_D8, CLK_TOP_ULPOSC, 1, 8, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_OSC_D16, CLK_TOP_ULPOSC, 1, 16, CLK_PARENT_TOPCKGEN),
|
||||
FACTOR(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2, CLK_PARENT_APMIXED),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D16, CLK_TOP_UNIVPLL_D3, 1,
|
||||
16, CLK_PARENT_TOPCKGEN),
|
||||
};
|
||||
|
||||
static const int axi_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2_D4,
|
||||
CLK_TOP_SYSPLL_D7,
|
||||
CLK_TOP_OSC_D4
|
||||
};
|
||||
|
||||
static const int mm_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MMPLL_D7,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2
|
||||
};
|
||||
|
||||
static const int img_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MMPLL_D6,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_UNIVPLL_D3_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2
|
||||
};
|
||||
|
||||
static const int cam_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2,
|
||||
CLK_TOP_MMPLL_D6,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_MMPLL_D7,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2,
|
||||
CLK_TOP_UNIVPLL_D3_D2
|
||||
};
|
||||
|
||||
static const int dsp_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MMPLL_D6,
|
||||
CLK_TOP_MMPLL_D7,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_UNIVPLL_D3_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2
|
||||
};
|
||||
|
||||
static const int dsp1_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MMPLL_D6,
|
||||
CLK_TOP_MMPLL_D7,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_UNIVPLL_D3_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2
|
||||
};
|
||||
|
||||
static const int dsp2_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MMPLL_D6,
|
||||
CLK_TOP_MMPLL_D7,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_UNIVPLL_D3_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2
|
||||
};
|
||||
|
||||
static const int ipu_if_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MMPLL_D6,
|
||||
CLK_TOP_MMPLL_D7,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_UNIVPLL_D3_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2
|
||||
};
|
||||
|
||||
static const int mfg_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MFGPLL_CK,
|
||||
CLK_TOP_UNIVPLL_D3,
|
||||
CLK_TOP_SYSPLL_D3
|
||||
};
|
||||
|
||||
static const int f52m_mfg_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D3_D2,
|
||||
CLK_TOP_UNIVPLL_D3_D4,
|
||||
CLK_TOP_UNIVPLL_D3_D8
|
||||
};
|
||||
|
||||
static const int camtg_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVP_192M_D8,
|
||||
CLK_TOP_UNIVPLL_D3_D8,
|
||||
CLK_TOP_UNIVP_192M_D4,
|
||||
CLK_TOP_UNIVPLL_D3_D16,
|
||||
CLK_TOP_F26M_CK_D2,
|
||||
CLK_TOP_UNIVP_192M_D16,
|
||||
CLK_TOP_UNIVP_192M_D32
|
||||
};
|
||||
|
||||
static const int camtg2_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVP_192M_D8,
|
||||
CLK_TOP_UNIVPLL_D3_D8,
|
||||
CLK_TOP_UNIVP_192M_D4,
|
||||
CLK_TOP_UNIVPLL_D3_D16,
|
||||
CLK_TOP_F26M_CK_D2,
|
||||
CLK_TOP_UNIVP_192M_D16,
|
||||
CLK_TOP_UNIVP_192M_D32
|
||||
};
|
||||
|
||||
static const int camtg3_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVP_192M_D8,
|
||||
CLK_TOP_UNIVPLL_D3_D8,
|
||||
CLK_TOP_UNIVP_192M_D4,
|
||||
CLK_TOP_UNIVPLL_D3_D16,
|
||||
CLK_TOP_F26M_CK_D2,
|
||||
CLK_TOP_UNIVP_192M_D16,
|
||||
CLK_TOP_UNIVP_192M_D32
|
||||
};
|
||||
|
||||
static const int camtg4_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVP_192M_D8,
|
||||
CLK_TOP_UNIVPLL_D3_D8,
|
||||
CLK_TOP_UNIVP_192M_D4,
|
||||
CLK_TOP_UNIVPLL_D3_D16,
|
||||
CLK_TOP_F26M_CK_D2,
|
||||
CLK_TOP_UNIVP_192M_D16,
|
||||
CLK_TOP_UNIVP_192M_D32
|
||||
};
|
||||
|
||||
static const int uart_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D3_D8
|
||||
};
|
||||
|
||||
static const int spi_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D5_D2,
|
||||
CLK_TOP_SYSPLL_D3_D4,
|
||||
CLK_TOP_MSDCPLL_D4
|
||||
};
|
||||
|
||||
static const int msdc50_hclk_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2
|
||||
};
|
||||
|
||||
static const int msdc50_0_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_MSDCPLL_CK,
|
||||
CLK_TOP_MSDCPLL_D2,
|
||||
CLK_TOP_UNIVPLL_D2_D4,
|
||||
CLK_TOP_SYSPLL_D3_D2,
|
||||
CLK_TOP_UNIVPLL_D2_D2
|
||||
};
|
||||
|
||||
static const int msdc30_1_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D3_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2,
|
||||
CLK_TOP_SYSPLL_D7,
|
||||
CLK_TOP_MSDCPLL_D2
|
||||
};
|
||||
|
||||
static const int msdc30_2_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D3_D2,
|
||||
CLK_TOP_SYSPLL_D3_D2,
|
||||
CLK_TOP_SYSPLL_D7,
|
||||
CLK_TOP_MSDCPLL_D2
|
||||
};
|
||||
|
||||
static const int audio_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D5_D4,
|
||||
CLK_TOP_SYSPLL_D7_D4,
|
||||
CLK_TOP_SYSPLL_D2_D16
|
||||
};
|
||||
|
||||
static const int aud_intbus_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2_D4,
|
||||
CLK_TOP_SYSPLL_D7_D2
|
||||
};
|
||||
|
||||
static const int pmicspi_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2_D8,
|
||||
CLK_TOP_OSC_D8
|
||||
};
|
||||
|
||||
static const int fpwrap_ulposc_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_OSC_D16,
|
||||
CLK_TOP_OSC_D4,
|
||||
CLK_TOP_OSC_D8
|
||||
};
|
||||
|
||||
static const int atb_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D5
|
||||
};
|
||||
|
||||
static const int sspm_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D2_D4,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D3
|
||||
};
|
||||
|
||||
static const int dpi0_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_TVDPLL_D2,
|
||||
CLK_TOP_TVDPLL_D4,
|
||||
CLK_TOP_TVDPLL_D8,
|
||||
CLK_TOP_TVDPLL_D16,
|
||||
CLK_TOP_UNIVPLL_D5_D2,
|
||||
CLK_TOP_UNIVPLL_D3_D4,
|
||||
CLK_TOP_SYSPLL_D3_D4,
|
||||
CLK_TOP_UNIVPLL_D3_D8
|
||||
};
|
||||
|
||||
static const int scam_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D5_D2
|
||||
};
|
||||
|
||||
static const int disppwm_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D3_D4,
|
||||
CLK_TOP_OSC_D2,
|
||||
CLK_TOP_OSC_D4,
|
||||
CLK_TOP_OSC_D16
|
||||
};
|
||||
|
||||
static const int usb_top_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D5_D4,
|
||||
CLK_TOP_UNIVPLL_D3_D4,
|
||||
CLK_TOP_UNIVPLL_D5_D2
|
||||
};
|
||||
|
||||
static const int ssusb_top_xhci_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D5_D4,
|
||||
CLK_TOP_UNIVPLL_D3_D4,
|
||||
CLK_TOP_UNIVPLL_D5_D2
|
||||
};
|
||||
|
||||
static const int spm_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2_D8
|
||||
};
|
||||
|
||||
static const int i2c_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2_D8,
|
||||
CLK_TOP_UNIVPLL_D5_D2
|
||||
};
|
||||
|
||||
static const int scp_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D2_D8,
|
||||
CLK_TOP_SYSPLL_D5,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_UNIVPLL_D3
|
||||
};
|
||||
|
||||
static const int seninf_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_UNIVPLL_D2_D2,
|
||||
CLK_TOP_UNIVPLL_D3_D2,
|
||||
CLK_TOP_UNIVPLL_D2_D4
|
||||
};
|
||||
|
||||
static const int dxcc_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D2_D4,
|
||||
CLK_TOP_SYSPLL_D2_D8
|
||||
};
|
||||
|
||||
static const int aud_engen1_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_APLL1_D2,
|
||||
CLK_TOP_APLL1_D4,
|
||||
CLK_TOP_APLL1_D8
|
||||
};
|
||||
|
||||
static const int aud_engen2_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_APLL2_D2,
|
||||
CLK_TOP_APLL2_D4,
|
||||
CLK_TOP_APLL2_D8
|
||||
};
|
||||
|
||||
static const int faes_ufsfde_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2,
|
||||
CLK_TOP_SYSPLL_D2_D2,
|
||||
CLK_TOP_SYSPLL_D3,
|
||||
CLK_TOP_SYSPLL_D2_D4,
|
||||
CLK_TOP_UNIVPLL_D3
|
||||
};
|
||||
|
||||
static const int fufs_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_SYSPLL_D2_D4,
|
||||
CLK_TOP_SYSPLL_D2_D8,
|
||||
CLK_TOP_SYSPLL_D2_D16
|
||||
};
|
||||
|
||||
static const int aud_1_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_APLL1_CK
|
||||
};
|
||||
|
||||
static const int aud_2_parents[] = {
|
||||
CLK_TOP_CLK26M,
|
||||
CLK_TOP_APLL2_CK
|
||||
};
|
||||
|
||||
static const struct mtk_composite top_muxes[] = {
|
||||
/* CLK_CFG_0 */
|
||||
MUX(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2),
|
||||
MUX(CLK_TOP_MUX_MM, mm_parents, 0x40, 8, 3),
|
||||
MUX(CLK_TOP_MUX_IMG, img_parents, 0x40, 16, 3),
|
||||
MUX(CLK_TOP_MUX_CAM, cam_parents, 0x40, 24, 4),
|
||||
/* CLK_CFG_1 */
|
||||
MUX(CLK_TOP_MUX_DSP, dsp_parents, 0x50, 0, 4),
|
||||
MUX(CLK_TOP_MUX_DSP1, dsp1_parents, 0x50, 8, 4),
|
||||
MUX(CLK_TOP_MUX_DSP2, dsp2_parents, 0x50, 16, 4),
|
||||
MUX(CLK_TOP_MUX_IPU_IF, ipu_if_parents, 0x50, 24, 4),
|
||||
/* CLK_CFG_2 */
|
||||
MUX(CLK_TOP_MUX_MFG, mfg_parents, 0x60, 0, 2),
|
||||
MUX(CLK_TOP_MUX_F52M_MFG, f52m_mfg_parents, 0x60, 8, 2),
|
||||
MUX(CLK_TOP_MUX_CAMTG, camtg_parents, 0x60, 16, 3),
|
||||
MUX(CLK_TOP_MUX_CAMTG2, camtg2_parents, 0x60, 24, 3),
|
||||
/* CLK_CFG_3 */
|
||||
MUX(CLK_TOP_MUX_CAMTG3, camtg3_parents, 0x70, 0, 3),
|
||||
MUX(CLK_TOP_MUX_CAMTG4, camtg4_parents, 0x70, 8, 3),
|
||||
MUX(CLK_TOP_MUX_UART, uart_parents, 0x70, 16, 1),
|
||||
MUX(CLK_TOP_MUX_SPI, spi_parents, 0x70, 24, 2),
|
||||
/* CLK_CFG_4 */
|
||||
MUX(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2),
|
||||
MUX(CLK_TOP_MUX_MSDC50_0, msdc50_0_parents, 0x80, 8, 3),
|
||||
MUX(CLK_TOP_MUX_MSDC30_1, msdc30_1_parents, 0x80, 16, 3),
|
||||
MUX(CLK_TOP_MUX_MSDC30_2, msdc30_2_parents, 0x80, 24, 3),
|
||||
/* CLK_CFG_5 */
|
||||
MUX(CLK_TOP_MUX_AUDIO, audio_parents, 0x90, 0, 2),
|
||||
MUX(CLK_TOP_MUX_AUD_INTBUS, aud_intbus_parents, 0x90, 8, 2),
|
||||
MUX(CLK_TOP_MUX_PMICSPI, pmicspi_parents, 0x90, 16, 2),
|
||||
MUX(CLK_TOP_MUX_FPWRAP_ULPOSC, fpwrap_ulposc_parents, 0x90, 24, 2),
|
||||
/* CLK_CFG_6 */
|
||||
MUX(CLK_TOP_MUX_ATB, atb_parents, 0xa0, 0, 2),
|
||||
MUX(CLK_TOP_MUX_SSPM, sspm_parents, 0xa0, 8, 3),
|
||||
MUX(CLK_TOP_MUX_DPI0, dpi0_parents, 0xa0, 16, 4),
|
||||
MUX(CLK_TOP_MUX_SCAM, scam_parents, 0xa0, 24, 1),
|
||||
/* CLK_CFG_7 */
|
||||
MUX(CLK_TOP_MUX_DISP_PWM, disppwm_parents, 0xb0, 0, 3),
|
||||
MUX(CLK_TOP_MUX_USB_TOP, usb_top_parents, 0xb0, 8, 2),
|
||||
MUX(CLK_TOP_MUX_SSUSB_TOP_XHCI, ssusb_top_xhci_parents, 0xb0, 16, 2),
|
||||
MUX(CLK_TOP_MUX_SPM, spm_parents, 0xb0, 24, 1),
|
||||
/* CLK_CFG_8 */
|
||||
MUX(CLK_TOP_MUX_I2C, i2c_parents, 0xc0, 0, 2),
|
||||
MUX(CLK_TOP_MUX_SCP, scp_parents, 0xc0, 8, 3),
|
||||
MUX(CLK_TOP_MUX_SENINF, seninf_parents, 0xc0, 16, 2),
|
||||
MUX(CLK_TOP_MUX_DXCC, dxcc_parents, 0xc0, 24, 2),
|
||||
/* CLK_CFG_9 */
|
||||
MUX(CLK_TOP_MUX_AUD_ENG1, aud_engen1_parents, 0xd0, 0, 2),
|
||||
MUX(CLK_TOP_MUX_AUD_ENG2, aud_engen2_parents, 0xd0, 8, 2),
|
||||
MUX(CLK_TOP_MUX_FAES_UFSFDE, faes_ufsfde_parents, 0xd0, 16, 3),
|
||||
MUX(CLK_TOP_MUX_FUFS, fufs_parents, 0xd0, 24, 2),
|
||||
/* CLK_CFG_10 */
|
||||
MUX(CLK_TOP_MUX_AUD_1, aud_1_parents, 0xe0, 0, 1),
|
||||
MUX(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_tree mt8183_clk_tree = {
|
||||
.xtal_rate = 26 * MHZ,
|
||||
.xtal2_rate = 26 * MHZ,
|
||||
.fdivs_offs = CLK_TOP_CLK13M,
|
||||
.muxes_offs = CLK_TOP_MUX_AXI,
|
||||
.plls = apmixed_plls,
|
||||
.fclks = top_fixed_clks,
|
||||
.fdivs = top_fixed_divs,
|
||||
.muxes = top_muxes,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra0_cg_regs = {
|
||||
.set_ofs = 0x80,
|
||||
.clr_ofs = 0x84,
|
||||
.sta_ofs = 0x90,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra1_cg_regs = {
|
||||
.set_ofs = 0x88,
|
||||
.clr_ofs = 0x8c,
|
||||
.sta_ofs = 0x94,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra2_cg_regs = {
|
||||
.set_ofs = 0xa4,
|
||||
.clr_ofs = 0xa8,
|
||||
.sta_ofs = 0xac,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra3_cg_regs = {
|
||||
.set_ofs = 0xc0,
|
||||
.clr_ofs = 0xc4,
|
||||
.sta_ofs = 0xc8,
|
||||
};
|
||||
|
||||
#define GATE_INFRA0(_id, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.parent = _parent, \
|
||||
.regs = &infra0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
||||
}
|
||||
|
||||
#define GATE_INFRA1(_id, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.parent = _parent, \
|
||||
.regs = &infra1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
||||
}
|
||||
|
||||
#define GATE_INFRA2(_id, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.parent = _parent, \
|
||||
.regs = &infra2_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
||||
}
|
||||
|
||||
#define GATE_INFRA3(_id, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.parent = _parent, \
|
||||
.regs = &infra3_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate infra_clks[] = {
|
||||
/* INFRA0 */
|
||||
GATE_INFRA0(CLK_INFRA_PMIC_TMR, CLK_TOP_MUX_AXI, 0),
|
||||
GATE_INFRA0(CLK_INFRA_PMIC_AP, CLK_TOP_MUX_AXI, 1),
|
||||
GATE_INFRA0(CLK_INFRA_PMIC_MD, CLK_TOP_MUX_AXI, 2),
|
||||
GATE_INFRA0(CLK_INFRA_PMIC_CONN, CLK_TOP_MUX_AXI, 3),
|
||||
GATE_INFRA0(CLK_INFRA_SCPSYS, CLK_TOP_MUX_SCP, 4),
|
||||
GATE_INFRA0(CLK_INFRA_SEJ, CLK_TOP_CLK26M, 5),
|
||||
GATE_INFRA0(CLK_INFRA_APXGPT, CLK_TOP_MUX_AXI, 6),
|
||||
GATE_INFRA0(CLK_INFRA_ICUSB, CLK_TOP_MUX_AXI, 8),
|
||||
GATE_INFRA0(CLK_INFRA_GCE, CLK_TOP_MUX_AXI, 9),
|
||||
GATE_INFRA0(CLK_INFRA_THERM, CLK_TOP_MUX_AXI, 10),
|
||||
GATE_INFRA0(CLK_INFRA_I2C0, CLK_TOP_MUX_I2C, 11),
|
||||
GATE_INFRA0(CLK_INFRA_I2C1, CLK_TOP_MUX_I2C, 12),
|
||||
GATE_INFRA0(CLK_INFRA_I2C2, CLK_TOP_MUX_I2C, 13),
|
||||
GATE_INFRA0(CLK_INFRA_I2C3, CLK_TOP_MUX_I2C, 14),
|
||||
GATE_INFRA0(CLK_INFRA_PWM_HCLK, CLK_TOP_MUX_AXI, 15),
|
||||
GATE_INFRA0(CLK_INFRA_PWM1, CLK_TOP_MUX_I2C, 16),
|
||||
GATE_INFRA0(CLK_INFRA_PWM2, CLK_TOP_MUX_I2C, 17),
|
||||
GATE_INFRA0(CLK_INFRA_PWM3, CLK_TOP_MUX_I2C, 18),
|
||||
GATE_INFRA0(CLK_INFRA_PWM4, CLK_TOP_MUX_I2C, 19),
|
||||
GATE_INFRA0(CLK_INFRA_PWM, CLK_TOP_MUX_I2C, 21),
|
||||
GATE_INFRA0(CLK_INFRA_UART0, CLK_TOP_MUX_UART, 22),
|
||||
GATE_INFRA0(CLK_INFRA_UART1, CLK_TOP_MUX_UART, 23),
|
||||
GATE_INFRA0(CLK_INFRA_UART2, CLK_TOP_MUX_UART, 24),
|
||||
GATE_INFRA0(CLK_INFRA_UART3, CLK_TOP_MUX_UART, 25),
|
||||
GATE_INFRA0(CLK_INFRA_GCE_26M, CLK_TOP_MUX_AXI, 27),
|
||||
GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, CLK_TOP_MUX_AXI, 28),
|
||||
GATE_INFRA0(CLK_INFRA_BTIF, CLK_TOP_MUX_AXI, 31),
|
||||
/* INFRA1 */
|
||||
GATE_INFRA1(CLK_INFRA_SPI0, CLK_TOP_MUX_SPI, 1),
|
||||
GATE_INFRA1(CLK_INFRA_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 2),
|
||||
GATE_INFRA1(CLK_INFRA_MSDC1, CLK_TOP_MUX_AXI, 4),
|
||||
GATE_INFRA1(CLK_INFRA_MSDC2, CLK_TOP_MUX_AXI, 5),
|
||||
GATE_INFRA1(CLK_INFRA_MSDC0_SCK, CLK_TOP_MUX_MSDC50_0, 6),
|
||||
GATE_INFRA1(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7),
|
||||
GATE_INFRA1(CLK_INFRA_GCPU, CLK_TOP_MUX_AXI, 8),
|
||||
GATE_INFRA1(CLK_INFRA_TRNG, CLK_TOP_MUX_AXI, 9),
|
||||
GATE_INFRA1(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10),
|
||||
GATE_INFRA1(CLK_INFRA_CPUM, CLK_TOP_MUX_AXI, 11),
|
||||
GATE_INFRA1(CLK_INFRA_CCIF1_AP, CLK_TOP_MUX_AXI, 12),
|
||||
GATE_INFRA1(CLK_INFRA_CCIF1_MD, CLK_TOP_MUX_AXI, 13),
|
||||
GATE_INFRA1(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14),
|
||||
GATE_INFRA1(CLK_INFRA_MSDC1_SCK, CLK_TOP_MUX_MSDC30_1, 16),
|
||||
GATE_INFRA1(CLK_INFRA_MSDC2_SCK, CLK_TOP_MUX_MSDC30_2, 17),
|
||||
GATE_INFRA1(CLK_INFRA_AP_DMA, CLK_TOP_MUX_AXI, 18),
|
||||
GATE_INFRA1(CLK_INFRA_XIU, CLK_TOP_MUX_AXI, 19),
|
||||
GATE_INFRA1(CLK_INFRA_DEVICE_APC, CLK_TOP_MUX_AXI, 20),
|
||||
GATE_INFRA1(CLK_INFRA_CCIF_AP, CLK_TOP_MUX_AXI, 23),
|
||||
GATE_INFRA1(CLK_INFRA_DEBUGSYS, CLK_TOP_MUX_AXI, 24),
|
||||
GATE_INFRA1(CLK_INFRA_AUDIO, CLK_TOP_MUX_AXI, 25),
|
||||
GATE_INFRA1(CLK_INFRA_CCIF_MD, CLK_TOP_MUX_AXI, 26),
|
||||
GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, CLK_TOP_MUX_DXCC, 27),
|
||||
GATE_INFRA1(CLK_INFRA_DXCC_AO, CLK_TOP_MUX_DXCC, 28),
|
||||
GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, CLK_TOP_MUX_AXI, 30),
|
||||
GATE_INFRA1(CLK_INFRA_DRAMC_F26M, CLK_TOP_CLK26M, 31),
|
||||
/* INFRA2 */
|
||||
GATE_INFRA2(CLK_INFRA_IRTX, CLK_TOP_CLK26M, 0),
|
||||
GATE_INFRA2(CLK_INFRA_USB, CLK_TOP_MUX_USB_TOP, 1),
|
||||
GATE_INFRA2(CLK_INFRA_DISP_PWM, CLK_TOP_MUX_AXI, 2),
|
||||
GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, CLK_TOP_MUX_AXI, 3),
|
||||
GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, CLK_TOP_CLK26M, 4),
|
||||
GATE_INFRA2(CLK_INFRA_SPI1, CLK_TOP_MUX_SPI, 6),
|
||||
GATE_INFRA2(CLK_INFRA_I2C4, CLK_TOP_MUX_I2C, 7),
|
||||
GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, CLK_TOP_CLK26M, 8),
|
||||
GATE_INFRA2(CLK_INFRA_SPI2, CLK_TOP_MUX_SPI, 9),
|
||||
GATE_INFRA2(CLK_INFRA_SPI3, CLK_TOP_MUX_SPI, 10),
|
||||
GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, CLK_TOP_MUX_SSUSB_TOP_XHCI, 11),
|
||||
GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, CLK_TOP_MUX_FUFS, 12),
|
||||
GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, CLK_TOP_MUX_FUFS, 13),
|
||||
GATE_INFRA2(CLK_INFRA_MD32_BCLK, CLK_TOP_MUX_AXI, 14),
|
||||
GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, CLK_TOP_MUX_AXI, 16),
|
||||
GATE_INFRA2(CLK_INFRA_I2C5, CLK_TOP_MUX_I2C, 18),
|
||||
GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, CLK_TOP_MUX_I2C, 19),
|
||||
GATE_INFRA2(CLK_INFRA_I2C5_IMM, CLK_TOP_MUX_I2C, 20),
|
||||
GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, CLK_TOP_MUX_I2C, 21),
|
||||
GATE_INFRA2(CLK_INFRA_I2C1_IMM, CLK_TOP_MUX_I2C, 22),
|
||||
GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, CLK_TOP_MUX_I2C, 23),
|
||||
GATE_INFRA2(CLK_INFRA_I2C2_IMM, CLK_TOP_MUX_I2C, 24),
|
||||
GATE_INFRA2(CLK_INFRA_SPI4, CLK_TOP_MUX_SPI, 25),
|
||||
GATE_INFRA2(CLK_INFRA_SPI5, CLK_TOP_MUX_SPI, 26),
|
||||
GATE_INFRA2(CLK_INFRA_CQ_DMA, CLK_TOP_MUX_AXI, 27),
|
||||
GATE_INFRA2(CLK_INFRA_UFS, CLK_TOP_MUX_FUFS, 28),
|
||||
GATE_INFRA2(CLK_INFRA_AES_UFSFDE, CLK_TOP_MUX_FAES_UFSFDE, 29),
|
||||
GATE_INFRA2(CLK_INFRA_UFS_TICK, CLK_TOP_MUX_FUFS, 30),
|
||||
/* INFRA3 */
|
||||
GATE_INFRA3(CLK_INFRA_MSDC0_SELF, CLK_TOP_MUX_MSDC50_0, 0),
|
||||
GATE_INFRA3(CLK_INFRA_MSDC1_SELF, CLK_TOP_MUX_MSDC50_0, 1),
|
||||
GATE_INFRA3(CLK_INFRA_MSDC2_SELF, CLK_TOP_MUX_MSDC50_0, 2),
|
||||
GATE_INFRA3(CLK_INFRA_UFS_AXI, CLK_TOP_MUX_AXI, 5),
|
||||
GATE_INFRA3(CLK_INFRA_I2C6, CLK_TOP_MUX_I2C, 6),
|
||||
GATE_INFRA3(CLK_INFRA_AP_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 7),
|
||||
GATE_INFRA3(CLK_INFRA_MD_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 8),
|
||||
GATE_INFRA3(CLK_INFRA_CCIF2_AP, CLK_TOP_MUX_AXI, 16),
|
||||
GATE_INFRA3(CLK_INFRA_CCIF2_MD, CLK_TOP_MUX_AXI, 17),
|
||||
GATE_INFRA3(CLK_INFRA_CCIF3_AP, CLK_TOP_MUX_AXI, 18),
|
||||
GATE_INFRA3(CLK_INFRA_CCIF3_MD, CLK_TOP_MUX_AXI, 19),
|
||||
GATE_INFRA3(CLK_INFRA_SEJ_F13M, CLK_TOP_CLK26M, 20),
|
||||
GATE_INFRA3(CLK_INFRA_AES_BCLK, CLK_TOP_MUX_AXI, 21),
|
||||
GATE_INFRA3(CLK_INFRA_I2C7, CLK_TOP_MUX_I2C, 22),
|
||||
GATE_INFRA3(CLK_INFRA_I2C8, CLK_TOP_MUX_I2C, 23),
|
||||
GATE_INFRA3(CLK_INFRA_FBIST2FPC, CLK_TOP_MUX_MSDC50_0, 24),
|
||||
};
|
||||
|
||||
static int mt8183_apmixedsys_probe(struct udevice *dev)
|
||||
{
|
||||
return mtk_common_clk_init(dev, &mt8183_clk_tree);
|
||||
}
|
||||
|
||||
static int mt8183_topckgen_probe(struct udevice *dev)
|
||||
{
|
||||
return mtk_common_clk_init(dev, &mt8183_clk_tree);
|
||||
}
|
||||
|
||||
static int mt8183_infracfg_probe(struct udevice *dev)
|
||||
{
|
||||
return mtk_common_clk_gate_init(dev, &mt8183_clk_tree, infra_clks);
|
||||
}
|
||||
|
||||
static const struct udevice_id mt8183_apmixed_compat[] = {
|
||||
{ .compatible = "mediatek,mt8183-apmixedsys", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct udevice_id mt8183_topckgen_compat[] = {
|
||||
{ .compatible = "mediatek,mt8183-topckgen", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct udevice_id mt8183_infracfg_compat[] = {
|
||||
{ .compatible = "mediatek,mt8183-infracfg", },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
|
||||
.name = "mt8183-apmixedsys",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = mt8183_apmixed_compat,
|
||||
.probe = mt8183_apmixedsys_probe,
|
||||
.priv_auto = sizeof(struct mtk_clk_priv),
|
||||
.ops = &mtk_clk_apmixedsys_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mtk_clk_topckgen) = {
|
||||
.name = "mt8183-topckgen",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = mt8183_topckgen_compat,
|
||||
.probe = mt8183_topckgen_probe,
|
||||
.priv_auto = sizeof(struct mtk_clk_priv),
|
||||
.ops = &mtk_clk_topckgen_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mtk_clk_infracfg) = {
|
||||
.name = "mt8183-infracfg",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = mt8183_infracfg_compat,
|
||||
.probe = mt8183_infracfg_probe,
|
||||
.priv_auto = sizeof(struct mtk_clk_priv),
|
||||
.ops = &mtk_clk_gate_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
|
@ -313,10 +313,10 @@ static int bcm6348_iudma_request(struct dma *dma)
|
|||
ch_priv->desc_id = 0;
|
||||
if (bcm6348_iudma_chan_is_rx(dma->id)) {
|
||||
ch_priv->desc_cnt = 0;
|
||||
ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
|
||||
ch_priv->busy_desc = NULL;
|
||||
} else {
|
||||
ch_priv->desc_cnt = ch_priv->dma_ring_size;
|
||||
ch_priv->busy_desc = NULL;
|
||||
ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -91,20 +91,17 @@ void __noreturn mmc_boot(void)
|
|||
CONFIG_CFG_DATA_SECTOR, 1, tmp_buf);
|
||||
if (err != 1) {
|
||||
puts("spl: mmc read failed!!\n");
|
||||
free(tmp_buf);
|
||||
hang();
|
||||
}
|
||||
|
||||
val = *(tmp_buf + MBRDBR_BOOT_SIG_55);
|
||||
if (0x55 != val) {
|
||||
puts("spl: mmc signature is not valid!!\n");
|
||||
free(tmp_buf);
|
||||
hang();
|
||||
}
|
||||
val = *(tmp_buf + MBRDBR_BOOT_SIG_AA);
|
||||
if (0xAA != val) {
|
||||
puts("spl: mmc signature is not valid!!\n");
|
||||
free(tmp_buf);
|
||||
hang();
|
||||
}
|
||||
|
||||
|
|
|
@ -52,9 +52,11 @@ static int pci_mmc_probe(struct udevice *dev)
|
|||
|
||||
static int pci_mmc_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct pci_mmc_priv *priv = dev_get_priv(dev);
|
||||
if (CONFIG_IS_ENABLED(DM_GPIO)) {
|
||||
struct pci_mmc_priv *priv = dev_get_priv(dev);
|
||||
|
||||
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
|
||||
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -11,7 +11,6 @@ mtd-$(CONFIG_ALTERA_QSPI) += altera_qspi.o
|
|||
mtd-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
|
||||
mtd-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
|
||||
mtd-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
|
||||
mtd-$(CONFIG_MW_EEPROM) += mw_eeprom.o
|
||||
mtd-$(CONFIG_FLASH_PIC32) += pic32_flash.o
|
||||
mtd-$(CONFIG_ST_SMI) += st_smi.o
|
||||
mtd-$(CONFIG_STM32_FLASH) += stm32_flash.o
|
||||
|
|
|
@ -1,238 +0,0 @@
|
|||
/* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */
|
||||
|
||||
#include <common.h>
|
||||
#include <eeprom.h>
|
||||
#include <asm/ic/ssi.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/*
|
||||
* Serial EEPROM opcodes, including start bit
|
||||
*/
|
||||
#define EEP_OPC_ERASE 0x7 /* 3-bit opcode */
|
||||
#define EEP_OPC_WRITE 0x5 /* 3-bit opcode */
|
||||
#define EEP_OPC_READ 0x6 /* 3-bit opcode */
|
||||
|
||||
#define EEP_OPC_ERASE_ALL 0x12 /* 5-bit opcode */
|
||||
#define EEP_OPC_ERASE_EN 0x13 /* 5-bit opcode */
|
||||
#define EEP_OPC_WRITE_ALL 0x11 /* 5-bit opcode */
|
||||
#define EEP_OPC_ERASE_DIS 0x10 /* 5-bit opcode */
|
||||
|
||||
static int addrlen;
|
||||
|
||||
static void mw_eeprom_select(int dev)
|
||||
{
|
||||
ssi_set_interface(2048, 0, 0, 0);
|
||||
ssi_chip_select(0);
|
||||
udelay(1);
|
||||
ssi_chip_select(dev);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
static int mw_eeprom_size(int dev)
|
||||
{
|
||||
int x;
|
||||
u16 res;
|
||||
|
||||
mw_eeprom_select(dev);
|
||||
ssi_tx_byte(EEP_OPC_READ);
|
||||
|
||||
res = ssi_txrx_byte(0) << 8;
|
||||
res |= ssi_rx_byte();
|
||||
for (x = 0; x < 16; x++) {
|
||||
if (! (res & 0x8000)) {
|
||||
break;
|
||||
}
|
||||
res <<= 1;
|
||||
}
|
||||
ssi_chip_select(0);
|
||||
|
||||
return x;
|
||||
}
|
||||
|
||||
int mw_eeprom_erase_enable(int dev)
|
||||
{
|
||||
mw_eeprom_select(dev);
|
||||
ssi_tx_byte(EEP_OPC_ERASE_EN);
|
||||
ssi_tx_byte(0);
|
||||
udelay(1);
|
||||
ssi_chip_select(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mw_eeprom_erase_disable(int dev)
|
||||
{
|
||||
mw_eeprom_select(dev);
|
||||
ssi_tx_byte(EEP_OPC_ERASE_DIS);
|
||||
ssi_tx_byte(0);
|
||||
udelay(1);
|
||||
ssi_chip_select(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
u32 mw_eeprom_read_word(int dev, int addr)
|
||||
{
|
||||
u16 rcv;
|
||||
u16 res;
|
||||
int bits;
|
||||
|
||||
mw_eeprom_select(dev);
|
||||
ssi_tx_byte((EEP_OPC_READ << 5) | ((addr >> (addrlen - 5)) & 0x1f));
|
||||
rcv = ssi_txrx_byte(addr << (13 - addrlen));
|
||||
res = rcv << (16 - addrlen);
|
||||
bits = 4 + addrlen;
|
||||
|
||||
while (bits>0) {
|
||||
rcv = ssi_rx_byte();
|
||||
if (bits > 7) {
|
||||
res |= rcv << (bits - 8);
|
||||
} else {
|
||||
res |= rcv >> (8 - bits);
|
||||
}
|
||||
bits -= 8;
|
||||
}
|
||||
|
||||
ssi_chip_select(0);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
int mw_eeprom_write_word(int dev, int addr, u16 data)
|
||||
{
|
||||
u8 byte1=0;
|
||||
u8 byte2=0;
|
||||
|
||||
mw_eeprom_erase_enable(dev);
|
||||
mw_eeprom_select(dev);
|
||||
|
||||
switch (addrlen) {
|
||||
case 6:
|
||||
byte1 = EEP_OPC_WRITE >> 2;
|
||||
byte2 = (EEP_OPC_WRITE << 6)&0xc0;
|
||||
byte2 |= addr;
|
||||
break;
|
||||
case 7:
|
||||
byte1 = EEP_OPC_WRITE >> 1;
|
||||
byte2 = (EEP_OPC_WRITE << 7)&0x80;
|
||||
byte2 |= addr;
|
||||
break;
|
||||
case 8:
|
||||
byte1 = EEP_OPC_WRITE;
|
||||
byte2 = addr;
|
||||
break;
|
||||
case 9:
|
||||
byte1 = EEP_OPC_WRITE << 1;
|
||||
byte1 |= addr >> 8;
|
||||
byte2 = addr & 0xff;
|
||||
break;
|
||||
case 10:
|
||||
byte1 = EEP_OPC_WRITE << 2;
|
||||
byte1 |= addr >> 8;
|
||||
byte2 = addr & 0xff;
|
||||
break;
|
||||
default:
|
||||
printf("Unsupported number of address bits: %d\n", addrlen);
|
||||
return -1;
|
||||
|
||||
}
|
||||
|
||||
ssi_tx_byte(byte1);
|
||||
ssi_tx_byte(byte2);
|
||||
ssi_tx_byte(data >> 8);
|
||||
ssi_tx_byte(data & 0xff);
|
||||
ssi_chip_select(0);
|
||||
udelay(10000); /* Worst case */
|
||||
mw_eeprom_erase_disable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int mw_eeprom_write(int dev, int addr, u8 *buffer, int len)
|
||||
{
|
||||
int done;
|
||||
|
||||
done = 0;
|
||||
if (addr & 1) {
|
||||
u16 temp = mw_eeprom_read_word(dev, addr >> 1);
|
||||
temp &= 0xff00;
|
||||
temp |= buffer[0];
|
||||
|
||||
mw_eeprom_write_word(dev, addr >> 1, temp);
|
||||
len--;
|
||||
addr++;
|
||||
buffer++;
|
||||
done++;
|
||||
}
|
||||
|
||||
while (len <= 2) {
|
||||
mw_eeprom_write_word(dev, addr >> 1, *(u16*)buffer);
|
||||
len-=2;
|
||||
addr+=2;
|
||||
buffer+=2;
|
||||
done+=2;
|
||||
}
|
||||
|
||||
if (len) {
|
||||
u16 temp = mw_eeprom_read_word(dev, addr >> 1);
|
||||
temp &= 0x00ff;
|
||||
temp |= buffer[0] << 8;
|
||||
|
||||
mw_eeprom_write_word(dev, addr >> 1, temp);
|
||||
len--;
|
||||
addr++;
|
||||
buffer++;
|
||||
done++;
|
||||
}
|
||||
|
||||
return done;
|
||||
}
|
||||
|
||||
|
||||
int mw_eeprom_read(int dev, int addr, u8 *buffer, int len)
|
||||
{
|
||||
int done;
|
||||
|
||||
done = 0;
|
||||
if (addr & 1) {
|
||||
u16 temp = mw_eeprom_read_word(dev, addr >> 1);
|
||||
buffer[0]= temp & 0xff;
|
||||
|
||||
len--;
|
||||
addr++;
|
||||
buffer++;
|
||||
done++;
|
||||
}
|
||||
|
||||
while (len <= 2) {
|
||||
*(u16*)buffer = mw_eeprom_read_word(dev, addr >> 1);
|
||||
len-=2;
|
||||
addr+=2;
|
||||
buffer+=2;
|
||||
done+=2;
|
||||
}
|
||||
|
||||
if (len) {
|
||||
u16 temp = mw_eeprom_read_word(dev, addr >> 1);
|
||||
buffer[0] = temp >> 8;
|
||||
|
||||
len--;
|
||||
addr++;
|
||||
buffer++;
|
||||
done++;
|
||||
}
|
||||
|
||||
return done;
|
||||
}
|
||||
|
||||
int mw_eeprom_probe(int dev)
|
||||
{
|
||||
addrlen = mw_eeprom_size(dev);
|
||||
|
||||
if (addrlen < 6 || addrlen > 10) {
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
|
@ -321,6 +321,18 @@ config NAND_STM32_FMC2
|
|||
The controller supports a maximum 8k page size and supports
|
||||
a maximum 8-bit correction error per sector of 512 bytes.
|
||||
|
||||
config CORTINA_NAND
|
||||
bool "Support for NAND controller on Cortina-Access SoCs"
|
||||
depends on CORTINA_PLATFORM
|
||||
select SYS_NAND_SELF_INIT
|
||||
select DM_MTD
|
||||
imply CMD_NAND
|
||||
help
|
||||
Enables support for NAND Flash chips on Coartina-Access SoCs platform
|
||||
This controller is found on Presidio/Venus SoCs.
|
||||
The controller supports a maximum 8k page size and supports
|
||||
a maximum 40-bit error correction per sector of 1024 bytes.
|
||||
|
||||
comment "Generic NAND options"
|
||||
|
||||
config SYS_NAND_BLOCK_SIZE
|
||||
|
|
|
@ -69,6 +69,7 @@ obj-$(CONFIG_NAND_PLAT) += nand_plat.o
|
|||
obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
|
||||
obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
|
||||
obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
|
||||
obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
|
||||
|
||||
else # minimal SPL drivers
|
||||
|
||||
|
|
1390
drivers/mtd/nand/raw/cortina_nand.c
Normal file
1390
drivers/mtd/nand/raw/cortina_nand.c
Normal file
File diff suppressed because it is too large
Load diff
293
drivers/mtd/nand/raw/cortina_nand.h
Normal file
293
drivers/mtd/nand/raw/cortina_nand.h
Normal file
|
@ -0,0 +1,293 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2020 Cortina Access Inc..
|
||||
*/
|
||||
|
||||
/* Cortina NAND definition */
|
||||
#define NAND_BASE_ADDR 0xE0000000
|
||||
#define BCH_GF_PARAM_M 14
|
||||
#define BCH_DATA_UNIT 1024
|
||||
#define FLASH_SHORT_DELAY 100
|
||||
#define FLASH_LONG_DELAY 1000
|
||||
#define FLASH_WIDTH 16
|
||||
#define BBT_PAGE_MASK 0xffffff3f
|
||||
#define WRITE_SIZE_512 512
|
||||
#define WRITE_SIZE_2048 2048
|
||||
#define WRITE_SIZE_4096 4096
|
||||
#define WRITE_SIZE_8192 8192
|
||||
#define ECC_STRENGTH_8 8
|
||||
#define ECC_STRENGTH_16 16
|
||||
#define ECC_STRENGTH_24 24
|
||||
#define ECC_STRENGTH_40 40
|
||||
#define EMPTY_PAGE 0xff
|
||||
#define ADDR1_MASK0 0x00ffffff
|
||||
#define ADDR2_MASK0 0xff000000
|
||||
#define ADDR1_MASK1 0xffff
|
||||
#define ADDR1_MASK2 0xff
|
||||
#define OOB_MASK 0xff
|
||||
#define EXT_ADDR_MASK 0x8000000
|
||||
|
||||
/* Status bits */
|
||||
#define NAND_STATUS_FAIL 0x01
|
||||
#define NAND_STATUS_FAIL_N1 0x02
|
||||
#define NAND_STATUS_TRUE_READY 0x20
|
||||
#define NAND_STATUS_READY 0x40
|
||||
#define NAND_STATUS_WP 0x80
|
||||
|
||||
/* Bit field in FLAS_TYPE */
|
||||
#define FLASH_PIN BIT(15)
|
||||
#define FLASH_TYPE_512 0x4000
|
||||
#define FLASH_TYPE_2K 0x5000
|
||||
#define FLASH_TYPE_4K 0x6000
|
||||
#define FLASH_TYPE_8K 0x7000
|
||||
#define FLASH_SIZE_CONFIGURABLEOOB (0x0 << 9)
|
||||
#define FLASH_SIZE_400OOB (0x1 << 9)
|
||||
#define FLASH_SIZE_436OOB (0x2 << 9)
|
||||
#define FLASH_SIZE_640OOB (0x3 << 9)
|
||||
|
||||
/* Bit field in FLASH_STATUS */
|
||||
#define NFLASH_READY BIT(26)
|
||||
|
||||
/* Bit field in FLASH_NF_ACCESS */
|
||||
#define NFLASH_ENABLE_ALTERNATIVE (0x0 << 15)
|
||||
#define AUTO_RESET BIT(16)
|
||||
#define DISABLE_AUTO_RESET (0x0 << 16)
|
||||
#define NFLASH_REG_WIDTH_RESERVED (0x3 << 10)
|
||||
#define NFLASH_REG_WIDTH_32 (0x2 << 10)
|
||||
#define NFLASH_REG_WIDTH_16 (0x1 << 10)
|
||||
#define NFLASH_REG_WIDTH_8 (0x0 << 10)
|
||||
|
||||
/* Bit field in FLASH_NF_COUNT */
|
||||
#define REG_CMD_COUNT_EMPTY 0x3
|
||||
#define REG_CMD_COUNT_3TOGO 0x2
|
||||
#define REG_CMD_COUNT_2TOGO 0x1
|
||||
#define REG_CMD_COUNT_1TOGO 0x0
|
||||
#define REG_ADDR_COUNT_EMPTY (0x7 << 4)
|
||||
#define REG_ADDR_COUNT_5 (0x4 << 4)
|
||||
#define REG_ADDR_COUNT_4 (0x3 << 4)
|
||||
#define REG_ADDR_COUNT_3 (0x2 << 4)
|
||||
#define REG_ADDR_COUNT_2 (0x1 << 4)
|
||||
#define REG_ADDR_COUNT_1 (0x0 << 4)
|
||||
#define REG_DATA_COUNT_EMPTY (0x3fff << 8)
|
||||
#define REG_DATA_COUNT_512_DATA (0x1FF << 8)
|
||||
#define REG_DATA_COUNT_2k_DATA (0x7FF << 8)
|
||||
#define REG_DATA_COUNT_4k_DATA (0xFFF << 8)
|
||||
#define REG_DATA_COUNT_DATA_1 (0x0 << 8)
|
||||
#define REG_DATA_COUNT_DATA_2 (0x1 << 8)
|
||||
#define REG_DATA_COUNT_DATA_3 (0x2 << 8)
|
||||
#define REG_DATA_COUNT_DATA_4 (0x3 << 8)
|
||||
#define REG_DATA_COUNT_DATA_5 (0x4 << 8)
|
||||
#define REG_DATA_COUNT_DATA_6 (0x5 << 8)
|
||||
#define REG_DATA_COUNT_DATA_7 (0x6 << 8)
|
||||
#define REG_DATA_COUNT_DATA_8 (0x7 << 8)
|
||||
#define REG_OOB_COUNT_EMPTY (0x3ff << 22)
|
||||
|
||||
/* Bit field in FLASH_FLASH_ACCESS_START */
|
||||
#define NFLASH_GO BIT(0)
|
||||
#define NFLASH_FIFO_REQ BIT(2)
|
||||
#define NFLASH_RD BIT(13)
|
||||
#define NFLASH_WT (BIT(12) | BIT(13))
|
||||
|
||||
/* Bit field in FLASH_NF_ECC_RESET */
|
||||
#define RESET_NFLASH_RESET BIT(2)
|
||||
#define RESET_NFLASH_FIFO BIT(1)
|
||||
#define RESET_NFLASH_ECC BIT(0)
|
||||
#define ECC_RESET_ALL \
|
||||
RESET_NFLASH_RESET | RESET_NFLASH_FIFO | RESET_NFLASH_ECC
|
||||
|
||||
/* Bit field in FLASH_NF_ECC_CONTROL */
|
||||
#define ENABLE_ECC_GENERATION BIT(8)
|
||||
#define DISABLE_ECC_GENERATION (0 << 8)
|
||||
|
||||
/* Flash FIFO control */
|
||||
#define FIFO_READ 2
|
||||
#define FIFO_WRITE 3
|
||||
|
||||
/* NFLASH INTERRUPT */
|
||||
#define REGIRQ_CLEAR BIT(0)
|
||||
#define F_ADDR_ERR 2
|
||||
|
||||
/* BCH ECC field definition */
|
||||
#define BCH_COMPARE BIT(0)
|
||||
#define BCH_ENABLE BIT(8)
|
||||
#define BCH_DISABLE (0 << 8)
|
||||
#define BCH_DECODE BIT(1)
|
||||
#define BCH_ENCODE (0 << 1)
|
||||
#define BCH_DECO_DONE BIT(30)
|
||||
#define BCH_GEN_DONE BIT(31)
|
||||
#define BCH_UNCORRECTABLE 0x3
|
||||
#define BCH_CORRECTABLE_ERR 0x2
|
||||
#define BCH_NO_ERR 0x1
|
||||
#define BCH_BUSY 0x0
|
||||
#define BCH_ERR_MASK 0x3
|
||||
#define BCH_ERR_NUM_MASK 0x3F
|
||||
#define BCH_ERR_LOC_MASK 0x3FFF
|
||||
#define BCH_CORRECT_LOC_MASK 0x7
|
||||
#define BCH_ERR_CAP_8 (0x0 << 9)
|
||||
#define BCH_ERR_CAP_16 (0x1 << 9)
|
||||
#define BCH_ERR_CAP_24 (0x2 << 9)
|
||||
#define BCH_ERR_CAP_40 (0x3 << 9)
|
||||
|
||||
#define BCH_GF_PARAM_M 14
|
||||
|
||||
struct nand_ctlr {
|
||||
/* Cortina NAND controller register */
|
||||
u32 flash_id;
|
||||
u32 flash_timeout;
|
||||
u32 flash_status;
|
||||
u32 flash_type;
|
||||
u32 flash_flash_access_start;
|
||||
u32 flash_flash_interrupt;
|
||||
u32 flash_flash_mask;
|
||||
u32 flash_fifo_control;
|
||||
u32 flash_fifo_status;
|
||||
u32 flash_fifo_address;
|
||||
u32 flash_fifo_match_address;
|
||||
u32 flash_fifo_data;
|
||||
u32 flash_sf_access;
|
||||
u32 flash_sf_ext_access;
|
||||
u32 flash_sf_address;
|
||||
u32 flash_sf_data;
|
||||
u32 flash_sf_timing;
|
||||
u32 resv[3];
|
||||
u32 flash_pf_access; // offset 0x050
|
||||
u32 flash_pf_timing;
|
||||
u32 resv1[2];
|
||||
u32 flash_nf_access; // offset 0x060
|
||||
u32 flash_nf_count;
|
||||
u32 flash_nf_command;
|
||||
u32 flash_nf_address_1;
|
||||
u32 flash_nf_address_2;
|
||||
u32 flash_nf_data;
|
||||
u32 flash_nf_timing;
|
||||
u32 flash_nf_ecc_status;
|
||||
u32 flash_nf_ecc_control;
|
||||
u32 flash_nf_ecc_oob;
|
||||
u32 flash_nf_ecc_gen0;
|
||||
u32 resv3[15];
|
||||
u32 flash_nf_ecc_reset; // offset 0x0c8
|
||||
u32 flash_nf_bch_control;
|
||||
u32 flash_nf_bch_status;
|
||||
u32 flash_nf_bch_error_loc01;
|
||||
u32 resv4[19];
|
||||
u32 flash_nf_bch_oob0; // offset 0x124
|
||||
u32 resv5[17];
|
||||
u32 flash_nf_bch_gen0_0; // offset 0x16c
|
||||
};
|
||||
|
||||
/* Definition for DMA bitfield */
|
||||
#define TX_DMA_ENABLE BIT(0)
|
||||
#define RX_DMA_ENABLE BIT(0)
|
||||
#define DMA_CHECK_OWNER BIT(1)
|
||||
#define OWN_DMA 0
|
||||
#define OWN_CPU 1
|
||||
|
||||
#define CA_DMA_DEPTH 3
|
||||
#define CA_DMA_DESC_NUM (BIT(0) << CA_DMA_DEPTH)
|
||||
#define CA_DMA_Q_PTR_MASK 0x1fff
|
||||
|
||||
struct dma_q_base_depth_t {
|
||||
u32 depth : 4 ; /* bits 3:0 */
|
||||
u32 base : 28 ; /* bits 31:4 */
|
||||
};
|
||||
|
||||
struct tx_descriptor_t {
|
||||
unsigned int buf_adr; /* Buff addr */
|
||||
unsigned int buf_adr_hi : 8 ; /* bits 7:0 */
|
||||
unsigned int buf_len : 16 ; /* bits 23:8 */
|
||||
unsigned int sgm : 1 ; /* bits 24 */
|
||||
unsigned int rsrvd : 6 ; /* bits 30:25 */
|
||||
unsigned int own : 1 ; /* bits 31:31 */
|
||||
};
|
||||
|
||||
struct rx_descriptor_t {
|
||||
unsigned int buf_adr; /* Buff addr */
|
||||
unsigned int buf_adr_hi : 8 ; /* bits 7:0 */
|
||||
unsigned int buf_len : 16 ; /* bits 23:8 */
|
||||
unsigned int rsrvd : 7 ; /* bits 30:24 */
|
||||
unsigned int own : 1 ; /* bits 31:31 */
|
||||
};
|
||||
|
||||
struct dma_global {
|
||||
u32 dma_glb_dma_lso_ctrl;
|
||||
u32 dma_glb_lso_interrupt;
|
||||
u32 dma_glb_lso_intenable;
|
||||
u32 dma_glb_dma_lso_vlan_tag_type0;
|
||||
u32 dma_glb_dma_lso_vlan_tag_type1;
|
||||
u32 dma_glb_dma_lso_axi_user_sel0;
|
||||
u32 dma_glb_axi_user_pat0;
|
||||
u32 dma_glb_axi_user_pat1;
|
||||
u32 dma_glb_axi_user_pat2;
|
||||
u32 dma_glb_axi_user_pat3;
|
||||
u32 dma_glb_fast_reg_pe0;
|
||||
u32 dma_glb_fast_reg_pe1;
|
||||
u32 dma_glb_dma_lso_tx_fdes_addr0;
|
||||
u32 dma_glb_dma_lso_tx_fdes_addr1;
|
||||
u32 dma_glb_dma_lso_tx_cdes_addr0;
|
||||
u32 dma_glb_dma_lso_tx_cdes_addr1;
|
||||
u32 dma_glb_dma_lso_tx_des_word0;
|
||||
u32 dma_glb_dma_lso_tx_des_word1;
|
||||
u32 dma_glb_dma_lso_lso_para_word0;
|
||||
u32 dma_glb_dma_lso_lso_para_word1;
|
||||
u32 dma_glb_dma_lso_debug0;
|
||||
u32 dma_glb_dma_lso_debug1;
|
||||
u32 dma_glb_dma_lso_debug2;
|
||||
u32 dma_glb_dma_lso_spare0;
|
||||
u32 dma_glb_dma_lso_spare1;
|
||||
u32 dma_glb_dma_ssp_rx_ctrl;
|
||||
u32 dma_glb_dma_ssp_tx_ctrl;
|
||||
u32 dma_glb_dma_ssp_axi_user_sel0;
|
||||
u32 dma_glb_dma_ssp_axi_user_sel1;
|
||||
u32 dma_glb_dma_ssp_rx_fdes_addr0;
|
||||
u32 dma_glb_dma_ssp_rx_fdes_addr1;
|
||||
u32 dma_glb_dma_ssp_rx_cdes_addr0;
|
||||
u32 dma_glb_dma_ssp_rx_cdes_addr1;
|
||||
u32 dma_glb_dma_ssp_rx_des_word0;
|
||||
u32 dma_glb_dma_ssp_rx_des_word1;
|
||||
u32 dma_glb_dma_ssp_tx_fdes_addr0;
|
||||
u32 dma_glb_dma_ssp_tx_fdes_addr1;
|
||||
u32 dma_glb_dma_ssp_tx_cdes_addr0;
|
||||
u32 dma_glb_dma_ssp_tx_cdes_addr1;
|
||||
u32 dma_glb_dma_ssp_tx_des_word0;
|
||||
u32 dma_glb_dma_ssp_tx_des_word1;
|
||||
u32 dma_glb_dma_ssp_debug0;
|
||||
u32 dma_glb_dma_ssp_debug1;
|
||||
u32 dma_glb_dma_ssp_debug2;
|
||||
u32 dma_glb_dma_ssp_spare0;
|
||||
u32 dma_glb_dma_ssp_spare1;
|
||||
};
|
||||
|
||||
struct dma_ssp {
|
||||
u32 dma_q_rxq_control;
|
||||
u32 dma_q_rxq_base_depth;
|
||||
u32 dma_q_rxq_base;
|
||||
u32 dma_q_rxq_wptr;
|
||||
u32 dma_q_rxq_rptr;
|
||||
u32 dma_q_rxq_pktcnt;
|
||||
u32 dma_q_txq_control;
|
||||
u32 dma_q_txq_base_depth;
|
||||
u32 dma_q_txq_base;
|
||||
u32 dma_q_txq_wptr;
|
||||
u32 dma_q_txq_rptr;
|
||||
u32 dma_q_txq_pktcnt;
|
||||
u32 dma_q_rxq_interrupt;
|
||||
u32 dma_q_rxq_intenable;
|
||||
u32 dma_q_txq_interrupt;
|
||||
u32 dma_q_txq_intenable;
|
||||
u32 dma_q_rxq_misc_interrupt;
|
||||
u32 dma_q_rxq_misc_intenable;
|
||||
u32 dma_q_txq_misc_interrupt;
|
||||
u32 dma_q_txq_misc_intenable;
|
||||
u32 dma_q_rxq_coal_interrupt;
|
||||
u32 dma_q_rxq_coal_intenable;
|
||||
u32 dma_q_txq_coal_interrupt;
|
||||
u32 dma_q_txq_coal_intenable;
|
||||
u32 dma_q_rxq_frag_buff_addr0;
|
||||
u32 dma_q_rxq_frag_buff_addr1;
|
||||
u32 dma_q_rxq_frag_buff_size;
|
||||
u32 dma_q_txq_frag_buff_addr0;
|
||||
u32 dma_q_txq_frag_buff_addr1;
|
||||
u32 dma_q_txq_frag_buff_size;
|
||||
u32 dma_q_dma_spare_0;
|
||||
u32 dma_q_dma_spare_1;
|
||||
};
|
|
@ -615,6 +615,7 @@ static int mtk_gpiochip_register(struct udevice *parent)
|
|||
if (!drv)
|
||||
return -ENOENT;
|
||||
|
||||
ret = -ENOENT;
|
||||
dev_for_each_subnode(node, parent)
|
||||
if (ofnode_read_bool(node, "gpio-controller")) {
|
||||
ret = 0;
|
||||
|
|
|
@ -91,6 +91,21 @@ config DM_PMIC_FAN53555
|
|||
The driver implements read/write operations for use with the FAN53555
|
||||
regulator driver and binds the regulator driver to its node.
|
||||
|
||||
config DM_PMIC_MP5416
|
||||
bool "Enable Driver Model for PMIC MP5416"
|
||||
depends on DM_PMIC
|
||||
help
|
||||
This config enables implementation of driver-model pmic uclass features
|
||||
for PMIC MP5416. The driver implements read/write operations.
|
||||
|
||||
config SPL_DM_PMIC_MP5416
|
||||
bool "Enable Driver Model for PMIC MP5416 in SPL stage"
|
||||
depends on DM_PMIC
|
||||
help
|
||||
This config enables implementation of driver-model pmic uclass
|
||||
features for PMIC MP5416. The driver implements read/write
|
||||
operations.
|
||||
|
||||
config DM_PMIC_PCA9450
|
||||
bool "Enable Driver Model for PMIC PCA9450"
|
||||
depends on DM_PMIC
|
||||
|
|
|
@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
|
|||
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
|
||||
obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
|
||||
obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o
|
||||
obj-$(CONFIG_$(SPL_)DM_PMIC_MP5416) += mp5416.o
|
||||
obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
|
||||
obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o
|
||||
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
|
||||
|
|
98
drivers/power/pmic/mp5416.c
Normal file
98
drivers/power/pmic/mp5416.c
Normal file
|
@ -0,0 +1,98 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2020 Gateworks Corporation
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <dm.h>
|
||||
#include <i2c.h>
|
||||
#include <log.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/regulator.h>
|
||||
#include <power/mp5416.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static const struct pmic_child_info pmic_children_info[] = {
|
||||
/* buck */
|
||||
{ .prefix = "b", .driver = MP6416_REGULATOR_DRIVER },
|
||||
/* ldo */
|
||||
{ .prefix = "l", .driver = MP6416_REGULATOR_DRIVER },
|
||||
{ },
|
||||
};
|
||||
|
||||
static int mp5416_reg_count(struct udevice *dev)
|
||||
{
|
||||
return MP5416_NUM_OF_REGS - 1;
|
||||
}
|
||||
|
||||
static int mp5416_write(struct udevice *dev, uint reg, const uint8_t *buff,
|
||||
int len)
|
||||
{
|
||||
if (dm_i2c_write(dev, reg, buff, len)) {
|
||||
pr_err("write error to device: %p register: %#x!", dev, reg);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mp5416_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
|
||||
{
|
||||
if (dm_i2c_read(dev, reg, buff, len)) {
|
||||
pr_err("read error from device: %p register: %#x!", dev, reg);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mp5416_bind(struct udevice *dev)
|
||||
{
|
||||
int children;
|
||||
ofnode regulators_node;
|
||||
|
||||
debug("%s %s\n", __func__, dev->name);
|
||||
regulators_node = dev_read_subnode(dev, "regulators");
|
||||
if (!ofnode_valid(regulators_node)) {
|
||||
debug("%s: %s regulators subnode not found!\n", __func__,
|
||||
dev->name);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
|
||||
|
||||
children = pmic_bind_children(dev, regulators_node, pmic_children_info);
|
||||
if (!children)
|
||||
debug("%s: %s - no child found\n", __func__, dev->name);
|
||||
|
||||
/* Always return success for this device */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mp5416_probe(struct udevice *dev)
|
||||
{
|
||||
debug("%s %s\n", __func__, dev->name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dm_pmic_ops mp5416_ops = {
|
||||
.reg_count = mp5416_reg_count,
|
||||
.read = mp5416_read,
|
||||
.write = mp5416_write,
|
||||
};
|
||||
|
||||
static const struct udevice_id mp5416_ids[] = {
|
||||
{ .compatible = "mps,mp5416", },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pmic_mp5416) = {
|
||||
.name = "mp5416 pmic",
|
||||
.id = UCLASS_PMIC,
|
||||
.of_match = mp5416_ids,
|
||||
.bind = mp5416_bind,
|
||||
.probe = mp5416_probe,
|
||||
.ops = &mp5416_ops,
|
||||
};
|
|
@ -288,7 +288,6 @@ void u_qe_init(void)
|
|||
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
|
||||
|
||||
if (!mmc) {
|
||||
free(addr);
|
||||
printf("\nMMC cannot find device for ucode\n");
|
||||
} else {
|
||||
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
|
||||
|
|
|
@ -1,4 +1,5 @@
|
|||
if RAM || SPL_RAM
|
||||
|
||||
config ASPEED_DDR4_DUALX8
|
||||
bool "Enable Dual X8 DDR4 die"
|
||||
depends on DM && OF_CONTROL && ARCH_ASPEED
|
||||
|
@ -7,4 +8,62 @@ config ASPEED_DDR4_DUALX8
|
|||
Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram
|
||||
controller needs to know if the memory chip mounted on the board is dual
|
||||
x8 die or not. Or it may get the wrong size of the memory space.
|
||||
endif
|
||||
|
||||
if ASPEED_AST2600
|
||||
|
||||
choice
|
||||
prompt "DDR4 target date rate"
|
||||
default ASPEED_DDR4_1600
|
||||
|
||||
config ASPEED_DDR4_400
|
||||
bool "DDR4 targets at 400Mbps"
|
||||
depends on DM && OF_CONTROL && ARCH_ASPEED
|
||||
help
|
||||
select DDR4 target data rate at 400M
|
||||
|
||||
config ASPEED_DDR4_800
|
||||
bool "DDR4 targets at 800Mbps"
|
||||
depends on DM && OF_CONTROL && ARCH_ASPEED
|
||||
help
|
||||
select DDR4 target data rate at 800M
|
||||
|
||||
config ASPEED_DDR4_1333
|
||||
bool "DDR4 targets at 1333Mbps"
|
||||
depends on DM && OF_CONTROL && ARCH_ASPEED
|
||||
help
|
||||
select DDR4 target data rate at 1333M
|
||||
|
||||
config ASPEED_DDR4_1600
|
||||
bool "DDR4 targets at 1600Mbps"
|
||||
depends on DM && OF_CONTROL && ARCH_ASPEED
|
||||
help
|
||||
select DDR4 target data rate at 1600M
|
||||
endchoice
|
||||
|
||||
config ASPEED_BYPASS_SELFTEST
|
||||
bool "bypass self test during DRAM initialization"
|
||||
default n
|
||||
help
|
||||
Say Y here to bypass DRAM self test to speed up the boot time
|
||||
|
||||
config ASPEED_ECC
|
||||
bool "aspeed SDRAM error correcting code"
|
||||
depends on DM && OF_CONTROL && ARCH_ASPEED
|
||||
default n
|
||||
help
|
||||
enable SDRAM ECC function
|
||||
|
||||
if ASPEED_ECC
|
||||
config ASPEED_ECC_SIZE
|
||||
int "ECC size: 0=driver auto-caluated"
|
||||
depends on ASPEED_ECC
|
||||
default 0
|
||||
help
|
||||
SDRAM size with the error correcting code enabled. The unit is
|
||||
in Megabytes. Noted that only the 8/9 of the configured size
|
||||
can be used by the system. The remaining 1/9 will be used by
|
||||
the ECC engine. If the size is set to 0, the sdram driver will
|
||||
calculate the SDRAM size and set the whole range be ECC enabled.
|
||||
endif # end of ASPEED_ECC
|
||||
endif # end of ASPEED_AST2600
|
||||
endif # end of RAM || SPL_RAM
|
||||
|
|
|
@ -1,3 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o
|
||||
obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o
|
||||
obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o
|
||||
|
|
1061
drivers/ram/aspeed/sdram_ast2600.c
Normal file
1061
drivers/ram/aspeed/sdram_ast2600.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -81,6 +81,15 @@ config RESET_AST2500
|
|||
Say Y if you want to control reset signals of different peripherals
|
||||
through System Control Unit (SCU).
|
||||
|
||||
config RESET_AST2600
|
||||
bool "Reset controller driver for AST2600 SoCs"
|
||||
depends on DM_RESET
|
||||
default y if ASPEED_AST2600
|
||||
help
|
||||
Support for reset controller on AST2600 SoC.
|
||||
Say Y if you want to control reset signals of different peripherals
|
||||
through System Control Unit (SCU).
|
||||
|
||||
config RESET_ROCKCHIP
|
||||
bool "Reset controller driver for Rockchip SoCs"
|
||||
depends on DM_RESET && ARCH_ROCKCHIP && CLK
|
||||
|
|
|
@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
|
|||
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
|
||||
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
|
||||
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
|
||||
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
|
||||
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
|
||||
obj-$(CONFIG_RESET_MESON) += reset-meson.o
|
||||
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
|
||||
|
|
108
drivers/reset/reset-ast2600.c
Normal file
108
drivers/reset/reset-ast2600.c
Normal file
|
@ -0,0 +1,108 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020 ASPEED Technology Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <log.h>
|
||||
#include <misc.h>
|
||||
#include <reset.h>
|
||||
#include <reset-uclass.h>
|
||||
#include <linux/err.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/scu_ast2600.h>
|
||||
|
||||
struct ast2600_reset_priv {
|
||||
struct ast2600_scu *scu;
|
||||
};
|
||||
|
||||
static int ast2600_reset_request(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
|
||||
reset_ctl->dev, reset_ctl->id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ast2600_reset_free(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
|
||||
reset_ctl->dev, reset_ctl->id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ast2600_reset_assert(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
|
||||
struct ast2600_scu *scu = priv->scu;
|
||||
|
||||
debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
|
||||
|
||||
if (reset_ctl->id < 32)
|
||||
writel(BIT(reset_ctl->id), scu->modrst_ctrl1);
|
||||
else
|
||||
writel(BIT(reset_ctl->id - 32), scu->modrst_ctrl2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ast2600_reset_deassert(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
|
||||
struct ast2600_scu *scu = priv->scu;
|
||||
|
||||
debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
|
||||
|
||||
if (reset_ctl->id < 32)
|
||||
writel(BIT(reset_ctl->id), scu->modrst_clr1);
|
||||
else
|
||||
writel(BIT(reset_ctl->id - 32), scu->modrst_clr2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ast2600_reset_probe(struct udevice *dev)
|
||||
{
|
||||
int rc;
|
||||
struct ast2600_reset_priv *priv = dev_get_priv(dev);
|
||||
struct udevice *scu_dev;
|
||||
|
||||
/* get SCU base from clock device */
|
||||
rc = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_DRIVER_GET(aspeed_ast2600_scu), &scu_dev);
|
||||
if (rc) {
|
||||
debug("%s: clock device not found, rc=%d\n", __func__, rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
priv->scu = devfdt_get_addr_ptr(scu_dev);
|
||||
if (IS_ERR_OR_NULL(priv->scu)) {
|
||||
debug("%s: invalid SCU base pointer\n", __func__);
|
||||
return PTR_ERR(priv->scu);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id ast2600_reset_ids[] = {
|
||||
{ .compatible = "aspeed,ast2600-reset" },
|
||||
{ }
|
||||
};
|
||||
|
||||
struct reset_ops ast2600_reset_ops = {
|
||||
.request = ast2600_reset_request,
|
||||
.rfree = ast2600_reset_free,
|
||||
.rst_assert = ast2600_reset_assert,
|
||||
.rst_deassert = ast2600_reset_deassert,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(ast2600_reset) = {
|
||||
.name = "ast2600_reset",
|
||||
.id = UCLASS_RESET,
|
||||
.of_match = ast2600_reset_ids,
|
||||
.probe = ast2600_reset_probe,
|
||||
.ops = &ast2600_reset_ops,
|
||||
.priv_auto = sizeof(struct ast2600_reset_priv),
|
||||
};
|
|
@ -12,6 +12,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/wdt.h>
|
||||
#include <linux/err.h>
|
||||
#include <hang.h>
|
||||
|
||||
static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
|
||||
{
|
||||
|
@ -33,11 +34,15 @@ static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
|
|||
return -EPROTONOSUPPORT;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
ret = wdt_expire_now(wdt, reset_mode);
|
||||
if (ret) {
|
||||
debug("Sysreset failed: %d", ret);
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
hang();
|
||||
#endif
|
||||
|
||||
return -EINPROGRESS;
|
||||
}
|
||||
|
|
|
@ -61,6 +61,16 @@ static int mtk_timer_probe(struct udevice *dev)
|
|||
if (!uc_priv->clock_rate)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Initialize the timer:
|
||||
* 1. set clock source to system clock with clock divider setting to 1
|
||||
* 2. set timer mode to free running
|
||||
* 3. reset timer counter to 0 then enable the timer
|
||||
*/
|
||||
writel(GPT4_CLK_SYS | GPT4_CLK_DIV1, priv->base + MTK_GPT4_CLK);
|
||||
writel(GPT4_FREERUN | GPT4_CLEAR | GPT4_ENABLE,
|
||||
priv->base + MTK_GPT4_CTRL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -86,6 +86,15 @@ config WDT_ASPEED
|
|||
It currently does not support Boot Flash Addressing Mode Detection or
|
||||
Second Boot.
|
||||
|
||||
config WDT_AST2600
|
||||
bool "Aspeed AST2600 watchdog timer support"
|
||||
depends on WDT
|
||||
default y if ASPEED_AST2600
|
||||
help
|
||||
Select this to enable watchdog timer for Aspeed ast2500/ast2400 devices.
|
||||
The watchdog timer is stopped when initialized. It performs reset, either
|
||||
full SoC reset or CPU or just some peripherals, based on the flags.
|
||||
|
||||
config WDT_AT91
|
||||
bool "AT91 watchdog timer support"
|
||||
depends on WDT
|
||||
|
|
|
@ -19,6 +19,7 @@ obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o
|
|||
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
|
||||
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
|
||||
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
|
||||
obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
|
||||
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
|
||||
obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
|
||||
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
|
||||
|
|
110
drivers/watchdog/ast2600_wdt.c
Normal file
110
drivers/watchdog/ast2600_wdt.c
Normal file
|
@ -0,0 +1,110 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2020 Aspeed Technology, Inc
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <log.h>
|
||||
#include <wdt.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/wdt_ast2600.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
struct ast2600_wdt_priv {
|
||||
struct ast2600_wdt *regs;
|
||||
};
|
||||
|
||||
static int ast2600_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
|
||||
{
|
||||
struct ast2600_wdt_priv *priv = dev_get_priv(dev);
|
||||
struct ast2600_wdt *wdt = priv->regs;
|
||||
|
||||
/* WDT counts in the 1MHz frequency, namely 1us */
|
||||
writel((u32)(timeout_ms * 1000), &wdt->counter_reload_val);
|
||||
writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart);
|
||||
writel(WDT_CTRL_EN | WDT_CTRL_RESET, &wdt->ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ast2600_wdt_stop(struct udevice *dev)
|
||||
{
|
||||
struct ast2600_wdt_priv *priv = dev_get_priv(dev);
|
||||
struct ast2600_wdt *wdt = priv->regs;
|
||||
|
||||
clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
|
||||
|
||||
writel(WDT_RESET_MASK1_DEFAULT, &wdt->reset_mask1);
|
||||
writel(WDT_RESET_MASK2_DEFAULT, &wdt->reset_mask2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ast2600_wdt_reset(struct udevice *dev)
|
||||
{
|
||||
struct ast2600_wdt_priv *priv = dev_get_priv(dev);
|
||||
struct ast2600_wdt *wdt = priv->regs;
|
||||
|
||||
writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ast2600_wdt_expire_now(struct udevice *dev, ulong flags)
|
||||
{
|
||||
int ret;
|
||||
struct ast2600_wdt_priv *priv = dev_get_priv(dev);
|
||||
struct ast2600_wdt *wdt = priv->regs;
|
||||
|
||||
ret = ast2600_wdt_start(dev, 1, flags);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
while (readl(&wdt->ctrl) & WDT_CTRL_EN)
|
||||
;
|
||||
|
||||
return ast2600_wdt_stop(dev);
|
||||
}
|
||||
|
||||
static int ast2600_wdt_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct ast2600_wdt_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->regs = dev_read_addr_ptr(dev);
|
||||
if (!priv->regs)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct wdt_ops ast2600_wdt_ops = {
|
||||
.start = ast2600_wdt_start,
|
||||
.reset = ast2600_wdt_reset,
|
||||
.stop = ast2600_wdt_stop,
|
||||
.expire_now = ast2600_wdt_expire_now,
|
||||
};
|
||||
|
||||
static const struct udevice_id ast2600_wdt_ids[] = {
|
||||
{ .compatible = "aspeed,ast2600-wdt" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int ast2600_wdt_probe(struct udevice *dev)
|
||||
{
|
||||
debug("%s() wdt%u\n", __func__, dev_seq(dev));
|
||||
ast2600_wdt_stop(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(ast2600_wdt) = {
|
||||
.name = "ast2600_wdt",
|
||||
.id = UCLASS_WDT,
|
||||
.of_match = ast2600_wdt_ids,
|
||||
.probe = ast2600_wdt_probe,
|
||||
.priv_auto = sizeof(struct ast2600_wdt_priv),
|
||||
.of_to_plat = ast2600_wdt_of_to_plat,
|
||||
.ops = &ast2600_wdt_ops,
|
||||
};
|
16
include/configs/evb_ast2600.h
Normal file
16
include/configs/evb_ast2600.h
Normal file
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) Aspeed Technology Inc.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <configs/aspeed-common.h>
|
||||
|
||||
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
/* Memory Info */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x83000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -67,4 +67,13 @@
|
|||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
|
||||
|
||||
/* nand driver parameters */
|
||||
#ifdef CONFIG_TARGET_PRESIDIO_ASIC
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_MAX_CHIPS 1
|
||||
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#endif
|
||||
|
||||
#endif /* __PRESIDIO_ASIC_H */
|
||||
|
|
62
include/dt-bindings/clock/ast2600-clock.h
Normal file
62
include/dt-bindings/clock/ast2600-clock.h
Normal file
|
@ -0,0 +1,62 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) ASPEED Technology Inc.
|
||||
*/
|
||||
|
||||
#define ASPEED_CLK_GATE_ECLK 0
|
||||
#define ASPEED_CLK_GATE_GCLK 1
|
||||
#define ASPEED_CLK_GATE_MCLK 2
|
||||
#define ASPEED_CLK_GATE_VCLK 3
|
||||
#define ASPEED_CLK_GATE_BCLK 4
|
||||
#define ASPEED_CLK_GATE_DCLK 5
|
||||
#define ASPEED_CLK_GATE_LCLK 6
|
||||
#define ASPEED_CLK_GATE_YCLK 7
|
||||
#define ASPEED_CLK_GATE_LHCCLK 8
|
||||
#define ASPEED_CLK_GATE_REFCLK 9
|
||||
#define ASPEED_CLK_GATE_ESPICLK 10
|
||||
#define ASPEED_CLK_GATE_UART1CLK 11
|
||||
#define ASPEED_CLK_GATE_UART2CLK 12
|
||||
#define ASPEED_CLK_GATE_UART3CLK 13
|
||||
#define ASPEED_CLK_GATE_UART4CLK 14
|
||||
#define ASPEED_CLK_GATE_UART5CLK 15
|
||||
#define ASPEED_CLK_GATE_UART6CLK 16
|
||||
#define ASPEED_CLK_GATE_UART7CLK 17
|
||||
#define ASPEED_CLK_GATE_UART8CLK 18
|
||||
#define ASPEED_CLK_GATE_UART9CLK 19
|
||||
#define ASPEED_CLK_GATE_UART10CLK 20
|
||||
#define ASPEED_CLK_GATE_UART11CLK 21
|
||||
#define ASPEED_CLK_GATE_UART12CLK 22
|
||||
#define ASPEED_CLK_GATE_UART13CLK 23
|
||||
#define ASPEED_CLK_GATE_MAC1CLK 24
|
||||
#define ASPEED_CLK_GATE_MAC2CLK 25
|
||||
#define ASPEED_CLK_GATE_MAC3CLK 26
|
||||
#define ASPEED_CLK_GATE_MAC4CLK 27
|
||||
#define ASPEED_CLK_GATE_RSACLK 28
|
||||
#define ASPEED_CLK_GATE_SDCLK 29
|
||||
#define ASPEED_CLK_GATE_SDEXTCLK 30
|
||||
#define ASPEED_CLK_GATE_EMMCCLK 31
|
||||
#define ASPEED_CLK_GATE_EMMCEXTCLK 32
|
||||
#define ASPEED_CLK_GATE_USBUHCICLK 33
|
||||
#define ASPEED_CLK_GATE_USBPORT1CLK 34
|
||||
#define ASPEED_CLK_GATE_USBPORT2CLK 35
|
||||
#define ASPEED_CLK_GATE_FSICLK 36
|
||||
|
||||
#define ASPEED_CLK_APLL 37
|
||||
#define ASPEED_CLK_EPLL 38
|
||||
#define ASPEED_CLK_DPLL 39
|
||||
#define ASPEED_CLK_HPLL 40
|
||||
#define ASPEED_CLK_AHB 41
|
||||
#define ASPEED_CLK_APB1 42
|
||||
#define ASPEED_CLK_APB2 43
|
||||
#define ASPEED_CLK_UART 44
|
||||
#define ASPEED_CLK_SDIO 45
|
||||
#define ASPEED_CLK_ECLK 46
|
||||
#define ASPEED_CLK_ECLK_MUX 47
|
||||
#define ASPEED_CLK_LHCLK 48
|
||||
#define ASPEED_CLK_MAC 49
|
||||
#define ASPEED_CLK_BCLK 50
|
||||
#define ASPEED_CLK_MPLL 51
|
||||
#define ASPEED_CLK_24M 52
|
||||
#define ASPEED_CLK_EMMC 53
|
||||
#define ASPEED_CLK_UARTX 54
|
||||
#define ASPEED_CLK_HUARTX 55
|
329
include/dt-bindings/clock/mt8183-clk.h
Normal file
329
include/dt-bindings/clock/mt8183-clk.h
Normal file
|
@ -0,0 +1,329 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT8183_H
|
||||
#define _DT_BINDINGS_CLK_MT8183_H
|
||||
|
||||
/* APMIXED */
|
||||
#define CLK_APMIXED_ARMPLL_LL 0
|
||||
#define CLK_APMIXED_ARMPLL_L 1
|
||||
#define CLK_APMIXED_CCIPLL 2
|
||||
#define CLK_APMIXED_MAINPLL 3
|
||||
#define CLK_APMIXED_UNIV2PLL 4
|
||||
#define CLK_APMIXED_MSDCPLL 5
|
||||
#define CLK_APMIXED_MMPLL 6
|
||||
#define CLK_APMIXED_MFGPLL 7
|
||||
#define CLK_APMIXED_TVDPLL 8
|
||||
#define CLK_APMIXED_APLL1 9
|
||||
#define CLK_APMIXED_APLL2 10
|
||||
#define CLK_APMIXED_SSUSB_26M 11
|
||||
#define CLK_APMIXED_APPLL_26M 12
|
||||
#define CLK_APMIXED_MIPIC0_26M 13
|
||||
#define CLK_APMIXED_MDPLLGP_26M 14
|
||||
#define CLK_APMIXED_MMSYS_26M 15
|
||||
#define CLK_APMIXED_UFS_26M 16
|
||||
#define CLK_APMIXED_MIPIC1_26M 17
|
||||
#define CLK_APMIXED_MEMPLL_26M 18
|
||||
#define CLK_APMIXED_CLKSQ_LVPLL_26M 19
|
||||
#define CLK_APMIXED_MIPID0_26M 20
|
||||
#define CLK_APMIXED_MIPID1_26M 21
|
||||
#define CLK_APMIXED_NR_CLK 22
|
||||
|
||||
/* TOPCKGEN */
|
||||
#define CLK_TOP_CLK26M 0
|
||||
#define CLK_TOP_ULPOSC 1
|
||||
#define CLK_TOP_UNIVP_192M 2
|
||||
#define CLK_TOP_CLK13M 3
|
||||
#define CLK_TOP_F26M_CK_D2 4
|
||||
#define CLK_TOP_SYSPLL_CK 5
|
||||
#define CLK_TOP_SYSPLL_D2 6
|
||||
#define CLK_TOP_SYSPLL_D3 7
|
||||
#define CLK_TOP_SYSPLL_D5 8
|
||||
#define CLK_TOP_SYSPLL_D7 9
|
||||
#define CLK_TOP_SYSPLL_D2_D2 10
|
||||
#define CLK_TOP_SYSPLL_D2_D4 11
|
||||
#define CLK_TOP_SYSPLL_D2_D8 12
|
||||
#define CLK_TOP_SYSPLL_D2_D16 13
|
||||
#define CLK_TOP_SYSPLL_D3_D2 14
|
||||
#define CLK_TOP_SYSPLL_D3_D4 15
|
||||
#define CLK_TOP_SYSPLL_D3_D8 16
|
||||
#define CLK_TOP_SYSPLL_D5_D2 17
|
||||
#define CLK_TOP_SYSPLL_D5_D4 18
|
||||
#define CLK_TOP_SYSPLL_D7_D2 19
|
||||
#define CLK_TOP_SYSPLL_D7_D4 20
|
||||
#define CLK_TOP_UNIVPLL_CK 21
|
||||
#define CLK_TOP_UNIVPLL_D2 22
|
||||
#define CLK_TOP_UNIVPLL_D3 23
|
||||
#define CLK_TOP_UNIVPLL_D5 24
|
||||
#define CLK_TOP_UNIVPLL_D7 25
|
||||
#define CLK_TOP_UNIVPLL_D2_D2 26
|
||||
#define CLK_TOP_UNIVPLL_D2_D4 27
|
||||
#define CLK_TOP_UNIVPLL_D2_D8 28
|
||||
#define CLK_TOP_UNIVPLL_D3_D2 29
|
||||
#define CLK_TOP_UNIVPLL_D3_D4 30
|
||||
#define CLK_TOP_UNIVPLL_D3_D8 31
|
||||
#define CLK_TOP_UNIVPLL_D5_D2 32
|
||||
#define CLK_TOP_UNIVPLL_D5_D4 33
|
||||
#define CLK_TOP_UNIVPLL_D5_D8 34
|
||||
#define CLK_TOP_UNIVP_192M_CK 35
|
||||
#define CLK_TOP_UNIVP_192M_D2 36
|
||||
#define CLK_TOP_UNIVP_192M_D4 37
|
||||
#define CLK_TOP_UNIVP_192M_D8 38
|
||||
#define CLK_TOP_UNIVP_192M_D16 39
|
||||
#define CLK_TOP_UNIVP_192M_D32 40
|
||||
#define CLK_TOP_APLL1_CK 41
|
||||
#define CLK_TOP_APLL1_D2 42
|
||||
#define CLK_TOP_APLL1_D4 43
|
||||
#define CLK_TOP_APLL1_D8 44
|
||||
#define CLK_TOP_APLL2_CK 45
|
||||
#define CLK_TOP_APLL2_D2 46
|
||||
#define CLK_TOP_APLL2_D4 47
|
||||
#define CLK_TOP_APLL2_D8 48
|
||||
#define CLK_TOP_TVDPLL_CK 49
|
||||
#define CLK_TOP_TVDPLL_D2 50
|
||||
#define CLK_TOP_TVDPLL_D4 51
|
||||
#define CLK_TOP_TVDPLL_D8 52
|
||||
#define CLK_TOP_TVDPLL_D16 53
|
||||
#define CLK_TOP_MMPLL_CK 54
|
||||
#define CLK_TOP_MMPLL_D4 55
|
||||
#define CLK_TOP_MMPLL_D4_D2 56
|
||||
#define CLK_TOP_MMPLL_D4_D4 57
|
||||
#define CLK_TOP_MMPLL_D5 58
|
||||
#define CLK_TOP_MMPLL_D5_D2 59
|
||||
#define CLK_TOP_MMPLL_D5_D4 60
|
||||
#define CLK_TOP_MMPLL_D6 61
|
||||
#define CLK_TOP_MMPLL_D7 62
|
||||
#define CLK_TOP_MFGPLL_CK 63
|
||||
#define CLK_TOP_MSDCPLL_CK 64
|
||||
#define CLK_TOP_MSDCPLL_D2 65
|
||||
#define CLK_TOP_MSDCPLL_D4 66
|
||||
#define CLK_TOP_MSDCPLL_D8 67
|
||||
#define CLK_TOP_MSDCPLL_D16 68
|
||||
#define CLK_TOP_AD_OSC_CK 69
|
||||
#define CLK_TOP_OSC_D2 70
|
||||
#define CLK_TOP_OSC_D4 71
|
||||
#define CLK_TOP_OSC_D8 72
|
||||
#define CLK_TOP_OSC_D16 73
|
||||
#define CLK_TOP_UNIVPLL 74
|
||||
#define CLK_TOP_UNIVPLL_D3_D16 75
|
||||
#define CLK_TOP_APLL12_DIV0 76
|
||||
#define CLK_TOP_APLL12_DIV1 77
|
||||
#define CLK_TOP_APLL12_DIV2 78
|
||||
#define CLK_TOP_APLL12_DIV3 79
|
||||
#define CLK_TOP_APLL12_DIV4 80
|
||||
#define CLK_TOP_APLL12_DIVB 81
|
||||
#define CLK_TOP_ARMPLL_DIV_PLL1 82
|
||||
#define CLK_TOP_ARMPLL_DIV_PLL2 83
|
||||
#define CLK_TOP_MUX_AXI 84
|
||||
#define CLK_TOP_MUX_MM 85
|
||||
#define CLK_TOP_MUX_IMG 86
|
||||
#define CLK_TOP_MUX_CAM 87
|
||||
#define CLK_TOP_MUX_DSP 88
|
||||
#define CLK_TOP_MUX_DSP1 89
|
||||
#define CLK_TOP_MUX_DSP2 90
|
||||
#define CLK_TOP_MUX_IPU_IF 91
|
||||
#define CLK_TOP_MUX_MFG 92
|
||||
#define CLK_TOP_MUX_F52M_MFG 93
|
||||
#define CLK_TOP_MUX_CAMTG 94
|
||||
#define CLK_TOP_MUX_CAMTG2 95
|
||||
#define CLK_TOP_MUX_CAMTG3 96
|
||||
#define CLK_TOP_MUX_CAMTG4 97
|
||||
#define CLK_TOP_MUX_UART 98
|
||||
#define CLK_TOP_MUX_SPI 99
|
||||
#define CLK_TOP_MUX_MSDC50_0_HCLK 100
|
||||
#define CLK_TOP_MUX_MSDC50_0 101
|
||||
#define CLK_TOP_MUX_MSDC30_1 102
|
||||
#define CLK_TOP_MUX_MSDC30_2 103
|
||||
#define CLK_TOP_MUX_AUDIO 104
|
||||
#define CLK_TOP_MUX_AUD_INTBUS 105
|
||||
#define CLK_TOP_MUX_PMICSPI 106
|
||||
#define CLK_TOP_MUX_FPWRAP_ULPOSC 107
|
||||
#define CLK_TOP_MUX_ATB 108
|
||||
#define CLK_TOP_MUX_SSPM 109
|
||||
#define CLK_TOP_MUX_DPI0 110
|
||||
#define CLK_TOP_MUX_SCAM 111
|
||||
#define CLK_TOP_MUX_DISP_PWM 112
|
||||
#define CLK_TOP_MUX_USB_TOP 113
|
||||
#define CLK_TOP_MUX_SSUSB_TOP_XHCI 114
|
||||
#define CLK_TOP_MUX_SPM 115
|
||||
#define CLK_TOP_MUX_I2C 116
|
||||
#define CLK_TOP_MUX_SCP 117
|
||||
#define CLK_TOP_MUX_SENINF 118
|
||||
#define CLK_TOP_MUX_DXCC 119
|
||||
#define CLK_TOP_MUX_AUD_ENG1 120
|
||||
#define CLK_TOP_MUX_AUD_ENG2 121
|
||||
#define CLK_TOP_MUX_FAES_UFSFDE 122
|
||||
#define CLK_TOP_MUX_FUFS 123
|
||||
#define CLK_TOP_MUX_AUD_1 124
|
||||
#define CLK_TOP_MUX_AUD_2 125
|
||||
#define CLK_TOP_MUX_APLL_I2S0 126
|
||||
#define CLK_TOP_MUX_APLL_I2S1 127
|
||||
#define CLK_TOP_MUX_APLL_I2S2 128
|
||||
#define CLK_TOP_MUX_APLL_I2S3 129
|
||||
#define CLK_TOP_MUX_APLL_I2S4 130
|
||||
#define CLK_TOP_MUX_APLL_I2S5 131
|
||||
#define CLK_TOP_NR_CLK 132
|
||||
|
||||
/* INFRACFG_AO */
|
||||
#define CLK_INFRA_PMIC_TMR 0
|
||||
#define CLK_INFRA_PMIC_AP 1
|
||||
#define CLK_INFRA_PMIC_MD 2
|
||||
#define CLK_INFRA_PMIC_CONN 3
|
||||
#define CLK_INFRA_SCPSYS 4
|
||||
#define CLK_INFRA_SEJ 5
|
||||
#define CLK_INFRA_APXGPT 6
|
||||
#define CLK_INFRA_ICUSB 7
|
||||
#define CLK_INFRA_GCE 8
|
||||
#define CLK_INFRA_THERM 9
|
||||
#define CLK_INFRA_I2C0 10
|
||||
#define CLK_INFRA_I2C1 11
|
||||
#define CLK_INFRA_I2C2 12
|
||||
#define CLK_INFRA_I2C3 13
|
||||
#define CLK_INFRA_PWM_HCLK 14
|
||||
#define CLK_INFRA_PWM1 15
|
||||
#define CLK_INFRA_PWM2 16
|
||||
#define CLK_INFRA_PWM3 17
|
||||
#define CLK_INFRA_PWM4 18
|
||||
#define CLK_INFRA_PWM 19
|
||||
#define CLK_INFRA_UART0 20
|
||||
#define CLK_INFRA_UART1 21
|
||||
#define CLK_INFRA_UART2 22
|
||||
#define CLK_INFRA_UART3 23
|
||||
#define CLK_INFRA_GCE_26M 24
|
||||
#define CLK_INFRA_CQ_DMA_FPC 25
|
||||
#define CLK_INFRA_BTIF 26
|
||||
#define CLK_INFRA_SPI0 27
|
||||
#define CLK_INFRA_MSDC0 28
|
||||
#define CLK_INFRA_MSDC1 29
|
||||
#define CLK_INFRA_MSDC2 30
|
||||
#define CLK_INFRA_MSDC0_SCK 31
|
||||
#define CLK_INFRA_DVFSRC 32
|
||||
#define CLK_INFRA_GCPU 33
|
||||
#define CLK_INFRA_TRNG 34
|
||||
#define CLK_INFRA_AUXADC 35
|
||||
#define CLK_INFRA_CPUM 36
|
||||
#define CLK_INFRA_CCIF1_AP 37
|
||||
#define CLK_INFRA_CCIF1_MD 38
|
||||
#define CLK_INFRA_AUXADC_MD 39
|
||||
#define CLK_INFRA_MSDC1_SCK 40
|
||||
#define CLK_INFRA_MSDC2_SCK 41
|
||||
#define CLK_INFRA_AP_DMA 42
|
||||
#define CLK_INFRA_XIU 43
|
||||
#define CLK_INFRA_DEVICE_APC 44
|
||||
#define CLK_INFRA_CCIF_AP 45
|
||||
#define CLK_INFRA_DEBUGSYS 46
|
||||
#define CLK_INFRA_AUDIO 47
|
||||
#define CLK_INFRA_CCIF_MD 48
|
||||
#define CLK_INFRA_DXCC_SEC_CORE 49
|
||||
#define CLK_INFRA_DXCC_AO 50
|
||||
#define CLK_INFRA_DRAMC_F26M 51
|
||||
#define CLK_INFRA_IRTX 52
|
||||
#define CLK_INFRA_DISP_PWM 53
|
||||
#define CLK_INFRA_CLDMA_BCLK 54
|
||||
#define CLK_INFRA_AUDIO_26M_BCLK 55
|
||||
#define CLK_INFRA_SPI1 56
|
||||
#define CLK_INFRA_I2C4 57
|
||||
#define CLK_INFRA_MODEM_TEMP_SHARE 58
|
||||
#define CLK_INFRA_SPI2 59
|
||||
#define CLK_INFRA_SPI3 60
|
||||
#define CLK_INFRA_UNIPRO_SCK 61
|
||||
#define CLK_INFRA_UNIPRO_TICK 62
|
||||
#define CLK_INFRA_UFS_MP_SAP_BCLK 63
|
||||
#define CLK_INFRA_MD32_BCLK 64
|
||||
#define CLK_INFRA_SSPM 65
|
||||
#define CLK_INFRA_UNIPRO_MBIST 66
|
||||
#define CLK_INFRA_SSPM_BUS_HCLK 67
|
||||
#define CLK_INFRA_I2C5 68
|
||||
#define CLK_INFRA_I2C5_ARBITER 69
|
||||
#define CLK_INFRA_I2C5_IMM 70
|
||||
#define CLK_INFRA_I2C1_ARBITER 71
|
||||
#define CLK_INFRA_I2C1_IMM 72
|
||||
#define CLK_INFRA_I2C2_ARBITER 73
|
||||
#define CLK_INFRA_I2C2_IMM 74
|
||||
#define CLK_INFRA_SPI4 75
|
||||
#define CLK_INFRA_SPI5 76
|
||||
#define CLK_INFRA_CQ_DMA 77
|
||||
#define CLK_INFRA_UFS 78
|
||||
#define CLK_INFRA_AES_UFSFDE 79
|
||||
#define CLK_INFRA_UFS_TICK 80
|
||||
#define CLK_INFRA_MSDC0_SELF 81
|
||||
#define CLK_INFRA_MSDC1_SELF 82
|
||||
#define CLK_INFRA_MSDC2_SELF 83
|
||||
#define CLK_INFRA_SSPM_26M_SELF 84
|
||||
#define CLK_INFRA_SSPM_32K_SELF 85
|
||||
#define CLK_INFRA_UFS_AXI 86
|
||||
#define CLK_INFRA_I2C6 87
|
||||
#define CLK_INFRA_AP_MSDC0 88
|
||||
#define CLK_INFRA_MD_MSDC0 89
|
||||
#define CLK_INFRA_USB 90
|
||||
#define CLK_INFRA_DEVMPU_BCLK 91
|
||||
#define CLK_INFRA_CCIF2_AP 92
|
||||
#define CLK_INFRA_CCIF2_MD 93
|
||||
#define CLK_INFRA_CCIF3_AP 94
|
||||
#define CLK_INFRA_CCIF3_MD 95
|
||||
#define CLK_INFRA_SEJ_F13M 96
|
||||
#define CLK_INFRA_AES_BCLK 97
|
||||
#define CLK_INFRA_I2C7 98
|
||||
#define CLK_INFRA_I2C8 99
|
||||
#define CLK_INFRA_FBIST2FPC 100
|
||||
#define CLK_INFRA_NR_CLK 101
|
||||
|
||||
/* MMSYS_CONFIG */
|
||||
#define CLK_MM_SMI_COMMON 0
|
||||
#define CLK_MM_SMI_LARB0 1
|
||||
#define CLK_MM_SMI_LARB1 2
|
||||
#define CLK_MM_GALS_COMM0 3
|
||||
#define CLK_MM_GALS_COMM1 4
|
||||
#define CLK_MM_GALS_CCU2MM 5
|
||||
#define CLK_MM_GALS_IPU12MM 6
|
||||
#define CLK_MM_GALS_IMG2MM 7
|
||||
#define CLK_MM_GALS_CAM2MM 8
|
||||
#define CLK_MM_GALS_IPU2MM 9
|
||||
#define CLK_MM_MDP_DL_TXCK 10
|
||||
#define CLK_MM_IPU_DL_TXCK 11
|
||||
#define CLK_MM_MDP_RDMA0 12
|
||||
#define CLK_MM_MDP_RDMA1 13
|
||||
#define CLK_MM_MDP_RSZ0 14
|
||||
#define CLK_MM_MDP_RSZ1 15
|
||||
#define CLK_MM_MDP_TDSHP 16
|
||||
#define CLK_MM_MDP_WROT0 17
|
||||
#define CLK_MM_FAKE_ENG 18
|
||||
#define CLK_MM_DISP_OVL0 19
|
||||
#define CLK_MM_DISP_OVL0_2L 20
|
||||
#define CLK_MM_DISP_OVL1_2L 21
|
||||
#define CLK_MM_DISP_RDMA0 22
|
||||
#define CLK_MM_DISP_RDMA1 23
|
||||
#define CLK_MM_DISP_WDMA0 24
|
||||
#define CLK_MM_DISP_COLOR0 25
|
||||
#define CLK_MM_DISP_CCORR0 26
|
||||
#define CLK_MM_DISP_AAL0 27
|
||||
#define CLK_MM_DISP_GAMMA0 28
|
||||
#define CLK_MM_DISP_DITHER0 29
|
||||
#define CLK_MM_DISP_SPLIT 30
|
||||
#define CLK_MM_DSI0_MM 31
|
||||
#define CLK_MM_DSI0_IF 32
|
||||
#define CLK_MM_DPI_MM 33
|
||||
#define CLK_MM_DPI_IF 34
|
||||
#define CLK_MM_FAKE_ENG2 35
|
||||
#define CLK_MM_MDP_DL_RX 36
|
||||
#define CLK_MM_IPU_DL_RX 37
|
||||
#define CLK_MM_26M 38
|
||||
#define CLK_MM_MMSYS_R2Y 39
|
||||
#define CLK_MM_DISP_RSZ 40
|
||||
#define CLK_MM_MDP_WDMA0 41
|
||||
#define CLK_MM_MDP_AAL 42
|
||||
#define CLK_MM_MDP_CCORR 43
|
||||
#define CLK_MM_DBI_MM 44
|
||||
#define CLK_MM_DBI_IF 45
|
||||
#define CLK_MM_NR_CLK 46
|
||||
|
||||
/* MCUCFG */
|
||||
#define CLK_MCU_MP0_SEL 0
|
||||
#define CLK_MCU_MP2_SEL 1
|
||||
#define CLK_MCU_BUS_SEL 2
|
||||
#define CLK_MCU_NR_CLK 3
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT8183_H */
|
70
include/dt-bindings/reset/ast2600-reset.h
Normal file
70
include/dt-bindings/reset/ast2600-reset.h
Normal file
|
@ -0,0 +1,70 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) ASPEED Technology Inc.
|
||||
*/
|
||||
|
||||
#ifndef _ABI_MACH_ASPEED_AST2600_RESET_H_
|
||||
#define _ABI_MACH_ASPEED_AST2600_RESET_H_
|
||||
|
||||
#define ASPEED_RESET_FSI (59)
|
||||
#define ASPEED_RESET_RESERVED58 (58)
|
||||
#define ASPEED_RESET_RESERVED57 (57)
|
||||
#define ASPEED_RESET_SD (56)
|
||||
#define ASPEED_RESET_ADC (55)
|
||||
#define ASPEED_RESET_JTAG_MASTER2 (54)
|
||||
#define ASPEED_RESET_MAC4 (53)
|
||||
#define ASPEED_RESET_MAC3 (52)
|
||||
#define ASPEED_RESET_RESERVE51 (51)
|
||||
#define ASPEED_RESET_RESERVE50 (50)
|
||||
#define ASPEED_RESET_RESERVE49 (49)
|
||||
#define ASPEED_RESET_RESERVE48 (48)
|
||||
#define ASPEED_RESET_RESERVE47 (47)
|
||||
#define ASPEED_RESET_RESERVE46 (46)
|
||||
#define ASPEED_RESET_I3C5 (45)
|
||||
#define ASPEED_RESET_I3C4 (44)
|
||||
#define ASPEED_RESET_I3C3 (43)
|
||||
#define ASPEED_RESET_I3C2 (42)
|
||||
#define ASPEED_RESET_I3C1 (41)
|
||||
#define ASPEED_RESET_I3C0 (40)
|
||||
#define ASPEED_RESET_I3C_DMA (39)
|
||||
#define ASPEED_RESET_RESERVED38 (38)
|
||||
#define ASPEED_RESET_PWM (37)
|
||||
#define ASPEED_RESET_PECI (36)
|
||||
#define ASPEED_RESET_MII (35)
|
||||
#define ASPEED_RESET_I2C (34)
|
||||
#define ASPEED_RESET_RESERVED33 (33)
|
||||
#define ASPEED_RESET_LPC_ESPI (32)
|
||||
#define ASPEED_RESET_H2X (31)
|
||||
#define ASPEED_RESET_GP_MCU (30)
|
||||
#define ASPEED_RESET_DP_MCU (29)
|
||||
#define ASPEED_RESET_DP (28)
|
||||
#define ASPEED_RESET_RC_XDMA (27)
|
||||
#define ASPEED_RESET_GRAPHICS (26)
|
||||
#define ASPEED_RESET_DEV_XDMA (25)
|
||||
#define ASPEED_RESET_DEV_MCTP (24)
|
||||
#define ASPEED_RESET_RC_MCTP (23)
|
||||
#define ASPEED_RESET_JTAG_MASTER (22)
|
||||
#define ASPEED_RESET_PCIE_DEV_OE (21)
|
||||
#define ASPEED_RESET_PCIE_DEV_O (20)
|
||||
#define ASPEED_RESET_PCIE_RC_OE (19)
|
||||
#define ASPEED_RESET_PCIE_RC_O (18)
|
||||
#define ASPEED_RESET_RESERVED17 (17)
|
||||
#define ASPEED_RESET_EMMC (16)
|
||||
#define ASPEED_RESET_UHCI (15)
|
||||
#define ASPEED_RESET_EHCI_P1 (14)
|
||||
#define ASPEED_RESET_CRT (13)
|
||||
#define ASPEED_RESET_MAC2 (12)
|
||||
#define ASPEED_RESET_MAC1 (11)
|
||||
#define ASPEED_RESET_RESERVED10 (10)
|
||||
#define ASPEED_RESET_RVAS (9)
|
||||
#define ASPEED_RESET_PCI_VGA (8)
|
||||
#define ASPEED_RESET_2D (7)
|
||||
#define ASPEED_RESET_VIDEO (6)
|
||||
#define ASPEED_RESET_PCI_DP (5)
|
||||
#define ASPEED_RESET_HACE (4)
|
||||
#define ASPEED_RESET_EHCI_P2 (3)
|
||||
#define ASPEED_RESET_RESERVED2 (2)
|
||||
#define ASPEED_RESET_AHB (1)
|
||||
#define ASPEED_RESET_SDRAM (0)
|
||||
|
||||
#endif /* _ABI_MACH_ASPEED_AST2600_RESET_H_ */
|
41
include/power/mp5416.h
Normal file
41
include/power/mp5416.h
Normal file
|
@ -0,0 +1,41 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* Copyright (C) 2020 Gateworks Corporation */
|
||||
|
||||
#ifndef MP5416_H_
|
||||
#define MP5416_H_
|
||||
|
||||
#define MP6416_REGULATOR_DRIVER "mp5416_regulator"
|
||||
|
||||
enum {
|
||||
MP5416_CTL0 = 0x00,
|
||||
MP5416_CTL1 = 0x01,
|
||||
MP5416_CTL2 = 0x02,
|
||||
MP5416_ILIMIT = 0x03,
|
||||
MP5416_VSET_SW1 = 0x04,
|
||||
MP5416_VSET_SW2 = 0x05,
|
||||
MP5416_VSET_SW3 = 0x06,
|
||||
MP5416_VSET_SW4 = 0x07,
|
||||
MP5416_VSET_LDO2 = 0x08,
|
||||
MP5416_VSET_LDO3 = 0x09,
|
||||
MP5416_VSET_LDO4 = 0x0a,
|
||||
MP5416_VSET_LDO5 = 0x0b,
|
||||
MP5416_STATUS1 = 0x0d,
|
||||
MP5416_STATUS2 = 0x0e,
|
||||
MP5416_STATUS3 = 0x0f,
|
||||
MP5416_ID2 = 0x11,
|
||||
MP5416_NUM_OF_REGS = 0x12,
|
||||
};
|
||||
|
||||
#define MP5416_VSET_EN BIT(7)
|
||||
#define MP5416_VSET_SW1_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
|
||||
#define MP5416_VSET_SW2_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
|
||||
#define MP5416_VSET_SW3_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
|
||||
#define MP5416_VSET_SW4_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
|
||||
#define MP5416_VSET_LDO_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
|
||||
#define MP5416_VSET_LDO_SVAL(x) ((((x) & 0x7f) * 25000) + 800000)
|
||||
#define MP5416_VSET_SW1_SVAL(x) (((x) - 600000) / 12500)
|
||||
#define MP5416_VSET_SW2_SVAL(x) (((x) - 800000) / 25000)
|
||||
#define MP5416_VSET_SW3_SVAL(x) (((x) - 600000) / 12500)
|
||||
#define MP5416_VSET_SW4_SVAL(x) (((x) - 800000) / 25000)
|
||||
|
||||
#endif
|
|
@ -4,4 +4,5 @@
|
|||
|
||||
obj-y += mem.o
|
||||
obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o
|
||||
obj-$(CONFIG_CMD_PWM) += pwm.o
|
||||
obj-y += setexpr.o
|
||||
|
|
47
test/cmd/pwm.c
Normal file
47
test/cmd/pwm.c
Normal file
|
@ -0,0 +1,47 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Test for pwm command
|
||||
*
|
||||
* Copyright 2020 SiFive, Inc
|
||||
*
|
||||
* Authors:
|
||||
* Pragnesh Patel <pragnesh.patel@sifive.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <dm/test.h>
|
||||
#include <test/test.h>
|
||||
#include <test/ut.h>
|
||||
|
||||
/* Basic test of 'pwm' command */
|
||||
static int dm_test_pwm_cmd(struct unit_test_state *uts)
|
||||
{
|
||||
struct udevice *dev;
|
||||
|
||||
ut_assertok(uclass_get_device(UCLASS_PWM, 0, &dev));
|
||||
ut_assertnonnull(dev);
|
||||
|
||||
ut_assertok(console_record_reset_enable());
|
||||
|
||||
/* pwm <invert> <pwm_dev_num> <channel> <polarity> */
|
||||
ut_assertok(run_command("pwm invert 0 0 1", 0));
|
||||
ut_assert_console_end();
|
||||
|
||||
ut_assertok(run_command("pwm invert 0 0 0", 0));
|
||||
ut_assert_console_end();
|
||||
|
||||
/* pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns> */
|
||||
ut_assertok(run_command("pwm config 0 0 10 50", 0));
|
||||
ut_assert_console_end();
|
||||
|
||||
/* pwm <enable/disable> <pwm_dev_num> <channel> */
|
||||
ut_assertok(run_command("pwm enable 0 0", 0));
|
||||
ut_assert_console_end();
|
||||
|
||||
ut_assertok(run_command("pwm disable 0 0", 0));
|
||||
ut_assert_console_end();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
DM_TEST(dm_test_pwm_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
|
|
@ -246,6 +246,7 @@ static const struct brom_img_type {
|
|||
/* Image type selected by user */
|
||||
static enum brlyt_img_type hdr_media;
|
||||
static int use_lk_hdr;
|
||||
static bool is_arm64_image;
|
||||
|
||||
/* LK image name */
|
||||
static char lk_name[32] = "U-Boot";
|
||||
|
@ -276,6 +277,7 @@ static int mtk_brom_parse_imagename(const char *imagename)
|
|||
static const char *media = "";
|
||||
static const char *nandinfo = "";
|
||||
static const char *lk = "";
|
||||
static const char *arm64_param = "";
|
||||
|
||||
key = buf;
|
||||
while (key) {
|
||||
|
@ -323,6 +325,9 @@ static int mtk_brom_parse_imagename(const char *imagename)
|
|||
|
||||
if (!strcmp(key, "lkname"))
|
||||
snprintf(lk_name, sizeof(lk_name), "%s", val);
|
||||
|
||||
if (!strcmp(key, "arm64"))
|
||||
arm64_param = val;
|
||||
}
|
||||
|
||||
if (next)
|
||||
|
@ -354,6 +359,9 @@ static int mtk_brom_parse_imagename(const char *imagename)
|
|||
}
|
||||
}
|
||||
|
||||
if (arm64_param && arm64_param[0] == '1')
|
||||
is_arm64_image = true;
|
||||
|
||||
free(buf);
|
||||
|
||||
if (hdr_media == BRLYT_TYPE_INVALID) {
|
||||
|
@ -458,6 +466,9 @@ static int mtk_image_verify_gen_header(const uint8_t *ptr, int print)
|
|||
le32_to_cpu(gfh->file_info.load_addr) +
|
||||
le32_to_cpu(gfh->file_info.jump_offset));
|
||||
|
||||
if (print)
|
||||
printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -523,6 +534,9 @@ static int mtk_image_verify_nand_header(const uint8_t *ptr, int print)
|
|||
le32_to_cpu(gfh->file_info.load_addr) +
|
||||
le32_to_cpu(gfh->file_info.jump_offset));
|
||||
|
||||
if (print)
|
||||
printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -581,6 +595,8 @@ static void put_ghf_common_header(struct gfh_common_header *gfh, int size,
|
|||
static void put_ghf_header(struct gfh_header *gfh, int file_size,
|
||||
int dev_hdr_size, int load_addr, int flash_type)
|
||||
{
|
||||
uint32_t cfg_bits;
|
||||
|
||||
memset(gfh, 0, sizeof(struct gfh_header));
|
||||
|
||||
/* GFH_FILE_INFO header */
|
||||
|
@ -608,11 +624,15 @@ static void put_ghf_header(struct gfh_header *gfh, int file_size,
|
|||
/* GFH_BROM_CFG header */
|
||||
put_ghf_common_header(&gfh->brom_cfg.gfh, sizeof(gfh->brom_cfg),
|
||||
GFH_TYPE_BROM_CFG, 3);
|
||||
gfh->brom_cfg.cfg_bits = cpu_to_le32(
|
||||
GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS |
|
||||
GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN |
|
||||
GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN);
|
||||
cfg_bits = GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS |
|
||||
GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN |
|
||||
GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN;
|
||||
gfh->brom_cfg.usbdl_by_kcol0_timeout_ms = cpu_to_le32(5000);
|
||||
if (is_arm64_image) {
|
||||
gfh->brom_cfg.jump_bl_arm64 = GFH_BROM_CFG_JUMP_BL_ARM64;
|
||||
cfg_bits |= GFH_BROM_CFG_JUMP_BL_ARM64_EN;
|
||||
}
|
||||
gfh->brom_cfg.cfg_bits = cpu_to_le32(cfg_bits);
|
||||
|
||||
/* GFH_BL_SEC_KEY header */
|
||||
put_ghf_common_header(&gfh->bl_sec_key.gfh, sizeof(gfh->bl_sec_key),
|
||||
|
|
|
@ -136,7 +136,9 @@ struct gfh_brom_cfg {
|
|||
struct gfh_common_header gfh;
|
||||
uint32_t cfg_bits;
|
||||
uint32_t usbdl_by_auto_detect_timeout_ms;
|
||||
uint8_t unused[0x48];
|
||||
uint8_t unused[0x45];
|
||||
uint8_t jump_bl_arm64;
|
||||
uint8_t unused2[2];
|
||||
uint32_t usbdl_by_kcol0_timeout_ms;
|
||||
uint32_t usbdl_by_flag_timeout_ms;
|
||||
uint32_t pad;
|
||||
|
@ -146,6 +148,8 @@ struct gfh_brom_cfg {
|
|||
#define GFH_BROM_CFG_USBDL_AUTO_DETECT_DIS 0x10
|
||||
#define GFH_BROM_CFG_USBDL_BY_KCOL0_TIMEOUT_EN 0x80
|
||||
#define GFH_BROM_CFG_USBDL_BY_FLAG_TIMEOUT_EN 0x100
|
||||
#define GFH_BROM_CFG_JUMP_BL_ARM64_EN 0x1000
|
||||
#define GFH_BROM_CFG_JUMP_BL_ARM64 0x64
|
||||
|
||||
struct gfh_bl_sec_key {
|
||||
struct gfh_common_header gfh;
|
||||
|
|
Loading…
Add table
Reference in a new issue