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armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.

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When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.

Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Zhichun Hua 2015-06-29 15:50:42 +08:00 • committed by York Sun
parent 21a257b9b3
commit db14f11dfe
1 changed files with 8 additions and 15 deletions
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23
arch/arm/cpu/armv8/fsl-lsch3/cpu.c
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@ -82,6 +82,12 @@ void cpu_name(char *name)
TCR_ORGN_NC | \
TCR_IRGN_NC | \
TCR_T0SZ(LSCH3_VA_BITS))
#define LSCH3_TCR_FINAL (TCR_TG0_4K | \
TCR_EL2_PS_40BIT | \
TCR_SHARED_OUTER | \
TCR_ORGN_WBWA | \
TCR_IRGN_WBWA | \
TCR_T0SZ(LSCH3_VA_BITS))
/*
* Final MMU
@ -266,21 +272,8 @@ static inline void final_mmu_setup(void)
/* point TTBR to the new table */
el = current_el();
asm volatile("dsb sy");
if (el == 1) {
asm volatile("msr ttbr0_el1, %0"
: : "r" ((u64)level0_table) : "memory");
} else if (el == 2) {
asm volatile("msr ttbr0_el2, %0"
: : "r" ((u64)level0_table) : "memory");
} else if (el == 3) {
asm volatile("msr ttbr0_el3, %0"
: : "r" ((u64)level0_table) : "memory");
} else {
hang();
}
asm volatile("isb");
set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL,
MEMORY_ATTRIBUTES);
/*
* MMU is already enabled, just need to invalidate TLB to load the
* new table. The new table is compatible with the current table, if