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armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.
When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
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1 changed files with 8 additions and 15 deletions
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@ -82,6 +82,12 @@ void cpu_name(char *name)
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TCR_ORGN_NC | \
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TCR_IRGN_NC | \
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TCR_T0SZ(LSCH3_VA_BITS))
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#define LSCH3_TCR_FINAL (TCR_TG0_4K | \
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TCR_EL2_PS_40BIT | \
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TCR_SHARED_OUTER | \
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TCR_ORGN_WBWA | \
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TCR_IRGN_WBWA | \
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TCR_T0SZ(LSCH3_VA_BITS))
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/*
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* Final MMU
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@ -266,21 +272,8 @@ static inline void final_mmu_setup(void)
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/* point TTBR to the new table */
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el = current_el();
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asm volatile("dsb sy");
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if (el == 1) {
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asm volatile("msr ttbr0_el1, %0"
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: : "r" ((u64)level0_table) : "memory");
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} else if (el == 2) {
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asm volatile("msr ttbr0_el2, %0"
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: : "r" ((u64)level0_table) : "memory");
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} else if (el == 3) {
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asm volatile("msr ttbr0_el3, %0"
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: : "r" ((u64)level0_table) : "memory");
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} else {
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hang();
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}
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asm volatile("isb");
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set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL,
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MEMORY_ATTRIBUTES);
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/*
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* MMU is already enabled, just need to invalidate TLB to load the
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* new table. The new table is compatible with the current table, if
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