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ppc4xx: respect 80-chars per line in ppc*.h files
After running checkstyle.pl on the three previous patches I noted that in the *.h files there were a lot of long lines. This patch solves this problem. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Niklaus Giger
Stefan Roese
parent
78d2a64137
commit
dbcc357166
4 changed files with 988 additions and 820 deletions
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@ -31,7 +31,7 @@
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#ifndef CONFIG_IOP480
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#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
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#else
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#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */
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#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/
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#endif
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/******************************************************************************
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@ -133,7 +133,7 @@
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#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
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#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
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#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
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#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
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#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
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#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
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#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
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#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
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@ -223,7 +223,7 @@
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/* Defines for CPC0_PCI Register */
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#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
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#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
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#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
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#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */
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/* Defines for CPC0_BOOR Register */
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#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
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@ -329,10 +329,10 @@
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#define PLL_PCIDIV_4 0x00000003
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/*
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*-------------------------------------------------------------------------------
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*------------------------------------------------------------------------------
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* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
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* assuming a 33.3MHz input clock to the 405EP.
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*-------------------------------------------------------------------------------
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*------------------------------------------------------------------------------
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*/
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#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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@ -521,7 +521,7 @@
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/*
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* PLL Voltage Controlled Oscillator (VCO) definitions
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* Maximum and minimum values (in MHz) for correct PLL operation.
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*/
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*/
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#define VCO_MIN 400
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#define VCO_MAX 800
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#endif /* #ifndef CONFIG_IOP480 */
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@ -536,15 +536,15 @@
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#define MAL_DCR_BASE 0x180
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#endif
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#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
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#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear)*/
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#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear) */
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#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
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#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set)*/
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#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset)*/
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#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/
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#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
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#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
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#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */
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#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */
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#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
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#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
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#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/
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#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */
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#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */
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#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */
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#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */
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@ -610,7 +610,7 @@
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#define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */
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#define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */
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#define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */
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#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk*/
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#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk */
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#else
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#define OCM_DCR_BASE 0x018
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#define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
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@ -780,8 +780,8 @@
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#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
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#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
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#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
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#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
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#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */
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#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */
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#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
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#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
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@ -803,13 +803,13 @@
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#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
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#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
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#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
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#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
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#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Sel Gating Mask */
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#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Sel Gating Disable */
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#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Sel Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Sel0 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Sel1 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Sel2 Gating Enable */
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#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Sel3 Gating Enable */
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#define SDR0_PFC0 0x4100
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#define SDR0_PFC1 0x4101
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566
include/ppc440.h
566
include/ppc440.h
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@ -145,10 +145,10 @@
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#define SDR0_XCR2 0x01c6
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#define SDR0_XPLLC0 0x01c1
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#define SDR0_XPLLD0 0x01c2
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#define SDR0_XPLLC1 0x01c4 /*notRCW - SG */
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#define SDR0_XPLLD1 0x01c5 /*notRCW - SG */
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#define SDR0_XPLLC2 0x01c7 /*notRCW - SG */
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#define SDR0_XPLLD2 0x01c8 /*notRCW - SG */
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#define SDR0_XPLLC1 0x01c4 /* notRCW - SG */
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#define SDR0_XPLLD1 0x01c5 /* notRCW - SG */
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#define SDR0_XPLLC2 0x01c7 /* notRCW - SG */
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#define SDR0_XPLLD2 0x01c8 /* dnotRCW - SG */
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#define SD0_AMP0 0x0240
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#define SD0_AMP1 0x0241
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#define SDR0_CUST2 0x4004
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@ -187,17 +187,17 @@
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* PLB3 Arbiter */
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/* PLB3 Arbiter */
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#define PLB3_DCR_BASE 0x070
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#define PLB3_ACR (PLB3_DCR_BASE + 0x7)
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/* PLB4 Arbiter - PowerPC440EP Pass1 */
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/* PLB4 Arbiter - PowerPC440EP Pass1 */
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#define PLB4_DCR_BASE 0x080
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#define PLB4_ACR (PLB4_DCR_BASE + 0x1)
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#define PLB4_ACR_WRP (0x80000000 >> 7)
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/* Pin Function Control Register 1 */
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/* Pin Function Control Register 1 */
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#define SDR0_PFC1 0x4101
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#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
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#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
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@ -211,25 +211,36 @@
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#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
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#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
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#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
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#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
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#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold
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Req Selection */
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#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
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#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
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#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
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#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
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Selection */
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#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
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#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
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#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
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#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
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#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
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Selection */
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#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En.
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Selected */
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#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
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#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
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#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
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#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
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#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
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Selection */
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#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
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Disable */
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#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
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Enable */
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#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
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#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
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#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
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#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
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#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable
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Selection */
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#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor
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Enable */
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#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor
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Enable */
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#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
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Gated In */
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/* USB Control Register */
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/* USB Control Register */
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#define SDR0_USB0 0x0320
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#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
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#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
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@ -238,7 +249,7 @@
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#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
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#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
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/* Miscealleneaous Function Reg. */
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/* Miscealleneaous Function Reg. */
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#define SDR0_MFR 0x4300
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#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
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#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
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@ -257,7 +268,7 @@
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#define SDR0_MFR_ERRATA3_EN0 0x00800000
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#define SDR0_MFR_ERRATA3_EN1 0x00400000
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#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
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#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
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#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
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#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
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#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
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#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
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@ -278,11 +289,13 @@
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define SDR0_USB2D0CR 0x0320
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#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
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#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
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#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC
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Master Selection */
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#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/
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#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
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#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
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#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface
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Selection */
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#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
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#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
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@ -290,27 +303,36 @@
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#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
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#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
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/* USB2 Host Control Register */
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/* USB2 Host Control Register */
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#define SDR0_USB2H0CR 0x0340
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#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
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#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/
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#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
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#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
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#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
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#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length
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Adjustment */
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/* Pin Function Control Register 1 */
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/* Pin Function Control Register 1 */
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#define SDR0_PFC1 0x4101
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#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
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#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
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#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
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#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
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#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
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#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
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#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
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#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
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#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
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#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
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#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
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#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select
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EMAC 0 */
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#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII
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bridge */
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#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII
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bridge */
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#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII
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bridge */
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#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII
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bridge */
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#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII
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bridge */
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#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII
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bridge */
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#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII
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bridge */
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#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
|
||||
#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
|
||||
|
|
@ -321,28 +343,39 @@
|
|||
#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
|
||||
#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
|
||||
#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
|
||||
#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
|
||||
#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req
|
||||
Selection */
|
||||
#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
|
||||
#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
|
||||
#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
|
||||
#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
|
||||
Selection */
|
||||
#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
|
||||
#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
|
||||
#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
|
||||
#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
|
||||
Selection */
|
||||
#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
|
||||
#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
|
||||
#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
|
||||
#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
|
||||
#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
|
||||
#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
|
||||
Selection */
|
||||
#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
|
||||
Disable */
|
||||
#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
|
||||
Enable */
|
||||
|
||||
#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
|
||||
#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
|
||||
#define SDR0_PFC1_PLB_PME_MASK 0x00001000
|
||||
/* PLB3/PLB4 Perf. Monitor En. Selection */
|
||||
#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000
|
||||
/* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000
|
||||
/* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
|
||||
Gated In */
|
||||
|
||||
/* Ethernet PLL Configuration Register */
|
||||
/* Ethernet PLL Configuration Register */
|
||||
#define SDR0_PFC2 0x4102
|
||||
#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
|
||||
#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
|
||||
#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication
|
||||
selector */
|
||||
#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
|
||||
#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
|
||||
|
||||
|
|
@ -357,9 +390,11 @@
|
|||
|
||||
#define SDR0_PFC4 0x4104
|
||||
|
||||
/* USB2PHY0 Control Register */
|
||||
/* USB2PHY0 Control Register */
|
||||
#define SDR0_USB2PHY0CR 0x4103
|
||||
#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
|
||||
#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000
|
||||
|
||||
/* PHY UTMI interface connection */
|
||||
#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
|
||||
#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
|
||||
|
||||
|
|
@ -367,40 +402,57 @@
|
|||
#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
|
||||
#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
|
||||
|
||||
#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
|
||||
#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
|
||||
#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
|
||||
#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000
|
||||
/* VBus detect (Device mode only) */
|
||||
#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000
|
||||
/* Pull-up resistance on D+ is disabled */
|
||||
#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000
|
||||
/* Pull-up resistance on D+ is enabled */
|
||||
|
||||
#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
|
||||
#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000
|
||||
/* PHY UTMI data width and clock select */
|
||||
#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
|
||||
#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
|
||||
|
||||
#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
|
||||
#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
|
||||
#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
|
||||
#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000
|
||||
/* Loop back enabled (only test purposes) */
|
||||
|
||||
#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
|
||||
#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000
|
||||
/* Force XO block on during a suspend */
|
||||
#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
|
||||
#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
|
||||
#define SDR0_USB2PHY0CR_XO_OFF 0x04000000
|
||||
/* PHY XO block is powered-off when all ports are suspended */
|
||||
|
||||
#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
|
||||
#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
|
||||
#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
|
||||
#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only
|
||||
for full-speed operation */
|
||||
|
||||
#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
|
||||
#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
|
||||
#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
|
||||
#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock
|
||||
source */
|
||||
#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal
|
||||
48M clock as a reference */
|
||||
#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO
|
||||
block output as a reference */
|
||||
|
||||
#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
|
||||
#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
|
||||
#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
|
||||
#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO
|
||||
block*/
|
||||
#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external
|
||||
clock */
|
||||
#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock
|
||||
from a crystal */
|
||||
|
||||
#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
|
||||
#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
|
||||
#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
|
||||
#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
|
||||
#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq
|
||||
= 12 MHz */
|
||||
#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq
|
||||
= 48 MHz */
|
||||
#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq
|
||||
= 24 MHz */
|
||||
|
||||
/* Miscealleneaous Function Reg. */
|
||||
/* Miscealleneaous Function Reg. */
|
||||
#define SDR0_MFR 0x4300
|
||||
#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
|
||||
#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
|
||||
|
|
@ -417,20 +469,20 @@
|
|||
#define SDR0_MFR_ERRATA3_EN0 0x00800000
|
||||
#define SDR0_MFR_ERRATA3_EN1 0x00400000
|
||||
#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
|
||||
#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
|
||||
#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */
|
||||
#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
|
||||
#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
|
||||
#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
|
||||
|
||||
#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
|
||||
|
||||
/* CUST1 Customer Configuration Register1 */
|
||||
/* CUST1 Customer Configuration Register1 */
|
||||
#define SDR0_CUST1 0x4002
|
||||
#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
|
||||
#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
|
||||
/* Pin Function Control Register 0 */
|
||||
/* Pin Function Control Register 0 */
|
||||
#define SDR0_PFC0 0x4100
|
||||
#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
|
||||
#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
|
||||
|
|
@ -438,7 +490,7 @@
|
|||
#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
|
||||
#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
|
||||
|
||||
/* Pin Function Control Register 1 */
|
||||
/* Pin Function Control Register 1 */
|
||||
#define SDR0_PFC1 0x4101
|
||||
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
|
||||
#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
|
||||
|
|
@ -452,30 +504,40 @@
|
|||
#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
|
||||
#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
|
||||
#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
|
||||
#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
|
||||
#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req
|
||||
Selection */
|
||||
#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
|
||||
#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
|
||||
#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
|
||||
#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5)
|
||||
Selection */
|
||||
#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
|
||||
#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
|
||||
#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
|
||||
#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27)
|
||||
Selection */
|
||||
#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
|
||||
#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
|
||||
#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
|
||||
#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
|
||||
#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
|
||||
#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject
|
||||
Selection */
|
||||
#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject
|
||||
Disable */
|
||||
#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject
|
||||
Enable */
|
||||
|
||||
#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
|
||||
#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
|
||||
#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En.
|
||||
Selection */
|
||||
#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor
|
||||
Enable */
|
||||
#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor
|
||||
Enable */
|
||||
#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation
|
||||
Gated In */
|
||||
|
||||
#endif /* 440EP || 440GR || 440EPX || 440GRX */
|
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
|
||||
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
|
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT)
|
||||
/* CUST0 Customer Configuration Register0 */
|
||||
/* CUST0 Customer Configuration Register0 */
|
||||
#define SDR0_CUST0 0x4000
|
||||
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
|
||||
#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
|
||||
|
|
@ -512,7 +574,7 @@
|
|||
|
||||
#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
|
||||
#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
|
||||
|
|
@ -572,12 +634,12 @@
|
|||
#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
|
||||
#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
|
||||
#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
|
||||
#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */
|
||||
#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/
|
||||
#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */
|
||||
#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/
|
||||
#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
|
||||
#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
|
||||
#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */
|
||||
#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/
|
||||
#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */
|
||||
#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */
|
||||
#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */
|
||||
|
|
@ -816,10 +878,14 @@
|
|||
|
||||
#define SDR0_PINSTP 0x0040
|
||||
#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
|
||||
#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
|
||||
#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
|
||||
#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
|
||||
#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
|
||||
#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0
|
||||
(EBC boot) */
|
||||
#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1
|
||||
(PCI boot) */
|
||||
#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled -
|
||||
Addr = 0x54 */
|
||||
#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled -
|
||||
Addr = 0x50 */
|
||||
#define SDR0_SDCS 0x0060
|
||||
#define SDR0_ECID0 0x0080
|
||||
#define SDR0_ECID1 0x0081
|
||||
|
|
@ -960,8 +1026,10 @@
|
|||
#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
|
||||
#define SDR0_PFC1_CPU_NO_TRACE 0x00000000
|
||||
#define SDR0_PFC1_CPU_TRACE 0x00080000
|
||||
#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
|
||||
#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
|
||||
#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19)
|
||||
/* $218C */
|
||||
#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03)
|
||||
/* $218C */
|
||||
|
||||
#define SDR0_MFR 0x4300
|
||||
#endif /* CONFIG_440SPE */
|
||||
|
|
@ -1023,34 +1091,43 @@
|
|||
|
||||
/* Ethernet Configuration Register (SDR0_ETH_CFG) */
|
||||
#define SDR0_ETH_CFG 0x4103
|
||||
#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */
|
||||
#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */
|
||||
#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */
|
||||
#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */
|
||||
#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */
|
||||
#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */
|
||||
#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */
|
||||
#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */
|
||||
#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */
|
||||
#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */
|
||||
#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */
|
||||
#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */
|
||||
#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */
|
||||
#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */
|
||||
#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */
|
||||
#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */
|
||||
#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */
|
||||
#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */
|
||||
#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */
|
||||
#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */
|
||||
#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */
|
||||
#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */
|
||||
#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */
|
||||
#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /*SGMII3 port loopback
|
||||
enable */
|
||||
#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /*SGMII2 port loopback
|
||||
enable */
|
||||
#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /*SGMII1 port loopback
|
||||
enable */
|
||||
#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /*SGMII0 port loopback
|
||||
enable */
|
||||
#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /*SGMII Mask */
|
||||
#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /*SGMII2 port enable */
|
||||
#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /*SGMII1 port enable */
|
||||
#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /*SGMII0 port enable */
|
||||
#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /*TAHOE1 Bypass selector */
|
||||
#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /*TAHOE0 Bypass selector */
|
||||
#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /*EMAC 3 PHY clock selector*/
|
||||
#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /*EMAC 2 PHY clock selector*/
|
||||
#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /*EMAC 1 PHY clock selector*/
|
||||
#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /*EMAC 0 PHY clock selector*/
|
||||
#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /*Swap EMAC2 with EMAC1 */
|
||||
#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /*Swap EMAC0 with EMAC3 */
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /*MDIO source selector mask*/
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /*MDIO source - EMAC0 */
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /*MDIO source - EMAC1 */
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /*MDIO source - EMAC2 */
|
||||
#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /*MDIO source - EMAC3 */
|
||||
#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /*ZMII bridge mode selector
|
||||
mask */
|
||||
#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /*ZMII bridge mode - MII */
|
||||
#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /*ZMII bridge mode - SMII */
|
||||
#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /*ZMII bridge mode - RMII
|
||||
(10 Mbps) */
|
||||
#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /*ZMII bridge mode - RMII
|
||||
(100 Mbps) */
|
||||
#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /*GMC Port 1 bridge
|
||||
selector */
|
||||
#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /*GMC Port 0 bridge
|
||||
selector */
|
||||
|
||||
#define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4
|
||||
#define SDR0_ETH_CFG_ZMII_MII_MODE 0x00
|
||||
|
|
@ -1063,26 +1140,46 @@
|
|||
|
||||
/* Miscealleneaous Function Reg. (SDR0_MFR) */
|
||||
#define SDR0_MFR 0x4300
|
||||
#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */
|
||||
#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx
|
||||
FIFO bits 64:127 */
|
||||
#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx
|
||||
FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx
|
||||
FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx
|
||||
FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx
|
||||
FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx
|
||||
FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx
|
||||
FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx
|
||||
FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx
|
||||
FIFO bits 64:127 */
|
||||
#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx
|
||||
FIFO bits 0:63 */
|
||||
#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx
|
||||
FIFO bits 64:127 */
|
||||
|
||||
/* EMACx TX Status Register (SDR0_EMACxTXST)*/
|
||||
#define SDR0_EMAC0TXST 0x4400
|
||||
|
|
@ -1090,30 +1187,30 @@
|
|||
#define SDR0_EMAC2TXST 0x4402
|
||||
#define SDR0_EMAC3TXST 0x4403
|
||||
|
||||
#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
|
||||
#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
|
||||
#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
|
||||
#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
|
||||
#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
|
||||
#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */
|
||||
#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
|
||||
#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
|
||||
#define SDR0_EMACxTXST_FUR 0x02000000 /*TX FIFO underrun */
|
||||
#define SDR0_EMACxTXST_BC 0x01000000 /*broadcase address */
|
||||
#define SDR0_EMACxTXST_MC 0x00800000 /*multicast address */
|
||||
#define SDR0_EMACxTXST_UC 0x00400000 /*unicast address */
|
||||
#define SDR0_EMACxTXST_FP 0x00200000 /*frame paused by control packet */
|
||||
#define SDR0_EMACxTXST_BFCS 0x00100000 /*bad FCS in the transmitted frame */
|
||||
#define SDR0_EMACxTXST_CPF 0x00080000 /*TX control pause frame */
|
||||
#define SDR0_EMACxTXST_CF 0x00040000 /*TX control frame */
|
||||
#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
|
||||
#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
|
||||
#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
|
||||
#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
|
||||
#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
|
||||
#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
|
||||
#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
|
||||
#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
|
||||
#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
|
||||
#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
|
||||
#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
|
||||
#define SDR0_EMACxTXST_1023 0x00010000 /*512-1023 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_511 0x00008000 /*256-511 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_255 0x00004000 /*128-255 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_127 0x00002000 /*65-127 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_64 0x00001000 /*64 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_SQE 0x00000800 /*SQE indication */
|
||||
#define SDR0_EMACxTXST_LOC 0x00000400 /*loss of carrier sense */
|
||||
#define SDR0_EMACxTXST_IERR 0x00000080 /*EMAC internal error */
|
||||
#define SDR0_EMACxTXST_EDF 0x00000040 /*excessive deferral */
|
||||
#define SDR0_EMACxTXST_ECOL 0x00000020 /*excessive collisions */
|
||||
#define SDR0_EMACxTXST_LCOL 0x00000010 /*late collision */
|
||||
#define SDR0_EMACxTXST_DFFR 0x00000008 /*deferred frame */
|
||||
#define SDR0_EMACxTXST_MCOL 0x00000004 /*multiple collision frame */
|
||||
#define SDR0_EMACxTXST_SCOL 0x00000002 /*single collision frame */
|
||||
#define SDR0_EMACxTXST_TXOK 0x00000001 /*transmit OK */
|
||||
|
||||
/* EMACx RX Status Register (SDR0_EMACxRXST)*/
|
||||
#define SDR0_EMAC0RXST 0x4404
|
||||
|
|
@ -1146,7 +1243,8 @@
|
|||
#define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */
|
||||
#define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */
|
||||
#define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */
|
||||
#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */
|
||||
#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal
|
||||
EMAC receive error */
|
||||
#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */
|
||||
#define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */
|
||||
|
||||
|
|
@ -1306,14 +1404,15 @@
|
|||
#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
|
||||
#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
|
||||
#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
|
||||
#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
|
||||
#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs*/
|
||||
#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
|
||||
#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
|
||||
#define SDR0_MFR_ERRATA3_EN0 0x00800000
|
||||
#define SDR0_MFR_ERRATA3_EN1 0x00400000
|
||||
#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
|
||||
#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
|
||||
#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
|
||||
#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3
|
||||
0-1 */
|
||||
#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
|
||||
#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
|
||||
#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
|
||||
|
|
@ -1348,8 +1447,10 @@
|
|||
#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
|
||||
#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
|
||||
#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
|
||||
#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
|
||||
#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
|
||||
#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/
|
||||
transmitter 0 */
|
||||
#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/
|
||||
transmitter 1 */
|
||||
#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
|
||||
#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
|
||||
#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
|
||||
|
|
@ -1373,8 +1474,10 @@
|
|||
#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
|
||||
#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
|
||||
#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
|
||||
#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
|
||||
#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
|
||||
#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/
|
||||
transmitter 2 */
|
||||
#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/
|
||||
transmitter 3 */
|
||||
|
||||
#define SDR0_SRST1 0x201
|
||||
#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
|
||||
|
|
@ -1383,11 +1486,14 @@
|
|||
#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
|
||||
#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
|
||||
#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
|
||||
#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
|
||||
#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
|
||||
#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
|
||||
#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4
|
||||
USB 2.0 Host */
|
||||
#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to
|
||||
USB 2.0 Host */
|
||||
#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to
|
||||
USB 2.0 Host */
|
||||
#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
|
||||
#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
|
||||
#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/
|
||||
#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
|
||||
#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
|
||||
#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
|
||||
|
|
@ -1411,8 +1517,10 @@
|
|||
#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
|
||||
#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
|
||||
#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
|
||||
#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
|
||||
#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
|
||||
#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/
|
||||
transmitter 0 */
|
||||
#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/
|
||||
transmitter 1 */
|
||||
#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
|
||||
#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */
|
||||
#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */
|
||||
|
|
@ -1427,11 +1535,13 @@
|
|||
#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/
|
||||
#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/
|
||||
#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/
|
||||
#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */
|
||||
#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/
|
||||
transmitter 2 */
|
||||
#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
|
||||
#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
|
||||
#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */
|
||||
#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */
|
||||
#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/
|
||||
transmitter 3 */
|
||||
#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */
|
||||
|
||||
#define SDR0_SRST1 0x201
|
||||
|
|
@ -1440,17 +1550,22 @@
|
|||
#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */
|
||||
#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */
|
||||
#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */
|
||||
#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */
|
||||
#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */
|
||||
#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */
|
||||
#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */
|
||||
#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access
|
||||
controller 0 */
|
||||
#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access
|
||||
controller 1 */
|
||||
#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access
|
||||
controller 2 */
|
||||
#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access
|
||||
controller 3 */
|
||||
#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */
|
||||
#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */
|
||||
#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */
|
||||
#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */
|
||||
#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */
|
||||
#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */
|
||||
#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */
|
||||
#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and
|
||||
serdes */
|
||||
#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */
|
||||
#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */
|
||||
#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */
|
||||
|
|
@ -1624,7 +1739,8 @@
|
|||
|
||||
/* PCI Local Configuration Registers
|
||||
--------------------------------- */
|
||||
#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
|
||||
#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real =>
|
||||
0x0EF400000 */
|
||||
|
||||
/* PCI Master Local Configuration Registers */
|
||||
#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
|
||||
|
|
@ -1641,9 +1757,11 @@
|
|||
#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
|
||||
|
||||
/* PCI Target Local Configuration Registers */
|
||||
#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
|
||||
#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/
|
||||
Attribute */
|
||||
#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
|
||||
#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
|
||||
#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/
|
||||
Attribute */
|
||||
#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
|
||||
|
||||
#else
|
||||
|
|
@ -1674,6 +1792,31 @@
|
|||
#define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
|
||||
#define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
|
||||
#define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
|
||||
#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
|
||||
#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
|
||||
#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
|
||||
#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
|
||||
#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
|
||||
#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame*/
|
||||
#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
|
||||
#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
|
||||
#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
|
||||
#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
|
||||
#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
|
||||
#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
|
||||
#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
|
||||
#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
|
||||
#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
|
||||
#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
|
||||
#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
|
||||
#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
|
||||
#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
|
||||
#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
|
||||
|
||||
#define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT )
|
||||
#define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT )
|
||||
|
||||
|
|
@ -1713,24 +1856,41 @@
|
|||
|
||||
#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
|
||||
|
||||
#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
|
||||
#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
|
||||
#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
|
||||
#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
|
||||
#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
|
||||
#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
|
||||
#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
|
||||
#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
|
||||
#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
|
||||
#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
|
||||
#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for
|
||||
Endpoint 0 plus IN Endpoints 1 to 3 */
|
||||
#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management
|
||||
register */
|
||||
#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address
|
||||
register */
|
||||
#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable
|
||||
register for USB2D0_INTRIN */
|
||||
#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for
|
||||
OUT Endpoints 1 to 3 */
|
||||
#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable
|
||||
register for USB2D0_INTRUSB */
|
||||
#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for
|
||||
common USB interrupts */
|
||||
#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable
|
||||
register for IntrOut */
|
||||
#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0
|
||||
test modes */
|
||||
#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for
|
||||
selecting the Endpoint status/control registers */
|
||||
#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
|
||||
#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
|
||||
#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
|
||||
#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
|
||||
#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
|
||||
#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
|
||||
#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
|
||||
#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
|
||||
#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status
|
||||
register for Endpoint 0. (Index register set to select Endpoint 0) */
|
||||
#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status
|
||||
register for IN Endpoint. (Index register set to select Endpoints 13) */
|
||||
#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet
|
||||
size for IN Endpoint. (Index register set to select Endpoints 13) */
|
||||
#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status
|
||||
register for OUT Endpoint. (Index register set to select Endpoints 13) */
|
||||
#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet
|
||||
size for OUT Endpoint. (Index register set to select Endpoints 13) */
|
||||
#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received
|
||||
bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
|
||||
#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in
|
||||
OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
|
|
|
|||
|
|
@ -140,8 +140,8 @@
|
|||
#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
|
||||
|
||||
#define RESET_VECTOR 0xfffffffc
|
||||
#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
|
||||
line aligned data. */
|
||||
#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
|
||||
cache line aligned data. */
|
||||
|
||||
#define CPR0_DCR_BASE 0x0C
|
||||
#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
|
||||
|
|
@ -162,17 +162,25 @@
|
|||
/*
|
||||
* Macros for indirect DCR access
|
||||
*/
|
||||
#define mtcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);mtdcr(CPR0_CFGDATA,d); } while (0)
|
||||
#define mfcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);d = mfdcr(CPR0_CFGDATA); } while (0)
|
||||
#define mtcpr(reg, d) \
|
||||
do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
|
||||
#define mfcpr(reg, d) \
|
||||
do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
|
||||
|
||||
#define mtebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);mtdcr(EBC0_CFGDATA,d); } while (0)
|
||||
#define mfebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);d = mfdcr(EBC0_CFGDATA); } while (0)
|
||||
#define mtebc(reg, d) \
|
||||
do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
|
||||
#define mfebc(reg, d) \
|
||||
do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
|
||||
|
||||
#define mtsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,d); } while (0)
|
||||
#define mfsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);d = mfdcr(SDRAM0_CFGDATA); } while (0)
|
||||
#define mtsdram(reg, d) \
|
||||
do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
|
||||
#define mfsdram(reg, d) \
|
||||
do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
|
||||
|
||||
#define mtsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);mtdcr(SDR0_CFGDATA,d); } while (0)
|
||||
#define mfsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);d = mfdcr(SDR0_CFGDATA); } while (0)
|
||||
#define mtsdr(reg, d) \
|
||||
do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
|
||||
#define mfsdr(reg, d) \
|
||||
do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue