mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-06-17 04:01:38 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
This commit is contained in:
commit
dd758c6720
35 changed files with 111 additions and 41 deletions
|
@ -476,6 +476,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \
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||||||
sun50i-a64-amarula-relic.dtb \
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sun50i-a64-amarula-relic.dtb \
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||||||
sun50i-a64-bananapi-m64.dtb \
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sun50i-a64-bananapi-m64.dtb \
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||||||
sun50i-a64-nanopi-a64.dtb \
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sun50i-a64-nanopi-a64.dtb \
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||||||
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sun50i-a64-oceanic-5205-5inmfd.dtb \
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||||||
sun50i-a64-olinuxino.dtb \
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sun50i-a64-olinuxino.dtb \
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||||||
sun50i-a64-orangepi-win.dtb \
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sun50i-a64-orangepi-win.dtb \
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||||||
sun50i-a64-pine64-lts.dtb \
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sun50i-a64-pine64-lts.dtb \
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||||||
|
|
68
arch/arm/dts/sun50i-a64-oceanic-5205-5inmfd.dts
Normal file
68
arch/arm/dts/sun50i-a64-oceanic-5205-5inmfd.dts
Normal file
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@ -0,0 +1,68 @@
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||||||
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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||||||
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/*
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* Copyright (C) 2019 Oceanic Systems (UK) Ltd.
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* Copyright (C) 2019 Amarula Solutions B.V.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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||||||
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/dts-v1/;
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||||||
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#include "sun50i-a64-sopine.dtsi"
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|
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||||||
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/ {
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model = "Oceanic 5205 5inMFD";
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compatible = "oceanic,5205-5inmfd", "allwinner,sun50i-a64";
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||||||
|
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||||||
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aliases {
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||||||
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ethernet0 = &emac;
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||||||
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serial0 = &uart0;
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};
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|
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||||||
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chosen {
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stdout-path = "serial0:115200n8";
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||||||
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};
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||||||
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};
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||||||
|
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||||||
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&ehci0 {
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status = "okay";
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};
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|
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&emac {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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phy-mode = "rgmii";
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phy-handle = <&ext_rgmii_phy>;
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phy-supply = <®_dc1sw>;
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||||||
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allwinner,tx-delay-ps = <600>;
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||||||
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status = "okay";
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||||||
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};
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||||||
|
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||||||
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&mdio {
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ext_rgmii_phy: ethernet-phy@1 {
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||||||
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compatible = "ethernet-phy-ieee802.3-c22";
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||||||
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reg = <1>;
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||||||
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};
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||||||
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};
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||||||
|
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||||||
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&ohci0 {
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status = "okay";
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||||||
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};
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||||||
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||||||
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®_dc1sw {
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regulator-name = "vcc-phy";
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||||||
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};
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||||||
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pb_pins>;
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status = "okay";
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};
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|
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||||||
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&usb_otg {
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dr_mode = "host";
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status = "okay";
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||||||
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};
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||||||
|
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||||||
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&usbphy {
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||||||
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status = "okay";
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||||||
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};
|
|
@ -28,6 +28,8 @@
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#define SUNXI_BOOTED_FROM_NAND 1
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#define SUNXI_BOOTED_FROM_NAND 1
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#define SUNXI_BOOTED_FROM_MMC2 2
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#define SUNXI_BOOTED_FROM_MMC2 2
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||||||
#define SUNXI_BOOTED_FROM_SPI 3
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#define SUNXI_BOOTED_FROM_SPI 3
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#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10
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||||||
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#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12
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||||||
|
|
||||||
/* boot head definition from sun4i boot code */
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/* boot head definition from sun4i boot code */
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||||||
struct boot_file_head {
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struct boot_file_head {
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||||||
|
|
|
@ -426,10 +426,11 @@ endif
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||||||
|
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||||||
config DRAM_ZQ
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config DRAM_ZQ
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int "sunxi dram zq value"
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int "sunxi dram zq value"
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default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
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default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
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MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
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default 127 if MACH_SUN7I
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default 127 if MACH_SUN7I
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||||||
default 14779 if MACH_SUN8I_V3S
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default 14779 if MACH_SUN8I_V3S
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||||||
default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
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default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
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||||||
default 4145117 if MACH_SUN9I
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default 4145117 if MACH_SUN9I
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||||||
default 3881915 if MACH_SUN50I
|
default 3881915 if MACH_SUN50I
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||||||
---help---
|
---help---
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||||||
|
@ -438,6 +439,7 @@ config DRAM_ZQ
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config DRAM_ODT_EN
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config DRAM_ODT_EN
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bool "sunxi dram odt enable"
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bool "sunxi dram odt enable"
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default y if MACH_SUN8I_A23
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default y if MACH_SUN8I_A23
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default y if MACH_SUNXI_H3_H5
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default y if MACH_SUN8I_R40
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default y if MACH_SUN8I_R40
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default y if MACH_SUN50I
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default y if MACH_SUN50I
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||||||
default y if MACH_SUN50I_H6
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default y if MACH_SUN50I_H6
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||||||
|
|
|
@ -240,10 +240,12 @@ uint32_t sunxi_get_boot_device(void)
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boot_source = readb(SPL_ADDR + 0x28);
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boot_source = readb(SPL_ADDR + 0x28);
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||||||
switch (boot_source) {
|
switch (boot_source) {
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case SUNXI_BOOTED_FROM_MMC0:
|
case SUNXI_BOOTED_FROM_MMC0:
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||||||
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case SUNXI_BOOTED_FROM_MMC0_HIGH:
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||||||
return BOOT_DEVICE_MMC1;
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return BOOT_DEVICE_MMC1;
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||||||
case SUNXI_BOOTED_FROM_NAND:
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case SUNXI_BOOTED_FROM_NAND:
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||||||
return BOOT_DEVICE_NAND;
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return BOOT_DEVICE_NAND;
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||||||
case SUNXI_BOOTED_FROM_MMC2:
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case SUNXI_BOOTED_FROM_MMC2:
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case SUNXI_BOOTED_FROM_MMC2_HIGH:
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return BOOT_DEVICE_MMC2;
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return BOOT_DEVICE_MMC2;
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case SUNXI_BOOTED_FROM_SPI:
|
case SUNXI_BOOTED_FROM_SPI:
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||||||
return BOOT_DEVICE_SPI;
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return BOOT_DEVICE_SPI;
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||||||
|
|
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@ -152,7 +152,7 @@ static void auto_set_timing_para(struct dram_para *para)
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reg_val &= ~(0xff << 8);
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reg_val &= ~(0xff << 8);
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reg_val &= ~(0xff << 0);
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reg_val &= ~(0xff << 0);
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reg_val |= (0x33 << 8);
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reg_val |= (0x33 << 8);
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reg_val |= (0x8 << 0);
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reg_val |= (0x10 << 0);
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writel(reg_val, &mctl_ctl->dramtmg8);
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writel(reg_val, &mctl_ctl->dramtmg8);
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||||||
/* Set phy interface time */
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/* Set phy interface time */
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||||||
reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
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reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
|
||||||
|
|
|
@ -341,6 +341,11 @@ M: FUKAUMI Naoki <naobsd@gmail.com>
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||||||
S: Maintained
|
S: Maintained
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||||||
F: configs/Nintendo_NES_Classic_Edition_defconfig
|
F: configs/Nintendo_NES_Classic_Edition_defconfig
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||||||
|
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||||||
|
OCEANIC 5205 5INMFD BOARD
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||||||
|
M: Jagan Teki <jagan@amarulasolutions.com>
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||||||
|
S: Maintained
|
||||||
|
F: configs/oceanic_5205_5inmfd_defconfig
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||||||
|
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||||||
OLIMEX A20-SOM204 BOARD
|
OLIMEX A20-SOM204 BOARD
|
||||||
M: Stefan Mavrodiev <stefan@olimex.com>
|
M: Stefan Mavrodiev <stefan@olimex.com>
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||||||
S: Maintained
|
S: Maintained
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
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||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
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||||||
CONFIG_MACH_SUN8I_H3=y
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CONFIG_MACH_SUN8I_H3=y
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CONFIG_DRAM_CLK=672
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CONFIG_DRAM_CLK=672
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CONFIG_DRAM_ZQ=3881979
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CONFIG_DRAM_ODT_EN=y
|
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CONFIG_MACPWR="PD6"
|
CONFIG_MACPWR="PD6"
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CONFIG_MMC_SUNXI_SLOT_EXTRA=2
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CONFIG_MMC_SUNXI_SLOT_EXTRA=2
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||||||
CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
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CONFIG_SPL=y
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CONFIG_SPL=y
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||||||
CONFIG_MACH_SUN50I_H5=y
|
CONFIG_MACH_SUN50I_H5=y
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CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
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CONFIG_DRAM_ZQ=3881979
|
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||||||
CONFIG_DRAM_ODT_EN=y
|
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CONFIG_MACPWR="PD6"
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CONFIG_MACPWR="PD6"
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CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_NR_DRAM_BANKS=1
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||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
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||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
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||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
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||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
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||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_MMC0_CD_PIN=""
|
CONFIG_MMC0_CD_PIN=""
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
# CONFIG_CMD_FLASH is not set
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN50I_H5=y
|
CONFIG_MACH_SUN50I_H5=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
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||||||
CONFIG_DRAM_ZQ=3881977
|
CONFIG_DRAM_ZQ=3881977
|
||||||
|
# CONFIG_DRAM_ODT_EN is not set
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN50I_H5=y
|
CONFIG_MACH_SUN50I_H5=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
# CONFIG_CMD_FLASH is not set
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_MMC0_CD_PIN="PH13"
|
CONFIG_MMC0_CD_PIN="PH13"
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN50I_H5=y
|
CONFIG_MACH_SUN50I_H5=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881977
|
CONFIG_DRAM_ZQ=3881977
|
||||||
|
# CONFIG_DRAM_ODT_EN is not set
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
# CONFIG_CMD_FLASH is not set
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
# CONFIG_VIDEO_DE2 is not set
|
# CONFIG_VIDEO_DE2 is not set
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
# CONFIG_VIDEO_DE2 is not set
|
# CONFIG_VIDEO_DE2 is not set
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN50I_H5=y
|
CONFIG_MACH_SUN50I_H5=y
|
||||||
CONFIG_DRAM_CLK=408
|
CONFIG_DRAM_CLK=408
|
||||||
CONFIG_DRAM_ZQ=3881977
|
CONFIG_DRAM_ZQ=3881977
|
||||||
|
# CONFIG_DRAM_ODT_EN is not set
|
||||||
CONFIG_MACPWR="PD6"
|
CONFIG_MACPWR="PD6"
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
|
20
configs/oceanic_5205_5inmfd_defconfig
Normal file
20
configs/oceanic_5205_5inmfd_defconfig
Normal file
|
@ -0,0 +1,20 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_SUNXI=y
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_MACH_SUN50I=y
|
||||||
|
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
|
||||||
|
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
|
||||||
|
CONFIG_DRAM_CLK=552
|
||||||
|
CONFIG_DRAM_ZQ=3881949
|
||||||
|
CONFIG_MMC0_CD_PIN=""
|
||||||
|
CONFIG_SPL_SPI_SUNXI=y
|
||||||
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
# CONFIG_SPL_DOS_PARTITION is not set
|
||||||
|
# CONFIG_SPL_EFI_PARTITION is not set
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-oceanic-5205-5inmfd"
|
||||||
|
CONFIG_SUN8I_EMAC=y
|
||||||
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_OHCI_HCD=y
|
||||||
|
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
|
|
@ -4,8 +4,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_USB1_VBUS_PIN="PG13"
|
CONFIG_USB1_VBUS_PIN="PG13"
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
# CONFIG_CMD_FLASH is not set
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
# CONFIG_CMD_FLASH is not set
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN50I_H5=y
|
CONFIG_MACH_SUN50I_H5=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881977
|
CONFIG_DRAM_ZQ=3881977
|
||||||
|
# CONFIG_DRAM_ODT_EN is not set
|
||||||
CONFIG_MACPWR="PD6"
|
CONFIG_MACPWR="PD6"
|
||||||
CONFIG_SPL_SPI_SUNXI=y
|
CONFIG_SPL_SPI_SUNXI=y
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=624
|
CONFIG_DRAM_CLK=624
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
CONFIG_SPL_I2C_SUPPORT=y
|
CONFIG_SPL_I2C_SUPPORT=y
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=624
|
CONFIG_DRAM_CLK=624
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_MACPWR="PD6"
|
CONFIG_MACPWR="PD6"
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
CONFIG_MACPWR="PD6"
|
CONFIG_MACPWR="PD6"
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_USB1_VBUS_PIN="PG13"
|
CONFIG_USB1_VBUS_PIN="PG13"
|
||||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN50I_H5=y
|
CONFIG_MACH_SUN50I_H5=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881977
|
CONFIG_DRAM_ZQ=3881977
|
||||||
|
# CONFIG_DRAM_ODT_EN is not set
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
# CONFIG_CMD_FLASH is not set
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=624
|
CONFIG_DRAM_CLK=624
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
# CONFIG_VIDEO_DE2 is not set
|
# CONFIG_VIDEO_DE2 is not set
|
||||||
CONFIG_SPL_SPI_SUNXI=y
|
CONFIG_SPL_SPI_SUNXI=y
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y
|
||||||
CONFIG_SPL=y
|
CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN8I_H3=y
|
CONFIG_MACH_SUN8I_H3=y
|
||||||
CONFIG_DRAM_CLK=624
|
CONFIG_DRAM_CLK=624
|
||||||
CONFIG_DRAM_ZQ=3881979
|
|
||||||
CONFIG_DRAM_ODT_EN=y
|
|
||||||
# CONFIG_VIDEO_DE2 is not set
|
# CONFIG_VIDEO_DE2 is not set
|
||||||
CONFIG_SPL_SPI_SUNXI=y
|
CONFIG_SPL_SPI_SUNXI=y
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN50I_H5=y
|
CONFIG_MACH_SUN50I_H5=y
|
||||||
CONFIG_DRAM_CLK=672
|
CONFIG_DRAM_CLK=672
|
||||||
CONFIG_DRAM_ZQ=3881977
|
CONFIG_DRAM_ZQ=3881977
|
||||||
|
# CONFIG_DRAM_ODT_EN is not set
|
||||||
CONFIG_MMC0_CD_PIN="PH13"
|
CONFIG_MMC0_CD_PIN="PH13"
|
||||||
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_SPL=y
|
||||||
CONFIG_MACH_SUN50I_H5=y
|
CONFIG_MACH_SUN50I_H5=y
|
||||||
CONFIG_DRAM_CLK=624
|
CONFIG_DRAM_CLK=624
|
||||||
CONFIG_DRAM_ZQ=3881977
|
CONFIG_DRAM_ZQ=3881977
|
||||||
|
# CONFIG_DRAM_ODT_EN is not set
|
||||||
CONFIG_NR_DRAM_BANKS=1
|
CONFIG_NR_DRAM_BANKS=1
|
||||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
# CONFIG_CMD_FLASH is not set
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
|
|
@ -16,4 +16,5 @@ CONFIG_NR_DRAM_BANKS=1
|
||||||
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-lts"
|
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-lts"
|
||||||
CONFIG_SUN8I_EMAC=y
|
CONFIG_SUN8I_EMAC=y
|
||||||
CONFIG_USB_EHCI_HCD=y
|
CONFIG_USB_EHCI_HCD=y
|
||||||
|
CONFIG_USB_OHCI_HCD=y
|
||||||
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
|
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
|
||||||
|
|
Loading…
Add table
Reference in a new issue