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MIPS: allow systems to skip loads during cache init
Current MIPS systems do not require that loads be performed to force the parity of cache lines, a simple invalidate by clearing the tag for each line will suffice. Thus this patch makes the loads & subsequent second invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD option, and defines that for existing mips32 targets. Exceptions are malta where this is known to be unnecessary, and qemu-mips where caches are not implemented. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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parent
ca4e833cd6
commit
dd7c72006e
2 changed files with 19 additions and 6 deletions
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@ -36,6 +36,7 @@ config TARGET_VCT
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SYS_MIPS_CACHE_INIT_RAM_LOAD
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config TARGET_DBAU1X00
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bool "Support dbau1x00"
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@ -43,12 +44,14 @@ config TARGET_DBAU1X00
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select SUPPORTS_LITTLE_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SYS_MIPS_CACHE_INIT_RAM_LOAD
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config TARGET_PB1X00
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bool "Support pb1x00"
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select SUPPORTS_LITTLE_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SUPPORTS_CPU_MIPS32_R2
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select SYS_MIPS_CACHE_INIT_RAM_LOAD
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endchoice
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@ -185,6 +188,9 @@ config 64BIT
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config SWAP_IO_SPACE
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bool
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config SYS_MIPS_CACHE_INIT_RAM_LOAD
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bool
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endif
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endmenu
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@ -113,6 +113,8 @@ LEAF(mips_cache_reset)
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l1_info t3, t9, MIPS_CONF1_DA_SHIFT
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#endif
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* Determine the largest L1 cache size */
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#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
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#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
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@ -134,14 +136,15 @@ LEAF(mips_cache_reset)
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f_fill64 a0, -64, zero
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bne a0, a1, 2b
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/*
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* The caches are probably in an indeterminate state,
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* so we force good parity into them by doing an
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* invalidate, load/fill, invalidate for each line.
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*/
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#endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
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/*
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* Assume bottom of RAM will generate good parity for the cache.
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* The caches are probably in an indeterminate state, so we force good
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* parity into them by doing an invalidate for each line. If
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* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is set then we'll proceed to
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* perform a load/fill & a further invalidate for each line, assuming
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* that the bottom of RAM (having just been cleared) will generate good
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* parity for the cache.
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*/
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/*
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@ -153,12 +156,14 @@ LEAF(mips_cache_reset)
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PTR_ADDU t1, t0, t2
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/* clear tag to invalidate */
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cache_loop t0, t1, t8, INDEX_STORE_TAG_I
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* fill once, so data field parity is correct */
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PTR_LI t0, INDEX_BASE
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cache_loop t0, t1, t8, FILL
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/* invalidate again - prudent but not strictly neccessary */
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PTR_LI t0, INDEX_BASE
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cache_loop t0, t1, t8, INDEX_STORE_TAG_I
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#endif
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/*
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* then initialize D-cache.
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@ -169,6 +174,7 @@ LEAF(mips_cache_reset)
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PTR_ADDU t1, t0, t3
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/* clear all tags */
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cache_loop t0, t1, t9, INDEX_STORE_TAG_D
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#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* load from each line (in cached space) */
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PTR_LI t0, INDEX_BASE
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2: LONG_L zero, 0(t0)
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@ -177,6 +183,7 @@ LEAF(mips_cache_reset)
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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cache_loop t0, t1, t9, INDEX_STORE_TAG_D
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#endif
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3: jr ra
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END(mips_cache_reset)
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