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Fix style issues primarily in 85xx and 83xx boards.

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This commit is contained in:
Jon Loeliger 2005-08-01 13:20:47 -05:00
parent b0e3294923
commit de1d0a6995
25 changed files with 544 additions and 567 deletions
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8
CHANGELOG
View file

@ -1,6 +1,14 @@
====================================================================== ======================================================================
Changes for U-Boot 1.1.3: Changes for U-Boot 1.1.3:
====================================================================== ======================================================================
* Patch by Jon Loeliger
Fix style issues primarily in 85xx and 83xx boards.
- C++ comments
- Trailing white space
- Indentation not by TAB
- Excessive amount of empty lines
- Trailing empty lines
* Patch by Ron Alder, 11 July 2005 * Patch by Ron Alder, 11 July 2005
Add Xianghua Xiao and Lunsheng Wang's support for the Add Xianghua Xiao and Lunsheng Wang's support for the
GDA MPC8540 EVAL board. GDA MPC8540 EVAL board.

28
board/mpc8349ads/mpc8349ads.c
View file

@ -53,7 +53,6 @@ int board_early_init_f (void)
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
long int initdram (int board_type) long int initdram (int board_type)
{ {
volatile immap_t *im = (immap_t *)CFG_IMMRBAR; volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
@ -148,7 +147,7 @@ int checkboard (void)
return 0; return 0;
} }
#if defined(CONFIG_PCI) //copy from mpc85xx #if defined(CONFIG_PCI)
/* /*
* Initialize PCI Devices, report devices found * Initialize PCI Devices, report devices found
*/ */
@ -190,8 +189,8 @@ pci_init_board(void)
} }
/* /*
if MPC8349ADS is soldered with SDRAM * if MPC8349ADS is soldered with SDRAM
*/ */
#if defined(CFG_BR2_PRELIM) \ #if defined(CFG_BR2_PRELIM) \
&& defined(CFG_OR2_PRELIM) \ && defined(CFG_OR2_PRELIM) \
&& defined(CFG_LBLAWBAR2_PRELIM) \ && defined(CFG_LBLAWBAR2_PRELIM) \
@ -207,7 +206,6 @@ sdram_init(void)
volatile lbus8349_t *lbc= &immap->lbus; volatile lbus8349_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: "); puts("\n SDRAM on Local Bus: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
@ -233,32 +231,33 @@ sdram_init(void)
lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/ lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
asm("sync"); asm("sync");
/*1 times*/ /*1 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*2 times*/ /*2 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*3 times*/ /*3 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*4 times*/ /*4 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*5 times*/ /*5 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*6 times*/ /*6 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*7 times*/ /*7 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*8 times*/ /*8 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation*/ /* 0x58636733;mode register write operation */
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync"); asm("sync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
@ -275,4 +274,3 @@ sdram_init(void)
put("SDRAM on Local Bus is NOT available!\n"); put("SDRAM on Local Bus is NOT available!\n");
} }
#endif #endif

40
board/mpc8540eval/mpc8540eval.c
View file

@ -23,34 +23,15 @@
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
extern long int spd_sdram (void);
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/immap_85xx.h> #include <asm/immap_85xx.h>
#include <spd.h> #include <spd.h>
extern long int spd_sdram (void);
long int fixed_sdram (void); long int fixed_sdram (void);
/* MPC8540ADS Board Status & Control Registers */
#if 0
typedef struct bscr_ {
unsigned long bcsr0;
unsigned long bcsr1;
unsigned long bcsr2;
unsigned long bcsr3;
unsigned long bcsr4;
unsigned long bcsr5;
unsigned long bcsr6;
unsigned long bcsr7;
} bcsr_t;
#endif
int board_pre_init (void) int board_pre_init (void)
{ {
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
@ -74,7 +55,8 @@ int checkboard (void)
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|| (CFG_LBC_LCRR & 0x0f) == 8) { || (CFG_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f)); printf ("\tLBC: %lu MHz\n",
sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
} else { } else {
printf("\tLBC: unknown\n"); printf("\tLBC: unknown\n");
} }
@ -199,7 +181,6 @@ long int initdram (int board_type)
return dram_size; return dram_size;
} }
#if defined(CFG_DRAM_TEST) #if defined(CFG_DRAM_TEST)
int testdram (void) int testdram (void)
{ {
@ -234,14 +215,13 @@ int testdram (void)
} }
#endif #endif
#if !defined(CONFIG_SPD_EEPROM) #if !defined(CONFIG_SPD_EEPROM)
/************************************************************************* /*************************************************************************
* fixed sdram init -- doesn't use serial presence detect. * fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ ************************************************************************/
long int fixed_sdram (void) long int fixed_sdram (void)
{ {
#ifndef CFG_RAMBOOT #ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr; volatile ccsr_ddr_t *ddr= &immap->im_ddr;
@ -251,21 +231,21 @@ long int fixed_sdram (void)
ddr->timing_cfg_2 = CFG_DDR_TIMING_2; ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE; ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL; ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC) #if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D; ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000; ddr->err_sbe = 0x00ff0000;
#endif #endif
asm("sync;isync;msync"); asm("sync;isync;msync");
udelay(500); udelay(500);
#if defined (CONFIG_DDR_ECC) #if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */ /* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else #else
ddr->sdram_cfg = CFG_DDR_CONTROL; ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif #endif
asm("sync; isync; msync"); asm("sync; isync; msync");
udelay(500); udelay(500);
#endif #endif
return (CFG_SDRAM_SIZE * 1024 * 1024); return (CFG_SDRAM_SIZE * 1024 * 1024);
} }
#endif /* !defined(CONFIG_SPD_EEPROM) */ #endif /* !defined(CONFIG_SPD_EEPROM) */

1
common/cmd_usb.c
View file

@ -457,7 +457,6 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* try to recognize storage devices immediately */ /* try to recognize storage devices immediately */
if (i >= 0) if (i >= 0)
usb_stor_curr_dev = usb_stor_scan(1); usb_stor_curr_dev = usb_stor_scan(1);
#endif #endif
return 0; return 0;
} }

3
common/usb.c
View file

@ -523,7 +523,6 @@ int usb_get_string(struct usb_device *dev, unsigned short langid, unsigned char
if (result > 0) if (result > 0)
break; break;
} }
return result; return result;
} }
@ -724,7 +723,6 @@ int usb_new_device(struct usb_device *dev)
/* find the port number we're at */ /* find the port number we're at */
if (parent) { if (parent) {
for (j = 0; j < parent->maxchild; j++) { for (j = 0; j < parent->maxchild; j++) {
if (parent->children[j] == dev) { if (parent->children[j] == dev) {
port = j; port = j;
@ -958,7 +956,6 @@ static int hub_port_reset(struct usb_device *dev, int port,
return -1; return -1;
if (portstatus & USB_PORT_STAT_ENABLE) { if (portstatus & USB_PORT_STAT_ENABLE) {
break; break;
} }

2
cpu/arm920t/s3c24x0/usb_ohci.c
View file

@ -53,7 +53,6 @@
#define OHCI_USE_NPS /* force NoPowerSwitching mode */ #define OHCI_USE_NPS /* force NoPowerSwitching mode */
#undef OHCI_VERBOSE_DEBUG /* not always helpful */ #undef OHCI_VERBOSE_DEBUG /* not always helpful */
/* For initializing controller (mask in an HCFS mode too) */ /* For initializing controller (mask in an HCFS mode too) */
#define OHCI_CONTROL_INIT \ #define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
@ -1221,7 +1220,6 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
} }
/*-------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------*/
/* common code for handling submit messages - used for all but root hub */ /* common code for handling submit messages - used for all but root hub */

1
cpu/mpc83xx/cpu_init.c
View file

@ -161,4 +161,3 @@ int cpu_init_r (void)
{ {
return 0; return 0;
} }

11
cpu/mpc83xx/pci.c
View file

@ -89,7 +89,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
//#if defined(CONFIG_PCI_2)
pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK); pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
@ -98,7 +98,6 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
//#endif
/* /*
* Configure PCI Inbound Translation Windows * Configure PCI Inbound Translation Windows
@ -131,13 +130,13 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
val8 = 0x34; val8 = 0x34;
ret = i2c_write(0x26,0x7,1,&val8,1); ret = i2c_write(0x26,0x7,1,&val8,1);
#if defined(PCI_64BIT) #if defined(PCI_64BIT)
val8 = 0xf4; // PMC2<->PCI1 64bit val8 = 0xf4; /* PMC2<->PCI1 64bit */
#elif defined(PCI_ALL_PCI1) #elif defined(PCI_ALL_PCI1)
val8 = 0xf3; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */
#elif defined(PCI_ONE_PCI1) #elif defined(PCI_ONE_PCI1)
val8 = 0xf9; // PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */
#elif defined(PCI_TWO_PCI1) #elif defined(PCI_TWO_PCI1)
val8 = 0xf5; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
#else #else
val8 = 0xf5; val8 = 0xf5;
#endif #endif

17
cpu/mpc83xx/spd_sdram.c
View file

@ -36,20 +36,16 @@
#ifdef CONFIG_SPD_EEPROM #ifdef CONFIG_SPD_EEPROM
#if defined(CONFIG_DDR_ECC) #if defined(CONFIG_DDR_ECC)
extern void dma_init(void); extern void dma_init(void);
extern uint dma_check(void); extern uint dma_check(void);
extern int dma_xfer(void *dest, uint count, void *src); extern int dma_xfer(void *dest, uint count, void *src);
#endif #endif
#ifndef CFG_READ_SPD #ifndef CFG_READ_SPD
#define CFG_READ_SPD i2c_read #define CFG_READ_SPD i2c_read
#endif #endif
/* /*
* Convert picoseconds into clock cycles (rounding up if needed). * Convert picoseconds into clock cycles (rounding up if needed).
*/ */
@ -67,14 +63,12 @@ picos_to_clk(int picos)
return clks; return clks;
} }
unsigned int unsigned int
banksize(unsigned char row_dens) banksize(unsigned char row_dens)
{ {
return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
} }
long int spd_sdram(int(read_spd)(uint addr)) long int spd_sdram(int(read_spd)(uint addr))
{ {
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
@ -298,9 +292,12 @@ long int spd_sdram(int(read_spd)(uint addr))
udelay(500); udelay(500);
/*
ddr->sdram_clk_cntl = 0x82000000;/*SS_EN=1, CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM clock cycle after address/command*/ * SS_EN=1,
* CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
* clock cycle after address/command
*/
ddr->sdram_clk_cntl = 0x82000000;
/* /*
* Figure out the settings for the sdram_cfg register. Build up * Figure out the settings for the sdram_cfg register. Build up
@ -339,7 +336,6 @@ long int spd_sdram(int(read_spd)(uint addr))
#endif #endif
ddr->sdram_cfg = tmp; ddr->sdram_cfg = tmp;
asm("sync;isync"); asm("sync;isync");
udelay(500); udelay(500);
@ -347,7 +343,6 @@ long int spd_sdram(int(read_spd)(uint addr))
return memsize;/*in MBytes*/ return memsize;/*in MBytes*/
} }
#endif /* CONFIG_SPD_EEPROM */ #endif /* CONFIG_SPD_EEPROM */

5
cpu/mpc83xx/speed.c
View file

@ -133,7 +133,6 @@ int get_clocks (void)
/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */ /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
/* FIXME: findout if there is a way to issue some warning */ /* FIXME: findout if there is a way to issue some warning */
return -2; return -2;
} }
if (im->clk.spmr & SPMR_CKID) { if (im->clk.spmr & SPMR_CKID) {
pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */ pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
@ -157,7 +156,6 @@ int get_clocks (void)
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */ #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
/* we have up to date pci_sync_in */ /* we have up to date pci_sync_in */
spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
@ -419,6 +417,5 @@ int print_clock_conf (void)
} }
putc ('\n'); putc ('\n');
#endif #endif
return (0); return 0;
} }

3
cpu/mpc83xx/start.S
View file

@ -101,7 +101,6 @@ version_string:
_HRCW_TABLE_ENTRY(CFG_HRCW_HIGH) _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
#ifndef CONFIG_DEFAULT_IMMR #ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined #error CONFIG_DEFAULT_IMMR must be defined
#endif /* CFG_DEFAULT_IMMR */ #endif /* CFG_DEFAULT_IMMR */
@ -665,8 +664,6 @@ relocate_code:
stwu r0,-4(r7) stwu r0,-4(r7)
bdnz 3b bdnz 3b
/* /*
* Now flush the cache: note that we must start from a cache aligned * Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line. * address. Otherwise we might miss one cache line.

6
drivers/tsec.c
View file

@ -524,9 +524,9 @@ static void adjust_link(struct eth_device *dev)
regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
| MACCFG2_MII); | MACCFG2_MII);
/* If We're in reduced mode, we /* If We're in reduced mode, we need
* need to say whether we're 10 * to say whether we're 10 or 100 MB.
* or 100 MB. */ */
if ((priv->speed == 100) if ((priv->speed == 100)
&& (priv->flags & TSEC_REDUCED)) && (priv->flags & TSEC_REDUCED))
regs->ecntrl |= ECNTRL_R100; regs->ecntrl |= ECNTRL_R100;

1
include/asm-ppc/i2c.h
View file

@ -38,7 +38,6 @@ typedef struct i2c
#define I2C_ADR_RES ~(I2C_ADR) #define I2C_ADR_RES ~(I2C_ADR)
u8 res0[3]; u8 res0[3];
u8 fdr; /**< I2C frequency divider register */ u8 fdr; /**< I2C frequency divider register */
#define IC2_FDR 0x3F #define IC2_FDR 0x3F
#define IC2_FDR_SHIFT 0 #define IC2_FDR_SHIFT 0
#define IC2_FDR_RES ~(IC2_FDR) #define IC2_FDR_RES ~(IC2_FDR)

124
include/asm-ppc/immap_83xx.h
View file

@ -21,15 +21,27 @@
*/ */
typedef struct law8349 { typedef struct law8349 {
u32 bar; /* LBIU local access window base address register */ u32 bar; /* LBIU local access window base address register */
#define LAWBAR_BAR 0xFFFFF000 /* Identifies the 20 most-significant address bits of the base of local access window n. The specified base address should be aligned to the window size, as defined by LBLAWARn[SIZE]. */ /* Identifies the 20 most-significant address bits of the base of local
* access window n. The specified base address should be aligned to the
* window size, as defined by LBLAWARn[SIZE].
*/
#define LAWBAR_BAR 0xFFFFF000
#define LAWBAR_RES ~(LAWBAR_BAR) #define LAWBAR_RES ~(LAWBAR_BAR)
u32 ar; /* LBIU local access window attribute register */ u32 ar; /* LBIU local access window attribute register */
/* /*
* This Macro were moved into mmu.h * This Macro were moved into mmu.h
*/ */
#if 0 #if 0
#define LAWAR_EN 0x80000000 /* 0 The local bus local access window n is disabled. 1 The local bus local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields combine to identify an address range for this window. */ /* 0 The local bus local access window n is disabled. 1 The local bus
#define LAWAR_SIZE 0x0000003F /* Identifies the size of the window from the starting address. Window size is 2^(SIZE+1) bytes. 000000–001010Reserved. Window is undefined. */ * local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields
* combine to identify an address range for this window.
*/
#define LAWAR_EN 0x80000000
/* Identifies the size of the window from the starting address. Window
* size is 2^(SIZE+1) bytes. 000000–001010Reserved. Window is
* undefined.
*/
#define LAWAR_SIZE 0x0000003F
#define LAWAR_SIZE_4K 0x0000000B #define LAWAR_SIZE_4K 0x0000000B
#define LAWAR_SIZE_8K 0x0000000C #define LAWAR_SIZE_8K 0x0000000C
#define LAWAR_SIZE_16K 0x0000000D #define LAWAR_SIZE_16K 0x0000000D
@ -62,7 +74,10 @@ typedef struct sysconf8349 {
u32 immrbar; /* Internal memory map base address register */ u32 immrbar; /* Internal memory map base address register */
u8 res0[0x04]; u8 res0[0x04];
u32 altcbar; /* Alternate configuration base address register */ u32 altcbar; /* Alternate configuration base address register */
#define ALTCBAR_BASE_ADDR 0xFFF00000 /* Identifies the12 most significant address bits of an alternate base address used for boot sequencer configuration accesses. */ /* Identifies the12 most significant address bits of an alternate base
* address used for boot sequencer configuration accesses.
*/
#define ALTCBAR_BASE_ADDR 0xFFF00000
#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ #define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
u8 res1[0x14]; u8 res1[0x14];
law8349_t lblaw[4]; /* LBIU local access window */ law8349_t lblaw[4]; /* LBIU local access window */
@ -88,8 +103,9 @@ typedef struct sysconf8349 {
#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */
#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */
#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_TBEN|SPCR_COREPR|SPCR_TSEC1DP \ #define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
|SPCR_TSEC1BDP|SPCR_TSEC1EP|SPCR_TSEC2DP|SPCR_TSEC2BDP|SPCR_TSEC2EP) | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
u32 sicrl; /* System General Purpose Register Low */ u32 sicrl; /* System General Purpose Register Low */
#define SICRL_LDP_A 0x80000000 #define SICRL_LDP_A 0x80000000
#define SICRL_USB0 0x40000000 #define SICRL_USB0 0x40000000
@ -107,10 +123,11 @@ typedef struct sysconf8349 {
#define SICRL_GPIO1_J 0x00008000 #define SICRL_GPIO1_J 0x00008000
#define SICRL_GPIO1_K 0x00004000 #define SICRL_GPIO1_K 0x00004000
#define SICRL_GPIO1_L 0x00003000 #define SICRL_GPIO1_L 0x00003000
#define SICRL_RES ~(SICRL_LDP_A|SICRL_USB0|SICRL_USB1|SICRL_UART|SICRL_GPIO1_A \ #define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
|SICRL_GPIO1_B|SICRL_GPIO1_C|SICRL_GPIO1_D|SICRL_GPIO1_E \ | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
|SICRL_GPIO1_F|SICRL_GPIO1_G|SICRL_GPIO1_H|SICRL_GPIO1_I \ | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
|SICRL_GPIO1_J|SICRL_GPIO1_K|SICRL_GPIO1_L ) | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
| SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
u32 sicrh; /* System General Purpose Register High */ u32 sicrh; /* System General Purpose Register High */
#define SICRH_DDR 0x80000000 #define SICRH_DDR 0x80000000
#define SICRH_TSEC1_A 0x10000000 #define SICRH_TSEC1_A 0x10000000
@ -137,13 +154,15 @@ typedef struct sysconf8349 {
#define SICRH_GPIO2_H 0x00000060 #define SICRH_GPIO2_H 0x00000060
#define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001 #define SICRH_TSOBI2 0x00000001
#define SICRh_RES ~(SICRH_DDR|SICRH_TSEC1_A|SICRH_TSEC1_B|SICRH_TSEC1_C \ #define SICRh_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
|SICRH_TSEC1_D|SICRH_TSEC1_E|SICRH_TSEC1_F|SICRH_TSEC2_A \ | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
|SICRH_TSEC2_B|SICRH_TSEC2_C|SICRH_TSEC2_D|SICRH_TSEC2_E \ | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
|SICRH_TSEC2_F|SICRH_TSEC2_G|SICRH_TSEC2_H|SICRH_GPIO2_A \ | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
|SICRH_GPIO2_B|SICRH_GPIO2_C|SICRH_GPIO2_D|SICRH_GPIO2_E \ | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
|SICRH_GPIO2_F|SICRH_GPIO2_G|SICRH_GPIO2_H|SICRH_TSOBI1 \ | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
|SICRH_TSOBI2) | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
| SICRH_TSOBI2)
u8 res6[0xE4]; u8 res6[0xE4];
} sysconf8349_t; } sysconf8349_t;
@ -275,10 +294,11 @@ typedef struct ipic8349 {
#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ #define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
#define SIIH_I2C2 0x00000002 /* I2C1 interrupt */ #define SIIH_I2C2 0x00000002 /* I2C1 interrupt */
#define SIIH_SPI 0x00000001 /* SPI interrupt */ #define SIIH_SPI 0x00000001 /* SPI interrupt */
#define SIIH_RES ~(SIIH_TSEC1TX|SIIH_TSEC1RX|SIIH_TSEC1ER|SIIH_TSEC2TX \ #define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
|SIIH_TSEC2RX|SIIH_TSEC2ER|SIIH_USB2DR|SIIH_USB2MPH \ | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
|SIIH_UART1 |SIIH_UART2 |SIIH_SEC |SIIH_I2C1 \ | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
|SIIH_I2C2 |SIIH_SPI) | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
| SIIH_I2C2 | SIIH_SPI)
u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */
#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ #define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */
#define SIIL_PIT 0x40000000 /* PIT interrupt */ #define SIIL_PIT 0x40000000 /* PIT interrupt */
@ -302,11 +322,12 @@ typedef struct ipic8349 {
#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ #define SIIL_GTM1 0x00000020 /* GTM1 interrupt */
#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ #define SIIL_GTM5 0x00000010 /* GTM5 interrupt */
#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ #define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */
#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_PCI2 |SIIL_RTCA \ #define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
|SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \ | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
|SIIL_GPIO1|SIIL_GPIO2|SIIL_DDR |SIIL_LBC |SIIL_GTM2 \ | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
|SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \ | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
|SIIL_GTM5 |SIIL_DPTC ) | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
| SIIL_GTM5 |SIIL_DPTC )
u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */
u8 res0[8]; u8 res0[8];
u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */
@ -335,8 +356,9 @@ typedef struct ipic8349 {
#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ #define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */
#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ #define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */
#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ #define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */
#define SEI_RES ~( SEI_IRQ0 |SEI_IRQ1 |SEI_IRQ2 |SEI_IRQ3 |SEI_IRQ4 \ #define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
|SEI_IRQ5 |SEI_IRQ6 |SEI_IRQ7 |SEI_SIRQ0) | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
| SEI_SIRQ0)
u32 secnr; /* System External Interrupt Control Register (SECNR) */ u32 secnr; /* System External Interrupt Control Register (SECNR) */
#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ #define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */
#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ #define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */
@ -350,9 +372,10 @@ typedef struct ipic8349 {
#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ #define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */
#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ #define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */
#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ #define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */
#define SECNR_RES ~( SECNR_MIXB0T|SECNR_MIXB1T|SECNR_MIXA0T|SECNR_SYSA1T \ #define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
|SECNR_EDI0 |SECNR_EDI1 |SECNR_EDI2 |SECNR_EDI3 \ | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
|SECNR_EDI4 |SECNR_EDI5 |SECNR_EDI6 |SECNR_EDI7) | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
| SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
u32 sersr; /* System Error Status Register (SERR) */ u32 sersr; /* System Error Status Register (SERR) */
u32 sermr; /* System Error Mask Register (SERR) */ u32 sermr; /* System Error Mask Register (SERR) */
#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ #define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */
@ -364,8 +387,9 @@ typedef struct ipic8349 {
#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ #define SERR_PCI2 0x02000000 /* PCI2 MCP request */
#define SERR_MU 0x01000000 /* MU MCP request */ #define SERR_MU 0x01000000 /* MU MCP request */
#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ #define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */
#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_DDR |SERR_LBC \ #define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
|SERR_PCI1|SERR_PCI2|SERR_MU |SERR_RNC ) |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
|SERR_RNC )
u32 sercr; /* System Error Control Register (SERCR) */ u32 sercr; /* System Error Control Register (SERCR) */
#define SERCR_MCPR 0x00000001 /* MCP Route */ #define SERCR_MCPR 0x00000001 /* MCP Route */
#define SERCR_RES ~(SERCR_MCPR) #define SERCR_RES ~(SERCR_MCPR)
@ -450,9 +474,11 @@ typedef struct reset8349 {
#define RCWH_TPR 0x00000100 /* TPR */ #define RCWH_TPR 0x00000100 /* TPR */
#define RCWH_TLE 0x00000008 /* TLE */ #define RCWH_TLE 0x00000008 /* TLE */
#define RCWH_LALE 0x00000004 /* LALE */ #define RCWH_LALE 0x00000004 /* LALE */
#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCI64|RCWH_PCI1ARB|RCWH_PCI2ARB \ #define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
|RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN|RCWH_ROMLOC \ | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
|RCWH_TSEC1M|RCWH_TSEC2M|RCWH_TPR|RCWH_TLE|RCWH_LALE) | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
| RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
| RCWH_TLE | RCWH_LALE)
u8 res0[8]; u8 res0[8];
u32 rsr; /* Reset status Register */ u32 rsr; /* Reset status Register */
#define RSR_RSTSRC 0xE0000000 /* Reset source */ #define RSR_RSTSRC 0xE0000000 /* Reset source */
@ -477,7 +503,7 @@ typedef struct reset8349 {
#define RSR_SRS_SHIFT 1 #define RSR_SRS_SHIFT 1
#define RSR_HRS 0x00000001 /* hard reset status */ #define RSR_HRS 0x00000001 /* hard reset status */
#define RSR_HRS_SHIFT 0 #define RSR_HRS_SHIFT 0
#define RSR_RES ~(RSR_RSTSRC|RSR_BSF|RSR_SWSR|RSR_SWHR|RSR_JHRS|RSR_JSRS|RSR_CSHR|RSR_SWRS|RSR_BMRS|RSR_SRS|RSR_HRS) #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
u32 rmr; /* Reset mode Register */ u32 rmr; /* Reset mode Register */
#define RMR_CSRE 0x00000001 /* checkstop reset enable */ #define RMR_CSRE 0x00000001 /* checkstop reset enable */
#define RMR_CSRE_SHIFT 0 #define RMR_CSRE_SHIFT 0
@ -486,7 +512,7 @@ typedef struct reset8349 {
u32 rcr; /* Reset Control Register */ u32 rcr; /* Reset Control Register */
#define RCR_SWHR 0x00000002 /* software hard reset */ #define RCR_SWHR 0x00000002 /* software hard reset */
#define RCR_SWSR 0x00000001 /* software soft reset */ #define RCR_SWSR 0x00000001 /* software soft reset */
#define RCR_RES ~(RCR_SWHR|RCR_SWSR) #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
u32 rcer; /* Reset Control Enable Register */ u32 rcer; /* Reset Control Enable Register */
#define RCER_CRE 0x00000001 /* software hard reset */ #define RCER_CRE 0x00000001 /* software hard reset */
#define RCER_RES ~(RCER_CRE) #define RCER_RES ~(RCER_CRE)
@ -505,8 +531,9 @@ typedef struct clk8349 {
#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ #define SPMR_CEVCOD 0x000000C0 /* CEVCOD */
#define SPMR_CEPDF 0x00000020 /* CEPDF */ #define SPMR_CEPDF 0x00000020 /* CEPDF */
#define SPMR_CEPMF 0x0000001F /* CEPMF */ #define SPMR_CEPMF 0x0000001F /* CEPMF */
#define SPMR_RES ~(SPMR_LBIUCM|SPMR_DDRCM|SPMR_SVCOD|SPMR_SPMF|SPMR_CKID \ #define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
|SPMR_COREPLL|SPMR_CEVCOD|SPMR_CEPDF|SPMR_CEPMF) | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
u32 occr; /* output clock control Register */ u32 occr; /* output clock control Register */
#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ #define OCCR_PCICOE0 0x80000000 /* PCICOE0 */
#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ #define OCCR_PCICOE1 0x40000000 /* PCICOE1 */
@ -526,10 +553,12 @@ typedef struct clk8349 {
#define OCCR_PCICD7 0x00010000 /* PCICD7 */ #define OCCR_PCICD7 0x00010000 /* PCICD7 */
#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ #define OCCR_PCI1CR 0x00000002 /* PCI1CR */
#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ #define OCCR_PCI2CR 0x00000001 /* PCI2CR */
#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2|OCCR_PCICOE3|OCCR_PCICOE4 \ #define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
|OCCR_PCICOE5|OCCR_PCICOE6|OCCR_PCICOE7|OCCR_PCICD0|OCCR_PCICD1 \ | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
|OCCR_PCICD2 |OCCR_PCICD3 |OCCR_PCICD4 |OCCR_PCICD5|OCCR_PCICD6 \ | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
|OCCR_PCICD7 |OCCR_PCI1CR |OCCR_PCI2CR ) | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \
| OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \
| OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR )
u32 sccr; /* system clock control Register */ u32 sccr; /* system clock control Register */
#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ #define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */
#define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_SHIFT 30
@ -542,8 +571,8 @@ typedef struct clk8349 {
#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ #define SCCR_USBDRCM 0x00300000 /* USBDRCM */
#define SCCR_USBDRCM_SHIFT 20 #define SCCR_USBDRCM_SHIFT 20
#define SCCR_PCICM 0x00010000 /* PCICM */ #define SCCR_PCICM 0x00010000 /* PCICM */
#define SCCR_RES ~( SCCR_TSEC1CM|SCCR_TSEC2CM|SCCR_ENCCM|SCCR_USBMPHCM \ #define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
|SCCR_USBDRCM|SCCR_PCICM) | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
u8 res0[0xF4]; u8 res0[0xF4];
} clk8349_t; } clk8349_t;
@ -554,7 +583,7 @@ typedef struct pmc8349 {
u32 pmccr; /* PMC Configuration Register */ u32 pmccr; /* PMC Configuration Register */
#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ #define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */
#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ #define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */
#define PMCCR_RES ~(PMCCR_SLPEN|PMCCR_DLPEN) #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
u32 pmcer; /* PMC Event Register */ u32 pmcer; /* PMC Event Register */
#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ #define PMCER_PMCI 0x00000001 /* PMC Interrupt */
#define PMCER_RES ~(PMCER_PMCI) #define PMCER_RES ~(PMCER_PMCI)
@ -701,7 +730,6 @@ typedef struct duart8349{
u8 udsr; /**< DMA status register */ u8 udsr; /**< DMA status register */
u8 res1[3]; u8 res1[3];
u8 res2[0xEC]; u8 res2[0xEC];
} duart8349_t; } duart8349_t;
/* /*

69
include/asm-ppc/immap_85xx.h
View file

@ -9,9 +9,9 @@
#ifndef __IMMAP_85xx__ #ifndef __IMMAP_85xx__
#define __IMMAP_85xx__ #define __IMMAP_85xx__
/*
/* Local-Access Registers and ECM Registers(0x0000-0x2000) */ * Local-Access Registers and ECM Registers(0x0000-0x2000)
*/
typedef struct ccsr_local_ecm { typedef struct ccsr_local_ecm {
uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
char res1[4]; char res1[4];
@ -65,9 +65,9 @@ typedef struct ccsr_local_ecm {
char res24[492]; char res24[492];
} ccsr_local_ecm_t; } ccsr_local_ecm_t;
/*
/* DDR memory controller registers(0x2000-0x3000) */ * DDR memory controller registers(0x2000-0x3000)
*/
typedef struct ccsr_ddr { typedef struct ccsr_ddr {
uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
char res1[4]; char res1[4];
@ -125,11 +125,9 @@ typedef struct ccsr_ddr {
char res12[240]; char res12[240];
} ccsr_ddr_t; } ccsr_ddr_t;
/*
* I2C Registers(0x3000-0x4000)
*/
/* I2C Registers(0x3000-0x4000) */
typedef struct ccsr_i2c { typedef struct ccsr_i2c {
u_char i2cadr; /* 0x3000 - I2C Address Register */ u_char i2cadr; /* 0x3000 - I2C Address Register */
#define MPC85xx_I2CADR_MASK 0xFE #define MPC85xx_I2CADR_MASK 0xFE
@ -246,10 +244,10 @@ typedef struct ccsr_lbc {
char res8[12072]; char res8[12072];
} ccsr_lbc_t; } ccsr_lbc_t;
/*
/* PCI Registers(0x8000-0x9000) */ * PCI Registers(0x8000-0x9000)
/* Omitting Reserved(0x9000-0x2_0000) */ * Omitting Reserved(0x9000-0x2_0000)
*/
typedef struct ccsr_pcix { typedef struct ccsr_pcix {
uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */ uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
@ -314,9 +312,9 @@ typedef struct ccsr_pcix {
char res11[94688]; char res11[94688];
} ccsr_pcix_t; } ccsr_pcix_t;
/*
/* L2 Cache Registers(0x2_0000-0x2_1000) */ * L2 Cache Registers(0x2_0000-0x2_1000)
*/
typedef struct ccsr_l2cache { typedef struct ccsr_l2cache {
uint l2ctl; /* 0x20000 - L2 configuration register 0 */ uint l2ctl; /* 0x20000 - L2 configuration register 0 */
char res1[12]; char res1[12];
@ -358,9 +356,9 @@ typedef struct ccsr_l2cache {
char res15[420]; char res15[420];
} ccsr_l2cache_t; } ccsr_l2cache_t;
/*
/* DMA Registers(0x2_1000-0x2_2000) */ * DMA Registers(0x2_1000-0x2_2000)
*/
typedef struct ccsr_dma { typedef struct ccsr_dma {
char res1[256]; char res1[256];
uint mr0; /* 0x21100 - DMA 0 Mode Register */ uint mr0; /* 0x21100 - DMA 0 Mode Register */
@ -439,7 +437,9 @@ typedef struct ccsr_dma {
char res22[11516]; char res22[11516];
} ccsr_dma_t; } ccsr_dma_t;
/* tsec1 tsec2: 24000-26000 */ /*
* tsec1 tsec2: 24000-26000
*/
typedef struct ccsr_tsec { typedef struct ccsr_tsec {
char res1[16]; char res1[16];
uint ievent; /* 0x24010 - Interrupt Event Register */ uint ievent; /* 0x24010 - Interrupt Event Register */
@ -726,8 +726,9 @@ typedef struct ccsr_tsec {
char res74[1024]; char res74[1024];
} ccsr_tsec_t; } ccsr_tsec_t;
/* PIC Registers(0x2_6000-0x4_0000-0x8_0000) */ /*
* PIC Registers(0x2_6000-0x4_0000-0x8_0000)
*/
typedef struct ccsr_pic { typedef struct ccsr_pic {
char res0[106496]; /* 0x26000-0x40000 */ char res0[106496]; /* 0x26000-0x40000 */
char res1[64]; char res1[64];
@ -1033,15 +1034,18 @@ typedef struct ccsr_pic {
char res150[130892]; char res150[130892];
} ccsr_pic_t; } ccsr_pic_t;
/* CPM Block(0x8_0000-0xc_0000) */ /*
* CPM Block(0x8_0000-0xc_0000)
*/
#ifndef CONFIG_CPM2 #ifndef CONFIG_CPM2
typedef struct ccsr_cpm { typedef struct ccsr_cpm {
char res[262144]; char res[262144];
} ccsr_cpm_t; } ccsr_cpm_t;
#else #else
/* 0x8000-0x8ffff:DPARM */ /*
* 0x8000-0x8ffff:DPARM
/* 0x9000-0x90bff: General SIU */ * 0x9000-0x90bff: General SIU
*/
typedef struct ccsr_cpm_siu { typedef struct ccsr_cpm_siu {
char res1[80]; char res1[80];
uint smaer; uint smaer;
@ -1332,7 +1336,6 @@ typedef struct ccsr_cpm {
char res1[16*1024]; char res1[16*1024];
u_char im_dpram2[16*1024]; u_char im_dpram2[16*1024];
char res2[16*1024]; char res2[16*1024];
ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
@ -1357,8 +1360,10 @@ typedef struct ccsr_cpm {
ccsr_cpm_iram_t im_cpm_iram; ccsr_cpm_iram_t im_cpm_iram;
} ccsr_cpm_t; } ccsr_cpm_t;
#endif #endif
/* RapidIO Registers(0xc_0000-0xe_0000) */
/*
* RapidIO Registers(0xc_0000-0xe_0000)
*/
typedef struct ccsr_rio { typedef struct ccsr_rio {
uint didcar; /* 0xc0000 - Device Identity Capability Register */ uint didcar; /* 0xc0000 - Device Identity Capability Register */
uint dicar; /* 0xc0004 - Device Information Capability Register */ uint dicar; /* 0xc0004 - Device Information Capability Register */
@ -1524,7 +1529,9 @@ typedef struct ccsr_rio {
char res58[60176]; char res58[60176];
} ccsr_rio_t; } ccsr_rio_t;
/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ /*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
typedef struct ccsr_gur { typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */

56
include/configs/MPC8349ADS.h
View file

@ -73,8 +73,6 @@
#define CFG_MEMTEST_START 0x00000000 /* memtest region */ #define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x00100000 #define CFG_MEMTEST_END 0x00100000
/* /*
* DDR Setup * DDR Setup
*/ */
@ -89,7 +87,6 @@
* Determine DDR configuration from I2C interface. * Determine DDR configuration from I2C interface.
*/ */
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#else #else
/* /*
* Manually set up DDR parameters * Manually set up DDR parameters
@ -103,7 +100,6 @@
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
#endif #endif
/* /*
* SDRAM on the Local Bus * SDRAM on the Local Bus
*/ */
@ -126,7 +122,6 @@
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */ #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ #define CFG_MAX_FLASH_SECT 64 /* sectors per device */
@ -137,7 +132,6 @@
#define CFG_MID_FLASH_JUMP 0x7F000000 #define CFG_MID_FLASH_JUMP 0x7F000000
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT #define CFG_RAMBOOT
#else #else
@ -153,7 +147,6 @@
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
#define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */ #define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */
#define CONFIG_L1_INIT_RAM #define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
@ -198,12 +191,9 @@
*/ */
#define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/ #define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/
#define CFG_LBLAWBAR2_PRELIM 0xF0000000 #define CFG_LBLAWBAR2_PRELIM 0xF0000000
#define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/ #define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/
/* /*
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
* *
@ -264,7 +254,6 @@
| CFG_LBC_LSDMR_CL3 \ | CFG_LBC_LSDMR_CL3 \
) )
/* /*
* SDRAM Controller configuration sequence. * SDRAM Controller configuration sequence.
*/ */
@ -278,13 +267,8 @@
| CFG_LBC_LSDMR_OP_MRW) | CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_NORMAL) | CFG_LBC_LSDMR_OP_NORMAL)
#endif #endif
/* /*
* Serial Port * Serial Port
*/ */
@ -322,7 +306,6 @@
#define CFG_TSEC2_OFFSET 0x25000 #define CFG_TSEC2_OFFSET 0x25000
#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
/* IO Configuration */ /* IO Configuration */
#define CFG_IO_CONF (\ #define CFG_IO_CONF (\
IO_CONF_UART |\ IO_CONF_UART |\
@ -347,7 +330,6 @@
#define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#define CFG_PCI2_MEM_BASE 0xA0000000 #define CFG_PCI2_MEM_BASE 0xA0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
@ -356,10 +338,7 @@
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
//#define PCI_64BIT
#define PCI_ALL_PCI1 #define PCI_ALL_PCI1
//#define PCI_ONE_PCI1
//#define PCI_TWO_PCI1
#if defined(PCI_64BIT) #if defined(PCI_64BIT)
#undef PCI_ALL_PCI1 #undef PCI_ALL_PCI1
#undef PCI_TWO_PCI1 #undef PCI_TWO_PCI1
@ -383,9 +362,7 @@
#endif /* CONFIG_PCI */ #endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET) #if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI #ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1 #define CONFIG_NET_MULTI 1
#endif #endif
@ -405,7 +382,6 @@
#endif /* CONFIG_TSEC_ENET */ #endif /* CONFIG_TSEC_ENET */
/* /*
* Environment * Environment
*/ */
@ -425,35 +401,35 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT) #if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \ | CFG_CMD_PING \
| CFG_CMD_PCI \ | CFG_CMD_PCI \
| CFG_CMD_I2C) \ | CFG_CMD_I2C) \
& \ & \
~(CFG_CMD_ENV \ ~(CFG_CMD_ENV \
| CFG_CMD_LOADS)) | CFG_CMD_LOADS))
#else #else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \ | CFG_CMD_PING \
| CFG_CMD_I2C) \ | CFG_CMD_I2C) \
& \ & \
~(CFG_CMD_ENV \ ~(CFG_CMD_ENV \
| CFG_CMD_LOADS)) | CFG_CMD_LOADS))
#endif #endif
#else #else
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PCI \ | CFG_CMD_PCI \
| CFG_CMD_PING \ | CFG_CMD_PING \
| CFG_CMD_I2C) | CFG_CMD_I2C)
#else #else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PING \ | CFG_CMD_PING \
| CFG_CMD_I2C \ | CFG_CMD_I2C \
| CFG_CMD_MII \ | CFG_CMD_MII \
) )
#endif #endif
#endif #endif
#include <cmd_confdefs.h> #include <cmd_confdefs.h>
@ -529,7 +505,6 @@
HRCWH_TSEC2M_IN_GMII ) HRCWH_TSEC2M_IN_GMII )
#endif #endif
#define CFG_HID0_INIT 0x000000000 #define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID0_FINAL CFG_HID0_INIT
@ -554,7 +529,6 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif #endif
/* /*
* Environment Configuration * Environment Configuration
*/ */
@ -565,13 +539,13 @@
#define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01 #define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01
#endif #endif
#define CONFIG_IPADDR 10.193.20.150 #define CONFIG_IPADDR 192.168.1.253
#define CONFIG_HOSTNAME unknown #define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /tftpboot/10.193.20.150 #define CONFIG_ROOTPATH /nfsroot
#define CONFIG_BOOTFILE /tftpboot/vmlinux.150 #define CONFIG_BOOTFILE your.uImage
#define CONFIG_SERVERIP 10.193.20.58 #define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_NETMASK 255.255.255.0
@ -587,7 +561,7 @@
"netdev=eth0\0" \ "netdev=eth0\0" \
"consoledev=ttyS0\0" \ "consoledev=ttyS0\0" \
"ramdiskaddr=400000\0" \ "ramdiskaddr=400000\0" \
"ramdiskfile=ramfs.83xx\0" \ "ramdiskfile=ramfs.83xx\0"
#define CONFIG_NFSBOOTCOMMAND \ #define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \ "setenv bootargs root=/dev/nfs rw " \

67
include/configs/MPC8540EVAL.h
View file

@ -51,8 +51,11 @@
/* sysclk for MPC8540EVAL */ /* sysclk for MPC8540EVAL */
#if defined(CONFIG_SYSCLK_66M) #if defined(CONFIG_SYSCLK_66M)
#define CONFIG_SYS_CLK_FREQ 66000000 /* the oscillator on board is 66Mhz */ /*
/* can also get 66M clock from external PCI */ * the oscillator on board is 66Mhz
* can also get 66M clock from external PCI
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#else #else
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
#endif #endif
@ -194,11 +197,11 @@
#undef CONFIG_EEPRO100 #undef CONFIG_EEPRO100
#define CONFIG_TULIP #define CONFIG_TULIP
#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_PNP /* do pci plug-and-play */
#if !defined(CONFIG_PCI_PNP) #if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
#endif #endif
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CFG_PCI_SUBSYS_DEVICEID 0x0008 #define CFG_PCI_SUBSYS_DEVICEID 0x0008
@ -221,23 +224,23 @@
#define CONFIG_ETHPRIME "TSEC0" #define CONFIG_ETHPRIME "TSEC0"
#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ #define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
#define INTEL_LXT971_PHY 1 /* on EVAL board. It is Davicom 9161 on ADS. */ #define INTEL_LXT971_PHY 1
#endif #endif
#undef DEBUG #undef DEBUG
/* Environment */ /* Environment */
#ifndef CFG_RAMBOOT #ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH) #if defined(CONFIG_RAM_AS_FLASH)
#define CFG_ENV_IS_NOWHERE #define CFG_ENV_IS_NOWHERE
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
#define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SIZE 0x2000
#else #else
#define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#endif #endif
#define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SIZE 0x2000
#else #else
/* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */ /* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
@ -245,7 +248,6 @@
#define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SIZE 0x2000
#endif #endif
/*#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.1.10:/tftproot/192.168.1.11 ip=192.168.1.11:192.168.1.10:192.168.1.0:255.255.255.0:mpc8540ads-003:eth0:off console=ttyS0,115200"*/
#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" #define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
@ -254,21 +256,24 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_PCI | CFG_CMD_I2C ) & \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
| CFG_CMD_PCI | CFG_CMD_I2C ) & \
~(CFG_CMD_ENV | CFG_CMD_LOADS )) ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) & \
~(CFG_CMD_ENV | \
CFG_CMD_LOADS ))
#endif
#else #else
#if defined(CONFIG_PCI) #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_PING | CFG_CMD_I2C ) | CFG_CMD_I2C ) & \
#else ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
#endif
#endif #endif
#else
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
| CFG_CMD_PING | CFG_CMD_I2C )
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
#endif
#endif
#include <cmd_confdefs.h> #include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_WATCHDOG /* watchdog disabled */

1
include/mpc83xx.h
View file

@ -285,5 +285,4 @@
#define LCRR_CLKDIV_8 0x00000008 #define LCRR_CLKDIV_8 0x00000008
#define LCRR_CLKDIV_SHIFT 0 #define LCRR_CLKDIV_SHIFT 0
#endif /* __MPC83XX_H__ */ #endif /* __MPC83XX_H__ */

2
include/spd.h
View file

@ -103,6 +103,4 @@ typedef struct spd_eeprom_s {
#define SPD_MEMTYPE_DDR (0x07) #define SPD_MEMTYPE_DDR (0x07)
#define SPD_MEMTYPE_DDR2 (0x08) #define SPD_MEMTYPE_DDR2 (0x08)
#endif /* _SPD_H_ */ #endif /* _SPD_H_ */