mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 13:41:31 +00:00
Merge branch '2021-08-31-kconfig-migrations-part2' into next
- Further CONFIG to Kconfig migrations
- Some DDR related symbols
- CONFIG_SYS_LOAD_ADDR moved, loadaddr always set in environment now.
- Finish MX7D, convert IMX_CONFIG
- Some RAMBOOT related options
- L1 cache size converted and named consistently for all arches. A
further follow-up to rename things for even better clarity is welcome.
- CONFIG_SKIP_LOWLEVEL_INIT, CONFIG_SYS_MALLOC_LEN
This commit is contained in:
Tom Rini
commit
df6cf3d809
1568 changed files with 2880 additions and 3018 deletions
KconfigREADME
api
arch
Kconfig
arc
arm
Kconfigconfig.mk
cpu
arm1136
arm720t
arm920t
arm926ejs
arm946es
armv7
armv8
pxa
sa1100
include/asm/arch-am33xx
mach-at91
mach-imx
mach-mediatek
mach-mvebu
mach-omap2
mach-orion5x
mach-rmobile
mach-rockchip
mach-stm32mp
mach-sunxi
mach-tegra
mips
nds32
powerpc
cpu
include/asm
riscv
sandbox/include/asm
x86
xtensa
board
advantech/imx8qm_rom7720_a1
aristainetos
armadeus/opos6uldev
beacon
beckhoff/mx53cx9020
bosch/guardian
boundary/nitrogen6x
compulab/imx8mm-cl-iot-gate
congatec
ea/mx7ulp_com
eets/pdu001
engicam/imx8mm
freescale
27
Kconfig
27
Kconfig
|
|
@ -83,7 +83,6 @@ config CC_OPTIMIZE_FOR_SIZE
|
|||
|
||||
config OPTIMIZE_INLINING
|
||||
bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
|
||||
default n
|
||||
help
|
||||
This option determines if U-Boot forces gcc to inline the functions
|
||||
developers have marked 'inline'. Doing so takes away freedom from gcc to
|
||||
|
|
@ -93,7 +92,6 @@ config OPTIMIZE_INLINING
|
|||
config SPL_OPTIMIZE_INLINING
|
||||
bool "Allow compiler to uninline functions marked 'inline' in SPL"
|
||||
depends on SPL
|
||||
default n
|
||||
help
|
||||
This option determines if U-Boot forces gcc to inline the functions
|
||||
developers have marked 'inline'. Doing so takes away freedom from gcc to
|
||||
|
|
@ -106,7 +104,6 @@ config ARCH_SUPPORTS_LTO
|
|||
config LTO
|
||||
bool "Enable Link Time Optimizations"
|
||||
depends on ARCH_SUPPORTS_LTO
|
||||
default n
|
||||
help
|
||||
This option enables Link Time Optimization (LTO), a mechanism which
|
||||
allows the compiler to optimize between different compilation units.
|
||||
|
|
@ -127,7 +124,6 @@ config LTO
|
|||
config TPL_OPTIMIZE_INLINING
|
||||
bool "Allow compiler to uninline functions marked 'inline' in TPL"
|
||||
depends on TPL
|
||||
default n
|
||||
help
|
||||
This option determines if U-Boot forces gcc to inline the functions
|
||||
developers have marked 'inline'. Doing so takes away freedom from gcc to
|
||||
|
|
@ -249,8 +245,11 @@ config SYS_MALLOC_F_LEN
|
|||
|
||||
config SYS_MALLOC_LEN
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hex "Define memory for Dynamic allocation"
|
||||
depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
|
||||
default 0x2000000 if ARCH_ROCKCHIP
|
||||
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
|
||||
default 0x4020000 if ARCH_SUNXI && !MACH_SUN8I_V3S
|
||||
default 0x200000 if ARCH_BMIPS || X86
|
||||
default 0x220000 if ARCH_SUNXI && MACH_SUN8I_V3S
|
||||
default 0x400000
|
||||
help
|
||||
This defines memory to be allocated for Dynamic allocation
|
||||
TODO: Use for other architectures
|
||||
|
|
@ -307,7 +306,6 @@ if EXPERT
|
|||
|
||||
config SYS_MALLOC_DEFAULT_TO_INIT
|
||||
bool "Default malloc to init while reserving the memory for it"
|
||||
default n
|
||||
help
|
||||
It may happen that one needs to move the dynamic allocation
|
||||
from one to another memory range, eg. when moving the malloc
|
||||
|
|
@ -389,6 +387,20 @@ config SYS_LDSCRIPT
|
|||
Path within the source tree to the linker script to use for the
|
||||
main U-Boot binary.
|
||||
|
||||
config SYS_LOAD_ADDR
|
||||
hex "Address in memory to use by default"
|
||||
default 0x01000000 if ARCH_SOCFPGA
|
||||
default 0x02000000 if PPC || X86
|
||||
default 0x22000000 if MACH_SUN9I
|
||||
default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
|
||||
default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
|
||||
default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
|
||||
default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL || MX6SX || MX6UL || MX6ULL)
|
||||
default 0x80800000 if ARCH_MX7
|
||||
default 0x90000000 if FSL_LSCH2 || FSL_LSCH3
|
||||
help
|
||||
Address in memory to use as the default safe load address.
|
||||
|
||||
config ERR_PTR_OFFSET
|
||||
hex
|
||||
default 0x0
|
||||
|
|
@ -423,7 +435,6 @@ config SYS_HAS_SRAM
|
|||
default y if TARGET_PIC32MZDASK
|
||||
default y if TARGET_DEVKIT8000
|
||||
default y if TARGET_TRICORDER
|
||||
default n
|
||||
help
|
||||
Enable this to allow support for the on board SRAM.
|
||||
SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
|
||||
|
|
|
|||
29
README
29
README
|
|
@ -465,10 +465,6 @@ The following options need to be configured:
|
|||
Board config to use DDR3L. It can be enabled for SoCs with
|
||||
DDR3L controllers.
|
||||
|
||||
CONFIG_SYS_FSL_DDR4
|
||||
Board config to use DDR4. It can be enabled for SoCs with
|
||||
DDR4 controllers.
|
||||
|
||||
CONFIG_SYS_FSL_IFC_BE
|
||||
Defines the IFC controller register space as Big Endian
|
||||
|
||||
|
|
@ -481,15 +477,6 @@ The following options need to be configured:
|
|||
CONFIG_SYS_FSL_LBC_CLK_DIV
|
||||
Defines divider of platform clock(clock input to eLBC controller).
|
||||
|
||||
CONFIG_SYS_FSL_PBL_PBI
|
||||
It enables addition of RCW (Power on reset configuration) in built image.
|
||||
Please refer doc/README.pblimage for more details
|
||||
|
||||
CONFIG_SYS_FSL_PBL_RCW
|
||||
It adds PBI(pre-boot instructions) commands in u-boot build image.
|
||||
PBI commands can be used to configure SoC before it starts the execution.
|
||||
Please refer doc/README.pblimage for more details
|
||||
|
||||
CONFIG_SYS_FSL_DDR_BE
|
||||
Defines the DDR controller register space as Big Endian
|
||||
|
||||
|
|
@ -2754,22 +2741,6 @@ Low Level (hardware related) configuration options:
|
|||
This only takes effect if the memory commands are activated
|
||||
globally (CONFIG_CMD_MEMORY).
|
||||
|
||||
- CONFIG_SKIP_LOWLEVEL_INIT
|
||||
[ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain
|
||||
low level initializations (like setting up the memory
|
||||
controller) are omitted and/or U-Boot does not
|
||||
relocate itself into RAM.
|
||||
|
||||
Normally this variable MUST NOT be defined. The only
|
||||
exception is when U-Boot is loaded (to RAM) by some
|
||||
other boot loader or by a debugger which performs
|
||||
these initializations itself.
|
||||
|
||||
- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
||||
[ARM926EJ-S only] This allows just the call to lowlevel_init()
|
||||
to be skipped. The normal CP15 init (such as enabling the
|
||||
instruction cache) is still performed.
|
||||
|
||||
- CONFIG_SPL_BUILD
|
||||
Set when the currently-running compilation is for an artifact
|
||||
that will end up in the SPL (as opposed to the TPL or U-Boot
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ menu "API"
|
|||
|
||||
config API
|
||||
bool "Enable U-Boot API"
|
||||
default n
|
||||
help
|
||||
This option enables the U-Boot API. See api/README for more information.
|
||||
|
||||
|
|
|
|||
82
arch/Kconfig
82
arch/Kconfig
|
|
@ -7,6 +7,27 @@ config HAVE_ARCH_IOREMAP
|
|||
config NEEDS_MANUAL_RELOC
|
||||
bool
|
||||
|
||||
config SYS_CACHE_SHIFT_4
|
||||
bool
|
||||
|
||||
config SYS_CACHE_SHIFT_5
|
||||
bool
|
||||
|
||||
config SYS_CACHE_SHIFT_6
|
||||
bool
|
||||
|
||||
config SYS_CACHE_SHIFT_7
|
||||
bool
|
||||
|
||||
config SYS_CACHELINE_SIZE
|
||||
int
|
||||
default 128 if SYS_CACHE_SHIFT_7
|
||||
default 64 if SYS_CACHE_SHIFT_6
|
||||
default 32 if SYS_CACHE_SHIFT_5
|
||||
default 16 if SYS_CACHE_SHIFT_4
|
||||
# Fall-back for MIPS
|
||||
default 32 if MIPS
|
||||
|
||||
config LINKER_LIST_ALIGN
|
||||
int
|
||||
default 32 if SANDBOX
|
||||
|
|
@ -29,6 +50,7 @@ config ARC
|
|||
select DM
|
||||
select HAVE_PRIVATE_LIBGCC
|
||||
select SUPPORT_OF_CONTROL
|
||||
select SYS_CACHE_SHIFT_7
|
||||
select TIMER
|
||||
|
||||
config ARM
|
||||
|
|
@ -44,6 +66,7 @@ config M68K
|
|||
select NEEDS_MANUAL_RELOC
|
||||
select SYS_BOOT_GET_CMDLINE
|
||||
select SYS_BOOT_GET_KBD
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select SUPPORT_OF_CONTROL
|
||||
|
||||
config MICROBLAZE
|
||||
|
|
@ -122,6 +145,7 @@ config SANDBOX
|
|||
select SPI
|
||||
select SUPPORT_OF_CONTROL
|
||||
select SYSRESET_CMD_POWEROFF
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select IRQ
|
||||
select SUPPORT_EXTENSION_SCAN
|
||||
imply BITREVERSE
|
||||
|
|
@ -188,6 +212,7 @@ config X86
|
|||
select OF_CONTROL
|
||||
select PCI
|
||||
select SUPPORT_OF_CONTROL
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select TIMER
|
||||
select USE_PRIVATE_LIBGCC
|
||||
select X86_TSC_TIMER
|
||||
|
|
@ -326,6 +351,63 @@ config SYS_DISABLE_DCACHE_OPS
|
|||
Note that, its up to the individual architectures to implement
|
||||
this functionality.
|
||||
|
||||
config SKIP_LOWLEVEL_INIT
|
||||
bool "Skip the calls to certain low level initialization functions"
|
||||
depends on ARM || NDS32 || MIPS || RISCV
|
||||
help
|
||||
If enabled, then certain low level initializations (like setting up
|
||||
the memory controller) are omitted and/or U-Boot does not relocate
|
||||
itself into RAM.
|
||||
Normally this variable MUST NOT be defined. The only exception is
|
||||
when U-Boot is loaded (to RAM) by some other boot loader or by a
|
||||
debugger which performs these initializations itself.
|
||||
|
||||
config SPL_SKIP_LOWLEVEL_INIT
|
||||
bool "Skip the calls to certain low level initialization functions"
|
||||
depends on SPL && (ARM || NDS32 || MIPS || RISCV)
|
||||
help
|
||||
If enabled, then certain low level initializations (like setting up
|
||||
the memory controller) are omitted and/or U-Boot does not relocate
|
||||
itself into RAM.
|
||||
Normally this variable MUST NOT be defined. The only exception is
|
||||
when U-Boot is loaded (to RAM) by some other boot loader or by a
|
||||
debugger which performs these initializations itself.
|
||||
|
||||
config TPL_SKIP_LOWLEVEL_INIT
|
||||
bool "Skip the calls to certain low level initialization functions"
|
||||
depends on SPL && ARM
|
||||
help
|
||||
If enabled, then certain low level initializations (like setting up
|
||||
the memory controller) are omitted and/or U-Boot does not relocate
|
||||
itself into RAM.
|
||||
Normally this variable MUST NOT be defined. The only exception is
|
||||
when U-Boot is loaded (to RAM) by some other boot loader or by a
|
||||
debugger which performs these initializations itself.
|
||||
|
||||
config SKIP_LOWLEVEL_INIT_ONLY
|
||||
bool "Skip the call to lowlevel_init during early boot ONLY"
|
||||
depends on ARM
|
||||
help
|
||||
This allows just the call to lowlevel_init() to be skipped. The
|
||||
normal CP15 init (such as enabling the instruction cache) is still
|
||||
performed.
|
||||
|
||||
config SPL_SKIP_LOWLEVEL_INIT_ONLY
|
||||
bool "Skip the call to lowlevel_init during early boot ONLY"
|
||||
depends on SPL && ARM
|
||||
help
|
||||
This allows just the call to lowlevel_init() to be skipped. The
|
||||
normal CP15 init (such as enabling the instruction cache) is still
|
||||
performed.
|
||||
|
||||
config TPL_SKIP_LOWLEVEL_INIT_ONLY
|
||||
bool "Skip the call to lowlevel_init during early boot ONLY"
|
||||
depends on TPL && ARM
|
||||
help
|
||||
This allows just the call to lowlevel_init() to be skipped. The
|
||||
normal CP15 init (such as enabling the instruction cache) is still
|
||||
performed.
|
||||
|
||||
source "arch/arc/Kconfig"
|
||||
source "arch/arm/Kconfig"
|
||||
source "arch/m68k/Kconfig"
|
||||
|
|
|
|||
|
|
@ -104,13 +104,11 @@ endchoice
|
|||
|
||||
config CPU_BIG_ENDIAN
|
||||
bool "Enable Big Endian Mode"
|
||||
default n
|
||||
help
|
||||
Build kernel for Big Endian Mode of ARC CPU
|
||||
|
||||
config SYS_ICACHE_OFF
|
||||
bool "Do not enable icache"
|
||||
default n
|
||||
help
|
||||
Do not enable instruction cache in U-Boot.
|
||||
|
||||
|
|
@ -123,7 +121,6 @@ config SPL_SYS_ICACHE_OFF
|
|||
|
||||
config SYS_DCACHE_OFF
|
||||
bool "Do not enable dcache"
|
||||
default n
|
||||
help
|
||||
Do not enable data cache in U-Boot.
|
||||
|
||||
|
|
@ -136,14 +133,12 @@ config SPL_SYS_DCACHE_OFF
|
|||
|
||||
menuconfig ARC_DBG
|
||||
bool "ARC debugging"
|
||||
default n
|
||||
|
||||
if ARC_DBG
|
||||
|
||||
config ARC_DBG_IOC_ENABLE
|
||||
bool "Enable IO coherency unit"
|
||||
depends on CPU_ARCHS38
|
||||
default n
|
||||
help
|
||||
Enable IO coherency unit to debug problems with caches and
|
||||
DMA peripherals.
|
||||
|
|
|
|||
|
|
@ -16,9 +16,6 @@
|
|||
*/
|
||||
#define ARCH_DMA_MINALIGN 128
|
||||
|
||||
/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
|
||||
|
||||
#if defined(ARC_MMU_ABSENT)
|
||||
#define CONFIG_ARC_MMU_VER 0
|
||||
#elif defined(CONFIG_ARC_MMU_V2)
|
||||
|
|
|
|||
|
|
@ -110,7 +110,6 @@ config THUMB2_KERNEL
|
|||
|
||||
config SYS_ICACHE_OFF
|
||||
bool "Do not enable icache"
|
||||
default n
|
||||
help
|
||||
Do not enable instruction cache in U-Boot.
|
||||
|
||||
|
|
@ -123,7 +122,6 @@ config SPL_SYS_ICACHE_OFF
|
|||
|
||||
config SYS_DCACHE_OFF
|
||||
bool "Do not enable dcache"
|
||||
default n
|
||||
help
|
||||
Do not enable data cache in U-Boot.
|
||||
|
||||
|
|
@ -338,21 +336,6 @@ config SYS_ARM_ARCH
|
|||
default 4 if CPU_SA1100
|
||||
default 8 if ARM64
|
||||
|
||||
config SYS_CACHE_SHIFT_5
|
||||
bool
|
||||
|
||||
config SYS_CACHE_SHIFT_6
|
||||
bool
|
||||
|
||||
config SYS_CACHE_SHIFT_7
|
||||
bool
|
||||
|
||||
config SYS_CACHELINE_SIZE
|
||||
int
|
||||
default 128 if SYS_CACHE_SHIFT_7
|
||||
default 64 if SYS_CACHE_SHIFT_6
|
||||
default 32 if SYS_CACHE_SHIFT_5
|
||||
|
||||
choice
|
||||
prompt "Select the ARM data write cache policy"
|
||||
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
|
||||
|
|
@ -458,7 +441,6 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
|
|||
|
||||
config ARM_CORTEX_CPU_IS_UP
|
||||
bool
|
||||
default n
|
||||
|
||||
config USE_ARCH_MEMCPY
|
||||
bool "Use an assembly optimized implementation of memcpy"
|
||||
|
|
@ -729,6 +711,7 @@ config ARCH_KEYSTONE
|
|||
bool "TI Keystone"
|
||||
select CMD_POWEROFF
|
||||
select CPU_V7A
|
||||
select DDR_SPD
|
||||
select GPIO_EXTRA_HEADER
|
||||
select SUPPORT_SPL
|
||||
select SYS_ARCH_TIMER
|
||||
|
|
@ -793,6 +776,7 @@ config ARCH_IMX8
|
|||
select ARM64
|
||||
select DM
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
select OF_CONTROL
|
||||
select ENABLE_ARM_SOC_BOOT0_HOOK
|
||||
|
||||
|
|
@ -800,6 +784,7 @@ config ARCH_IMX8M
|
|||
bool "NXP i.MX8M platform"
|
||||
select ARM64
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
select SYS_FSL_HAS_SEC if IMX_HAB
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_SEC_LE
|
||||
|
|
@ -812,6 +797,7 @@ config ARCH_IMX8ULP
|
|||
bool "NXP i.MX8ULP platform"
|
||||
select ARM64
|
||||
select DM
|
||||
select MACH_IMX
|
||||
select OF_CONTROL
|
||||
select SUPPORT_SPL
|
||||
select GPIO_EXTRA_HEADER
|
||||
|
|
@ -823,6 +809,7 @@ config ARCH_IMXRT
|
|||
select DM
|
||||
select DM_SERIAL
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
select SUPPORT_SPL
|
||||
imply CMD_DM
|
||||
|
||||
|
|
@ -830,6 +817,7 @@ config ARCH_MX23
|
|||
bool "NXP i.MX23 family"
|
||||
select CPU_ARM926EJS
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
select PL011_SERIAL
|
||||
select SUPPORT_SPL
|
||||
|
||||
|
|
@ -837,6 +825,7 @@ config ARCH_MX25
|
|||
bool "NXP MX25"
|
||||
select CPU_ARM926EJS
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
imply MXC_GPIO
|
||||
|
||||
config ARCH_MX28
|
||||
|
|
@ -844,17 +833,20 @@ config ARCH_MX28
|
|||
select CPU_ARM926EJS
|
||||
select GPIO_EXTRA_HEADER
|
||||
select PL011_SERIAL
|
||||
select MACH_IMX
|
||||
select SUPPORT_SPL
|
||||
|
||||
config ARCH_MX31
|
||||
bool "NXP i.MX31 family"
|
||||
select CPU_ARM1136
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
|
||||
config ARCH_MX7ULP
|
||||
bool "NXP MX7ULP"
|
||||
select CPU_V7A
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
select SYS_FSL_HAS_SEC if IMX_HAB
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_SEC_LE
|
||||
|
|
@ -867,6 +859,7 @@ config ARCH_MX7
|
|||
select ARCH_MISC_INIT
|
||||
select CPU_V7A
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
select SYS_FSL_HAS_SEC if IMX_HAB
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_SEC_LE
|
||||
|
|
@ -878,6 +871,7 @@ config ARCH_MX6
|
|||
bool "Freescale MX6"
|
||||
select CPU_V7A
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_COMPAT_4
|
||||
select SYS_FSL_SEC_LE
|
||||
|
|
@ -894,6 +888,7 @@ config ARCH_MX5
|
|||
select BOARD_EARLY_INIT_F
|
||||
select CPU_V7A
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
imply MXC_GPIO
|
||||
|
||||
config ARCH_NEXELL
|
||||
|
|
@ -1081,6 +1076,7 @@ config ARCH_VF610
|
|||
bool "Freescale Vybrid"
|
||||
select CPU_V7A
|
||||
select GPIO_EXTRA_HEADER
|
||||
select MACH_IMX
|
||||
select SYS_FSL_ERRATUM_ESDHC111
|
||||
imply CMD_MTDPARTS
|
||||
imply MTD_RAW_NAND
|
||||
|
|
@ -1908,7 +1904,6 @@ config ARCH_SUPPORT_TFABOOT
|
|||
config TFABOOT
|
||||
bool "Support for booting from TF-A"
|
||||
depends on ARCH_SUPPORT_TFABOOT
|
||||
default n
|
||||
help
|
||||
Some platforms support the setup of secure registers (for instance
|
||||
for CPU errata handling) or provide secure services like PSCI.
|
||||
|
|
|
|||
|
|
@ -158,7 +158,8 @@ ifdef CONFIG_EFI_LOADER
|
|||
OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_IMX_CONFIG),)
|
||||
ifdef CONFIG_MACH_IMX
|
||||
ifneq ($(CONFIG_IMX_CONFIG),"")
|
||||
ifdef CONFIG_SPL
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
INPUTS-y += SPL
|
||||
|
|
@ -174,6 +175,7 @@ ifneq ($(CONFIG_VF610),)
|
|||
INPUTS-y += u-boot.vyb
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
EFI_LDS := elf_arm_efi.lds
|
||||
EFI_CRT0 := crt0_arm_efi.o
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ reset:
|
|||
msr cpsr,r0
|
||||
|
||||
/* the mask ROM code should have PLL and others stable */
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
|
|
@ -62,7 +62,7 @@ c_runtime_cpu_setup:
|
|||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
cpu_init_crit:
|
||||
/*
|
||||
* flush v4 I/D caches
|
||||
|
|
@ -81,7 +81,7 @@ cpu_init_crit:
|
|||
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
/*
|
||||
* Jump to board specific initialization... The Mask ROM will have already initialized
|
||||
* basic memory. Go here to bump up clock rate and handle wake up conditions.
|
||||
|
|
@ -91,4 +91,4 @@ cpu_init_crit:
|
|||
mov lr, ip /* restore link */
|
||||
#endif
|
||||
mov pc, lr /* back to my caller */
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -37,8 +37,8 @@ reset:
|
|||
* we do sys-critical inits only at reboot,
|
||||
* not when booting from ram!
|
||||
*/
|
||||
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
||||
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
|
||||
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
|
|
@ -62,8 +62,8 @@ c_runtime_cpu_setup:
|
|||
*************************************************************************
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
||||
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
|
||||
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
cpu_init_crit:
|
||||
|
||||
mov ip, lr
|
||||
|
|
@ -76,4 +76,4 @@ cpu_init_crit:
|
|||
mov lr, ip
|
||||
|
||||
mov pc, lr
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ copyex:
|
|||
* we do sys-critical inits only at reboot,
|
||||
* not when booting from ram!
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
|
|
@ -78,7 +78,7 @@ c_runtime_cpu_setup:
|
|||
*/
|
||||
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
cpu_init_crit:
|
||||
/*
|
||||
* flush v4 I/D caches
|
||||
|
|
@ -97,7 +97,7 @@ cpu_init_crit:
|
|||
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
/*
|
||||
* before relocating, we have to setup RAM timing
|
||||
* because memory timing is board-dependend, you will
|
||||
|
|
@ -109,4 +109,4 @@ cpu_init_crit:
|
|||
mov lr, ip
|
||||
#endif
|
||||
mov pc, lr
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ reset:
|
|||
* we do sys-critical inits only at reboot,
|
||||
* not when booting from ram!
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
|
|
@ -69,7 +69,7 @@ c_runtime_cpu_setup:
|
|||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
cpu_init_crit:
|
||||
/*
|
||||
* flush D cache before disabling it
|
||||
|
|
@ -100,7 +100,7 @@ flush_dcache:
|
|||
#endif
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
/*
|
||||
* Go setup Memory and board specific bits prior to relocation.
|
||||
*/
|
||||
|
|
@ -109,4 +109,4 @@ flush_dcache:
|
|||
mov lr, r4 /* restore link */
|
||||
#endif
|
||||
mov pc, lr /* back to my caller */
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ reset:
|
|||
* we do sys-critical inits only at reboot,
|
||||
* not when booting from ram!
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
|
|
@ -70,7 +70,7 @@ c_runtime_cpu_setup:
|
|||
*/
|
||||
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
cpu_init_crit:
|
||||
/*
|
||||
* flush v4 I/D caches
|
||||
|
|
@ -89,7 +89,7 @@ cpu_init_crit:
|
|||
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
/*
|
||||
* Go setup Memory and board specific bits prior to relocation.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o
|
|||
obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
|
||||
ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y)
|
||||
obj-y += lowlevel_init.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -42,8 +42,8 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
|
||||
|
||||
sys_info->freq_systembus = sysclk;
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
|
||||
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
|
||||
sys_info->freq_ddrbus = get_board_ddr_clk();
|
||||
#else
|
||||
sys_info->freq_ddrbus = sysclk;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -80,11 +80,11 @@ switch_to_hypervisor_ret:
|
|||
#endif
|
||||
|
||||
/* the mask ROM code should have PLL and others stable */
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
#ifdef CONFIG_CPU_V7A
|
||||
bl cpu_init_cp15
|
||||
#endif
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -320,8 +320,8 @@ skip_errata_801819:
|
|||
mov pc, r5 @ back to my caller
|
||||
ENDPROC(cpu_init_cp15)
|
||||
|
||||
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
||||
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
|
||||
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
/*************************************************************************
|
||||
*
|
||||
* CPU_init_critical registers
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@ if ARM64
|
|||
config ARMV8_SPL_EXCEPTION_VECTORS
|
||||
bool "Install crash dump exception vectors"
|
||||
depends on SPL
|
||||
default n
|
||||
help
|
||||
The default exception vector table is only used for the crash
|
||||
dump, but still takes quite a lot of space in the image size.
|
||||
|
|
@ -128,7 +127,6 @@ config PSCI_RESET
|
|||
|
||||
config ARMV8_PSCI
|
||||
bool "Enable PSCI support" if EXPERT
|
||||
default n
|
||||
help
|
||||
PSCI is Power State Coordination Interface defined by ARM.
|
||||
The PSCI in U-boot provides a general framework and each platform
|
||||
|
|
@ -156,7 +154,6 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
|
|||
|
||||
config ARMV8_EA_EL3_FIRST
|
||||
bool "External aborts and SError interrupt exception are taken in EL3"
|
||||
default n
|
||||
help
|
||||
Exception handling at all exception levels for External Abort and
|
||||
SError interrupt exception are taken in EL3.
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ config ARCH_LS1012A
|
|||
select FSL_LAYERSCAPE
|
||||
select FSL_LSCH2
|
||||
select GICV2
|
||||
select SKIP_LOWLEVEL_INIT
|
||||
select SYS_FSL_SRDS_1
|
||||
select SYS_HAS_SERDES
|
||||
select SYS_FSL_DDR_BE
|
||||
|
|
@ -62,6 +63,7 @@ config ARCH_LS1043A
|
|||
select FSL_LSCH2
|
||||
select GICV2
|
||||
select HAS_FSL_XHCI_USB if USB_HOST
|
||||
select SKIP_LOWLEVEL_INIT
|
||||
select SYS_FSL_SRDS_1
|
||||
select SYS_HAS_SERDES
|
||||
select SYS_FSL_DDR
|
||||
|
|
@ -96,6 +98,7 @@ config ARCH_LS1046A
|
|||
select FSL_LSCH2
|
||||
select GICV2
|
||||
select HAS_FSL_XHCI_USB if USB_HOST
|
||||
select SKIP_LOWLEVEL_INIT
|
||||
select SYS_FSL_SRDS_1
|
||||
select SYS_HAS_SERDES
|
||||
select SYS_FSL_DDR
|
||||
|
|
@ -134,6 +137,7 @@ config ARCH_LS1088A
|
|||
select FSL_LAYERSCAPE
|
||||
select FSL_LSCH3
|
||||
select GICV3
|
||||
select SKIP_LOWLEVEL_INIT
|
||||
select SYS_FSL_SRDS_1
|
||||
select SYS_HAS_SERDES
|
||||
select SYS_FSL_DDR
|
||||
|
|
@ -181,6 +185,7 @@ config ARCH_LS2080A
|
|||
select FSL_LAYERSCAPE
|
||||
select FSL_LSCH3
|
||||
select GICV3
|
||||
select SKIP_LOWLEVEL_INIT
|
||||
select SYS_FSL_SRDS_1
|
||||
select SYS_HAS_SERDES
|
||||
select SYS_FSL_DDR
|
||||
|
|
@ -296,6 +301,7 @@ config ARCH_LX2160A
|
|||
|
||||
config FSL_LSCH2
|
||||
bool
|
||||
select SKIP_LOWLEVEL_INIT
|
||||
select SYS_FSL_HAS_CCI400
|
||||
select SYS_FSL_HAS_SEC
|
||||
select SYS_FSL_SEC_COMPAT_5
|
||||
|
|
@ -447,7 +453,6 @@ config QSPI_AHB_INIT
|
|||
|
||||
config FSPI_AHB_EN_4BYTE
|
||||
bool "Enable 4-byte Fast Read command for AHB mode"
|
||||
default n
|
||||
help
|
||||
The default setting for FlexSPI AHB bus just supports 3-byte addressing.
|
||||
But some FlexSPI flash sizes are up to 64MBytes.
|
||||
|
|
|
|||
|
|
@ -61,8 +61,8 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
#endif
|
||||
cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
|
||||
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
|
||||
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
|
||||
sys_info->freq_ddrbus = get_board_ddr_clk();
|
||||
#else
|
||||
sys_info->freq_ddrbus = sysclk;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -78,10 +78,10 @@ void get_sys_info(struct sys_info *sys_info)
|
|||
void *offset;
|
||||
|
||||
sys_info->freq_systembus = sysclk;
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
|
||||
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
|
||||
sys_info->freq_ddrbus = get_board_ddr_clk();
|
||||
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
||||
sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
|
||||
sys_info->freq_ddrbus2 = get_board_ddr_clk();
|
||||
#endif
|
||||
#else
|
||||
sys_info->freq_ddrbus = sysclk;
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ reset:
|
|||
orr r0,r0,#0xd3
|
||||
msr cpsr,r0
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
|
|
@ -92,7 +92,7 @@ c_runtime_cpu_setup:
|
|||
*
|
||||
*************************************************************************
|
||||
*/
|
||||
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
|
||||
cpu_init_crit:
|
||||
/*
|
||||
* flush v4 I/D caches
|
||||
|
|
@ -111,7 +111,7 @@ cpu_init_crit:
|
|||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
mov pc, lr /* back to my caller */
|
||||
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
|
||||
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
|
||||
|
||||
/*
|
||||
* Enable MMU to use DCache as DRAM.
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ reset:
|
|||
* we do sys-critical inits only at reboot,
|
||||
* not when booting from ram!
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
|
|
@ -95,7 +95,7 @@ cpu_init_crit:
|
|||
ldr r1, cpuspeed
|
||||
str r1, [r0, #PPCR]
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
/*
|
||||
* before relocating, we have to setup RAM timing
|
||||
* because memory timing is board-dependend, you will
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
|
||||
#define __ARCH_ARM_MACH_CHILISOM_SOM_H__
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
void chilisom_enable_pin_mux(void);
|
||||
void chilisom_spl_board_init(void);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -298,7 +298,6 @@ endchoice
|
|||
|
||||
config ATMEL_SFR
|
||||
bool
|
||||
default n
|
||||
|
||||
config SYS_SOC
|
||||
default "at91"
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
|
||||
#include <config.h>
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/at91_mc.h>
|
||||
|
|
@ -148,4 +148,4 @@ SMRDATA1:
|
|||
.word CONFIG_SYS_SDRAM_VAL
|
||||
SMRDATA1E:
|
||||
/* SMRDATA1 is 176 bytes long */
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -1,8 +1,13 @@
|
|||
config MACH_IMX
|
||||
bool
|
||||
|
||||
config HAS_CAAM
|
||||
bool
|
||||
|
||||
config IMX_CONFIG
|
||||
string
|
||||
string "DCD script to use"
|
||||
depends on MACH_IMX
|
||||
default "arch/arm/mach-imx/spl_sd.cfg"
|
||||
|
||||
config ROM_UNIFIED_SECTIONS
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -102,7 +102,6 @@ config MX6_OCRAM_256KB
|
|||
config MX6_DDRCAL
|
||||
bool "Include dynamic DDR calibration routines"
|
||||
depends on SPL
|
||||
default n
|
||||
help
|
||||
Say "Y" if your board uses dynamic (per-boot) DDR calibration.
|
||||
If unsure, say N.
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ config TARGET_COLIBRI_IMX7
|
|||
select DM
|
||||
select DM_SERIAL
|
||||
select DM_THERMAL
|
||||
select MX7D
|
||||
imply CMD_DM
|
||||
|
||||
endchoice
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@ const struct rproc_att hostmap[] = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
/* enable all periherial can be accessed in nosec mode */
|
||||
static void init_csu(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec)
|
|||
return usec;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
int timer_init(void)
|
||||
{
|
||||
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@ config SYS_VENDOR
|
|||
|
||||
config MT8512
|
||||
bool "MediaTek MT8512 SoC"
|
||||
default n
|
||||
|
||||
choice
|
||||
prompt "MediaTek board select"
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ if ARCH_MVEBU
|
|||
|
||||
config HAVE_MVEBU_EFUSE
|
||||
bool
|
||||
default n
|
||||
|
||||
config ARMADA_32BIT
|
||||
bool
|
||||
|
|
@ -184,6 +183,33 @@ config TARGET_CRS3XX_98DX3236
|
|||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "DDR bus width"
|
||||
default DDR_64BIT
|
||||
depends on ARMADA_XP
|
||||
|
||||
config DDR_64BIT
|
||||
bool "64bit bus width"
|
||||
|
||||
config DDR_32BIT
|
||||
bool "32bit bus width"
|
||||
|
||||
endchoice
|
||||
|
||||
config DDR_LOG_LEVEL
|
||||
int "DDR training code log level"
|
||||
depends on ARMADA_XP
|
||||
default 0
|
||||
range 0 3
|
||||
help
|
||||
Amount of information provided on error while running the DDR
|
||||
training code. At level 0, provides an error code in a case of
|
||||
failure, RL, WL errors and other algorithm failure. At level 1,
|
||||
provides the D-Unit setup (SPD/Static configuration). At level 2,
|
||||
provides the windows margin as a results of DQS centeralization.
|
||||
At level 3, rovides the windows margin of each DQ as a results of
|
||||
DQS centeralization.
|
||||
|
||||
config SYS_BOARD
|
||||
default "clearfog" if TARGET_CLEARFOG
|
||||
default "helios4" if TARGET_HELIOS4
|
||||
|
|
@ -284,14 +310,12 @@ endchoice
|
|||
|
||||
config MVEBU_EFUSE
|
||||
bool "Enable eFuse support"
|
||||
default n
|
||||
depends on HAVE_MVEBU_EFUSE
|
||||
help
|
||||
Enable support for reading and writing eFuses on mvebu SoCs.
|
||||
|
||||
config MVEBU_EFUSE_FAKE
|
||||
bool "Fake eFuse access (dry run)"
|
||||
default n
|
||||
depends on MVEBU_EFUSE
|
||||
help
|
||||
This enables a "dry run" mode where eFuses are not really programmed.
|
||||
|
|
|
|||
|
|
@ -27,10 +27,6 @@
|
|||
|
||||
#define CONFIG_SYS_L2_PL310
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* By default the generated mvebu kwbimage.cfg is used
|
||||
* If for some board, different configuration file need to be used,
|
||||
|
|
|
|||
|
|
@ -120,6 +120,7 @@ config AM33XX
|
|||
select SPECIFY_CONSOLE_INDEX
|
||||
imply NAND_OMAP_ELM
|
||||
imply NAND_OMAP_GPMC
|
||||
imply SKIP_LOWLEVEL_INIT
|
||||
imply SPL_NAND_AM33XX_BCH
|
||||
imply SPL_NAND_SUPPORT
|
||||
imply SYS_I2C_OMAP24XX
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ endif
|
|||
obj-$(CONFIG_TI816X) += clock_ti816x.o
|
||||
obj-y += sys_info.o
|
||||
obj-y += ddr.o
|
||||
ifeq ($(CONFIG_TI816X)$(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y += emif4.o
|
||||
endif
|
||||
obj-$(CONFIG_TI816X) += ti816x_emif4.o
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
int dram_init(void)
|
||||
{
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
sdram_init();
|
||||
#endif
|
||||
|
||||
|
|
@ -351,7 +351,7 @@ int arch_misc_init(void)
|
|||
|
||||
#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
|
||||
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
|
||||
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
|
||||
|
|
@ -599,7 +599,7 @@ void board_init_f(ulong dummy)
|
|||
int arch_cpu_init_dm(void)
|
||||
{
|
||||
hw_data_init();
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
early_system_init();
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
#include <power/tps65217.h>
|
||||
#include <spl.h>
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
|
|
@ -182,4 +182,4 @@ void sdram_init(void)
|
|||
&ddr3_chilisom_emif_reg_data, 0);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -76,8 +76,8 @@ void early_system_init(void)
|
|||
hw_data_init();
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
||||
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
|
||||
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: secure_unlock
|
||||
|
|
|
|||
|
|
@ -170,8 +170,8 @@ pll_div_val5:
|
|||
go_to_speed_end:
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
||||
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
|
||||
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
||||
ENTRY(lowlevel_init)
|
||||
ldr sp, SRAM_STACK
|
||||
str ip, [sp] /* stash ip register */
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ obj-y = cpu.o
|
|||
obj-y += dram.o
|
||||
obj-y += timer.o
|
||||
|
||||
ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT
|
||||
obj-y += lowlevel_init.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -133,7 +133,6 @@ config SYS_SOC
|
|||
config RMOBILE_EXTRAM_BOOT
|
||||
bool "Enable boot from RAM"
|
||||
depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
|
||||
default n
|
||||
|
||||
choice
|
||||
prompt "Qos setting primary"
|
||||
|
|
|
|||
|
|
@ -100,6 +100,7 @@ config ROCKCHIP_RK3288
|
|||
bool "Support Rockchip RK3288"
|
||||
select CPU_V7A
|
||||
select OF_BOARD_SETUP
|
||||
select SKIP_LOWLEVEL_INIT_ONLY
|
||||
select SUPPORT_SPL
|
||||
select SPL
|
||||
select SUPPORT_TPL
|
||||
|
|
|
|||
|
|
@ -190,7 +190,6 @@ config STM32_ECDSA_VERIFY
|
|||
|
||||
config CMD_STM32KEY
|
||||
bool "command stm32key to fuse public key hash"
|
||||
default n
|
||||
help
|
||||
fuse public key hash in corresponding fuse used to authenticate
|
||||
binary.
|
||||
|
|
|
|||
|
|
@ -629,7 +629,6 @@ config SYS_SOC
|
|||
|
||||
config UART0_PORT_F
|
||||
bool "UART0 on MicroSD breakout board"
|
||||
default n
|
||||
---help---
|
||||
Repurpose the SD card slot for getting access to the UART0 serial
|
||||
console. Primarily useful only for low level u-boot debugging on
|
||||
|
|
@ -640,7 +639,6 @@ config UART0_PORT_F
|
|||
|
||||
config OLD_SUNXI_KERNEL_COMPAT
|
||||
bool "Enable workarounds for booting old kernels"
|
||||
default n
|
||||
---help---
|
||||
Set this to enable various workarounds for old kernels, this results in
|
||||
sub-optimal settings for newer kernels, only enable if needed.
|
||||
|
|
@ -771,14 +769,12 @@ config I2C0_ENABLE
|
|||
|
||||
config I2C1_ENABLE
|
||||
bool "Enable I2C/TWI controller 1"
|
||||
default n
|
||||
select CMD_I2C
|
||||
---help---
|
||||
See I2C0_ENABLE help text.
|
||||
|
||||
config I2C2_ENABLE
|
||||
bool "Enable I2C/TWI controller 2"
|
||||
default n
|
||||
select CMD_I2C
|
||||
---help---
|
||||
See I2C0_ENABLE help text.
|
||||
|
|
@ -786,7 +782,6 @@ config I2C2_ENABLE
|
|||
if MACH_SUN6I || MACH_SUN7I
|
||||
config I2C3_ENABLE
|
||||
bool "Enable I2C/TWI controller 3"
|
||||
default n
|
||||
select CMD_I2C
|
||||
---help---
|
||||
See I2C0_ENABLE help text.
|
||||
|
|
@ -805,7 +800,6 @@ endif
|
|||
if MACH_SUN7I
|
||||
config I2C4_ENABLE
|
||||
bool "Enable I2C/TWI controller 4"
|
||||
default n
|
||||
select CMD_I2C
|
||||
---help---
|
||||
See I2C0_ENABLE help text.
|
||||
|
|
@ -813,7 +807,6 @@ endif
|
|||
|
||||
config AXP_GPIO
|
||||
bool "Enable support for gpio-s on axp PMICs"
|
||||
default n
|
||||
---help---
|
||||
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
|
||||
|
||||
|
|
@ -845,14 +838,12 @@ config VIDEO_HDMI
|
|||
config VIDEO_VGA
|
||||
bool "VGA output support"
|
||||
depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
|
||||
default n
|
||||
---help---
|
||||
Say Y here to add support for outputting video over VGA.
|
||||
|
||||
config VIDEO_VGA_VIA_LCD
|
||||
bool "VGA via LCD controller support"
|
||||
depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
|
||||
default n
|
||||
---help---
|
||||
Say Y here to add support for external DACs connected to the parallel
|
||||
LCD interface driving a VGA connector, such as found on the
|
||||
|
|
@ -861,7 +852,6 @@ config VIDEO_VGA_VIA_LCD
|
|||
config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
|
||||
bool "Force sync active high for VGA via LCD controller support"
|
||||
depends on VIDEO_VGA_VIA_LCD
|
||||
default n
|
||||
---help---
|
||||
Say Y here if you've a board which uses opendrain drivers for the vga
|
||||
hsync and vsync signals. Opendrain drivers cannot generate steep enough
|
||||
|
|
@ -879,7 +869,6 @@ config VIDEO_VGA_EXTERNAL_DAC_EN
|
|||
config VIDEO_COMPOSITE
|
||||
bool "Composite video output support"
|
||||
depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
|
||||
default n
|
||||
---help---
|
||||
Say Y here to add support for outputting composite video.
|
||||
|
||||
|
|
@ -943,7 +932,6 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW
|
|||
config VIDEO_LCD_PANEL_I2C
|
||||
bool "LCD panel needs to be configured via i2c"
|
||||
depends on VIDEO_SUNXI
|
||||
default n
|
||||
select CMD_I2C
|
||||
---help---
|
||||
Say y here if the LCD panel needs to be configured via i2c. This
|
||||
|
|
@ -976,7 +964,6 @@ config VIDEO_LCD_IF_LVDS
|
|||
|
||||
config SUNXI_DE2
|
||||
bool
|
||||
default n
|
||||
|
||||
config VIDEO_DE2
|
||||
bool "Display Engine 2 video driver"
|
||||
|
|
|
|||
|
|
@ -72,6 +72,7 @@ config TEGRA_ARMV7_COMMON
|
|||
select CPU_V7A
|
||||
select SPL
|
||||
select SPL_BOARD_INIT if SPL
|
||||
select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
|
||||
select SUPPORT_SPL
|
||||
select TEGRA_CLKRST
|
||||
select TEGRA_COMMON
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ config TARGET_MALTA
|
|||
select DYNAMIC_IO_PORT_BASE
|
||||
select MIPS_CM
|
||||
select MIPS_INSERT_BOOT_CONFIG
|
||||
select MIPS_L1_CACHE_SHIFT_6
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select MIPS_L2_CACHE
|
||||
select OF_CONTROL
|
||||
select OF_ISA_BUS
|
||||
|
|
@ -132,7 +132,7 @@ config TARGET_BOSTON
|
|||
select DM
|
||||
select DM_SERIAL
|
||||
select MIPS_CM
|
||||
select MIPS_L1_CACHE_SHIFT_6
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select MIPS_L2_CACHE
|
||||
select OF_BOARD_SETUP
|
||||
select OF_CONTROL
|
||||
|
|
@ -153,7 +153,7 @@ config TARGET_XILFPGA
|
|||
select DM_ETH
|
||||
select DM_GPIO
|
||||
select DM_SERIAL
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select OF_CONTROL
|
||||
select ROM_EXCEPTION_VECTORS
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -346,7 +346,6 @@ config MIPS_RELOCATION_TABLE_SIZE
|
|||
|
||||
config RESTORE_EXCEPTION_VECTOR_BASE
|
||||
bool "Restore exception vector base before booting linux kernel"
|
||||
default n
|
||||
help
|
||||
In U-Boot the exception vector base will be moved to top of memory,
|
||||
to be used to display register dump when exception occurs.
|
||||
|
|
@ -361,7 +360,6 @@ config RESTORE_EXCEPTION_VECTOR_BASE
|
|||
config OVERRIDE_EXCEPTION_VECTOR_BASE
|
||||
bool "Override the exception vector base to be restored"
|
||||
depends on RESTORE_EXCEPTION_VECTOR_BASE
|
||||
default n
|
||||
help
|
||||
Enable this option if you want to use a different exception vector
|
||||
base rather than the previously saved one.
|
||||
|
|
@ -376,7 +374,6 @@ config NEW_EXCEPTION_VECTOR_BASE
|
|||
|
||||
config INIT_STACK_WITHOUT_MALLOC_F
|
||||
bool "Do not reserve malloc space on initial stack"
|
||||
default n
|
||||
help
|
||||
Enable this option if you don't want to reserve malloc space on
|
||||
initial stack. This is useful if the initial stack can't hold large
|
||||
|
|
@ -385,7 +382,6 @@ config INIT_STACK_WITHOUT_MALLOC_F
|
|||
|
||||
config SPL_INIT_STACK_WITHOUT_MALLOC_F
|
||||
bool "Do not reserve malloc space on initial stack in SPL"
|
||||
default n
|
||||
help
|
||||
Enable this option if you don't want to reserve malloc space on
|
||||
initial stack. This is useful if the initial stack can't hold large
|
||||
|
|
@ -394,7 +390,6 @@ config SPL_INIT_STACK_WITHOUT_MALLOC_F
|
|||
|
||||
config SPL_LOADER_SUPPORT
|
||||
bool
|
||||
default n
|
||||
help
|
||||
Enable this option if you want to use SPL loaders without DM enabled.
|
||||
|
||||
|
|
@ -422,7 +417,6 @@ config MIPS_BOOT_ENV_LEGACY
|
|||
|
||||
config MIPS_BOOT_FDT
|
||||
bool "Hand over a flattened device tree to Linux kernel"
|
||||
default n
|
||||
help
|
||||
Enable this option if you want U-Boot to hand over a flattened
|
||||
device tree to the kernel. According to UHI register $a0 will be set
|
||||
|
|
@ -501,7 +495,6 @@ config SYS_MIPS_CACHE_INIT_RAM_LOAD
|
|||
|
||||
config MIPS_INIT_STACK_IN_SRAM
|
||||
bool
|
||||
default n
|
||||
help
|
||||
Select this if the initial stack frame could be setup in SRAM.
|
||||
Normally the initial stack frame is set up in DRAM which is often
|
||||
|
|
@ -512,7 +505,6 @@ config MIPS_INIT_STACK_IN_SRAM
|
|||
|
||||
config MIPS_SRAM_INIT
|
||||
bool
|
||||
default n
|
||||
depends on MIPS_INIT_STACK_IN_SRAM
|
||||
help
|
||||
Select this if the SRAM for initial stack needs to be initialized
|
||||
|
|
@ -566,26 +558,6 @@ config SYS_CACHE_SIZE_AUTO
|
|||
so if you know the cache configuration for your system at compile
|
||||
time it would be beneficial to configure it.
|
||||
|
||||
config MIPS_L1_CACHE_SHIFT_4
|
||||
bool
|
||||
|
||||
config MIPS_L1_CACHE_SHIFT_5
|
||||
bool
|
||||
|
||||
config MIPS_L1_CACHE_SHIFT_6
|
||||
bool
|
||||
|
||||
config MIPS_L1_CACHE_SHIFT_7
|
||||
bool
|
||||
|
||||
config MIPS_L1_CACHE_SHIFT
|
||||
int
|
||||
default "7" if MIPS_L1_CACHE_SHIFT_7
|
||||
default "6" if MIPS_L1_CACHE_SHIFT_6
|
||||
default "5" if MIPS_L1_CACHE_SHIFT_5
|
||||
default "4" if MIPS_L1_CACHE_SHIFT_4
|
||||
default "5"
|
||||
|
||||
config MIPS_L2_CACHE
|
||||
bool
|
||||
help
|
||||
|
|
@ -604,7 +576,6 @@ config MIPS_CM
|
|||
|
||||
config MIPS_INSERT_BOOT_CONFIG
|
||||
bool
|
||||
default n
|
||||
help
|
||||
Enable this to insert some board-specific boot configuration in
|
||||
the U-Boot binary at offset 0x10.
|
||||
|
|
|
|||
|
|
@ -233,7 +233,7 @@ wr_done:
|
|||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
/* Initialize any external memory */
|
||||
PTR_LA t9, lowlevel_init
|
||||
|
|
@ -254,7 +254,7 @@ wr_done:
|
|||
nop
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
/* Initialize any external memory */
|
||||
PTR_LA t9, lowlevel_init
|
||||
|
|
|
|||
|
|
@ -6,17 +6,7 @@
|
|||
#ifndef __MIPS_CACHE_H__
|
||||
#define __MIPS_CACHE_H__
|
||||
|
||||
#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
|
||||
#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
|
||||
|
||||
/*
|
||||
* CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
|
||||
* DMA buffer alignment. Satisfy those drivers by providing it as a synonym
|
||||
* of ARCH_DMA_MINALIGN for now.
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
|
||||
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ choice
|
|||
|
||||
config SOC_BMIPS_BCM3380
|
||||
bool "BMIPS BCM3380 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -31,7 +31,7 @@ config SOC_BMIPS_BCM3380
|
|||
|
||||
config SOC_BMIPS_BCM6318
|
||||
bool "BMIPS BCM6318 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -41,7 +41,7 @@ config SOC_BMIPS_BCM6318
|
|||
|
||||
config SOC_BMIPS_BCM6328
|
||||
bool "BMIPS BCM6328 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -51,7 +51,7 @@ config SOC_BMIPS_BCM6328
|
|||
|
||||
config SOC_BMIPS_BCM6338
|
||||
bool "BMIPS BCM6338 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -61,7 +61,7 @@ config SOC_BMIPS_BCM6338
|
|||
|
||||
config SOC_BMIPS_BCM6348
|
||||
bool "BMIPS BCM6348 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -71,7 +71,7 @@ config SOC_BMIPS_BCM6348
|
|||
|
||||
config SOC_BMIPS_BCM6358
|
||||
bool "BMIPS BCM6358 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -81,7 +81,7 @@ config SOC_BMIPS_BCM6358
|
|||
|
||||
config SOC_BMIPS_BCM6368
|
||||
bool "BMIPS BCM6368 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -91,7 +91,7 @@ config SOC_BMIPS_BCM6368
|
|||
|
||||
config SOC_BMIPS_BCM6362
|
||||
bool "BMIPS BCM6362 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -101,7 +101,7 @@ config SOC_BMIPS_BCM6362
|
|||
|
||||
config SOC_BMIPS_BCM63268
|
||||
bool "BMIPS BCM63268 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
@ -112,7 +112,7 @@ config SOC_BMIPS_BCM63268
|
|||
|
||||
config SOC_BMIPS_BCM6838
|
||||
bool "BMIPS BCM6838 family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select MIPS_TUNE_4KC
|
||||
select SUPPORTS_BIG_ENDIAN
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ choice
|
|||
|
||||
config SOC_MT7620
|
||||
bool "MT7620"
|
||||
select MIPS_L1_CACHE_SHIFT_5
|
||||
select SYS_CACHE_SHIFT_5
|
||||
select SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
select PINCTRL_MT7620
|
||||
select MT7620_SERIAL
|
||||
|
|
@ -54,7 +54,7 @@ config SOC_MT7620
|
|||
|
||||
config SOC_MT7628
|
||||
bool "MT7628"
|
||||
select MIPS_L1_CACHE_SHIFT_5
|
||||
select SYS_CACHE_SHIFT_5
|
||||
select MIPS_INIT_STACK_IN_SRAM
|
||||
select MIPS_SRAM_INIT
|
||||
select SYS_MIPS_CACHE_INIT_RAM_LOAD
|
||||
|
|
|
|||
|
|
@ -40,7 +40,6 @@ endchoice
|
|||
config SPL_UART2_SPIS_PINMUX
|
||||
bool "Use alternative pinmux for UART2 in SPL stage"
|
||||
depends on SPL_SERIAL_SUPPORT
|
||||
default n
|
||||
help
|
||||
Select this if the UART2 of your board is connected to GPIO 16/17
|
||||
(shared with SPIS) rather than the usual GPIO 20/21.
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
.set noreorder
|
||||
|
||||
LEAF(mips_sram_init)
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
/* Setup CPU PLL */
|
||||
li t0, DELAY_USEC(1000000)
|
||||
li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG)
|
||||
|
|
@ -116,7 +116,7 @@ _cpu_pll_done:
|
|||
sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
|
||||
bnez a1, 3b
|
||||
nop
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
||||
jr ra
|
||||
nop
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ choice
|
|||
|
||||
config SOC_PIC32MZDA
|
||||
bool "Microchip PIC32MZ[DA] family"
|
||||
select MIPS_L1_CACHE_SHIFT_4
|
||||
select SYS_CACHE_SHIFT_4
|
||||
select ROM_EXCEPTION_VECTORS
|
||||
select SUPPORTS_CPU_MIPS32_R1
|
||||
select SUPPORTS_CPU_MIPS32_R2
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@ endchoice
|
|||
|
||||
config SYS_ICACHE_OFF
|
||||
bool "Do not enable icache"
|
||||
default n
|
||||
help
|
||||
Do not enable instruction cache in U-Boot.
|
||||
|
||||
|
|
@ -31,7 +30,6 @@ config SPL_SYS_ICACHE_OFF
|
|||
|
||||
config SYS_DCACHE_OFF
|
||||
bool "Do not enable dcache"
|
||||
default n
|
||||
help
|
||||
Do not enable data cache in U-Boot.
|
||||
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ mem_init:
|
|||
move $lp, $r11
|
||||
ret
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
move $r10, $lp
|
||||
|
|
@ -144,4 +144,4 @@ enable_fpu:
|
|||
ret
|
||||
#endif
|
||||
|
||||
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -164,7 +164,7 @@ sdram_b0_cr:
|
|||
ret
|
||||
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
|
@ -314,4 +314,4 @@ show_led:
|
|||
li $r8, (CONFIG_DEBUG_LED)
|
||||
swi $r7, [$r8]
|
||||
ret
|
||||
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ set_ivb:
|
|||
|
||||
jal mem_init
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
jal lowlevel_init
|
||||
/*
|
||||
* gp = ~VMA for burn mode
|
||||
|
|
|
|||
|
|
@ -131,6 +131,7 @@ config MPC83XX_LDP_PIN
|
|||
config ARCH_MPC830X
|
||||
bool
|
||||
select MPC83XX_SDHC_SUPPORT
|
||||
select SYS_CACHE_SHIFT_5
|
||||
|
||||
config ARCH_MPC8308
|
||||
bool
|
||||
|
|
@ -154,6 +155,7 @@ config ARCH_MPC831X
|
|||
select MPC83XX_PCI_SUPPORT
|
||||
select MPC83XX_TSEC1_SUPPORT
|
||||
select MPC83XX_TSEC2_SUPPORT
|
||||
select SYS_CACHE_SHIFT_5
|
||||
|
||||
config ARCH_MPC8313
|
||||
bool
|
||||
|
|
@ -165,9 +167,11 @@ config ARCH_MPC832X
|
|||
bool
|
||||
select MPC83XX_QUICC_ENGINE
|
||||
select MPC83XX_PCI_SUPPORT
|
||||
select SYS_CACHE_SHIFT_5
|
||||
|
||||
config ARCH_MPC834X
|
||||
bool
|
||||
select SYS_CACHE_SHIFT_5
|
||||
|
||||
config ARCH_MPC8349
|
||||
bool
|
||||
|
|
@ -184,6 +188,7 @@ config ARCH_MPC8360
|
|||
select MPC83XX_PCI_SUPPORT
|
||||
select MPC83XX_LDP_PIN
|
||||
select MPC83XX_SECOND_I2C
|
||||
select SYS_CACHE_SHIFT_5
|
||||
|
||||
config ARCH_MPC837X
|
||||
bool
|
||||
|
|
@ -196,6 +201,7 @@ config ARCH_MPC837X
|
|||
select MPC83XX_SATA_SUPPORT
|
||||
select MPC83XX_LDP_PIN
|
||||
select MPC83XX_SECOND_I2C
|
||||
select SYS_CACHE_SHIFT_5
|
||||
select FSL_ELBC
|
||||
|
||||
config SYS_IMMR
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ obj-y += cpu.o
|
|||
obj-y += cpu_init.o
|
||||
obj-y += speed.o
|
||||
obj-y += interrupts.o
|
||||
obj-y += ecc.o
|
||||
obj-$(CONFIG_DDR_ECC_CMD) += ecc.o
|
||||
ifndef CONFIG_PINCTRL
|
||||
obj-$(CONFIG_QE) += qe_io.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
#include <mpc83xx.h>
|
||||
#include <command.h>
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
|
||||
void ecc_print_status(void)
|
||||
{
|
||||
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
|
|
@ -386,4 +385,3 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc,
|
|||
" - writes pattern injecting errors with word access\n"
|
||||
" - writes pattern with word access, generates error\n"
|
||||
" - disables injects\n" " - re-inits memory");
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -834,12 +834,6 @@ long int spd_sdram()
|
|||
#endif
|
||||
debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
|
||||
|
||||
#if defined(CONFIG_DDR_2T_TIMING)
|
||||
/*
|
||||
* Enable 2T timing by setting sdram_cfg[16].
|
||||
*/
|
||||
sdram_cfg |= SDRAM_CFG_2T_EN;
|
||||
#endif
|
||||
/* Enable controller, and GO! */
|
||||
ddr->sdram_cfg = sdram_cfg;
|
||||
sync();
|
||||
|
|
@ -914,16 +908,12 @@ void ddr_enable_ecc(unsigned int dram_size)
|
|||
pattern[0] = 0xdeadbeef;
|
||||
pattern[1] = 0xdeadbeef;
|
||||
|
||||
#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
|
||||
dma_meminit(pattern[0], dram_size);
|
||||
#else
|
||||
debug("ddr init: CPU FP write method\n");
|
||||
size = dram_size;
|
||||
for (p = 0; p < (u64*)(size); p++) {
|
||||
ppcDWstore((u32*)p, pattern);
|
||||
}
|
||||
sync();
|
||||
#endif
|
||||
|
||||
t_end = get_tbms();
|
||||
icache_disable();
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@ config TARGET_MPC8548CDS
|
|||
bool "Support MPC8548CDS"
|
||||
select ARCH_MPC8548
|
||||
select FSL_VIA
|
||||
select SYS_CACHE_SHIFT_5
|
||||
|
||||
config TARGET_P1010RDB_PA
|
||||
bool "Support P1010RDB_PA"
|
||||
|
|
@ -322,6 +323,7 @@ config ARCH_MPC8540
|
|||
config ARCH_MPC8544
|
||||
bool
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_5
|
||||
select SYS_FSL_ERRATUM_A005125
|
||||
select FSL_PCIE_RESET
|
||||
select SYS_FSL_HAS_DDR2
|
||||
|
|
@ -356,6 +358,7 @@ config ARCH_MPC8560
|
|||
config ARCH_P1010
|
||||
bool
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_5
|
||||
select SYS_FSL_ERRATUM_A004477
|
||||
select SYS_FSL_ERRATUM_A004508
|
||||
select SYS_FSL_ERRATUM_A005125
|
||||
|
|
@ -401,6 +404,7 @@ config ARCH_P1011
|
|||
config ARCH_P1020
|
||||
bool
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_5
|
||||
select SYS_FSL_ERRATUM_A004508
|
||||
select SYS_FSL_ERRATUM_A005125
|
||||
select SYS_FSL_ERRATUM_ELBC_A001
|
||||
|
|
@ -496,6 +500,7 @@ config ARCH_P1025
|
|||
config ARCH_P2020
|
||||
bool
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_5
|
||||
select SYS_FSL_ERRATUM_A004477
|
||||
select SYS_FSL_ERRATUM_A004508
|
||||
select SYS_FSL_ERRATUM_A005125
|
||||
|
|
@ -516,6 +521,7 @@ config ARCH_P2041
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select SYS_FSL_ERRATUM_A004510
|
||||
select SYS_FSL_ERRATUM_A004849
|
||||
select SYS_FSL_ERRATUM_A005275
|
||||
|
|
@ -540,6 +546,7 @@ config ARCH_P3041
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select SYS_FSL_DDR_VER_44
|
||||
select SYS_FSL_ERRATUM_A004510
|
||||
select SYS_FSL_ERRATUM_A004849
|
||||
|
|
@ -569,6 +576,7 @@ config ARCH_P4080
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select SYS_FSL_DDR_VER_44
|
||||
select SYS_FSL_ERRATUM_A004510
|
||||
select SYS_FSL_ERRATUM_A004580
|
||||
|
|
@ -607,6 +615,7 @@ config ARCH_P5040
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select SYS_FSL_DDR_VER_44
|
||||
select SYS_FSL_ERRATUM_A004510
|
||||
select SYS_FSL_ERRATUM_A004699
|
||||
|
|
@ -630,11 +639,13 @@ config ARCH_P5040
|
|||
|
||||
config ARCH_QEMU_E500
|
||||
bool
|
||||
select SYS_CACHE_SHIFT_5
|
||||
|
||||
config ARCH_T1024
|
||||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select SYS_FSL_DDR_VER_50
|
||||
select SYS_FSL_ERRATUM_A008378
|
||||
select SYS_FSL_ERRATUM_A008109
|
||||
|
|
@ -657,6 +668,7 @@ config ARCH_T1040
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select SYS_FSL_DDR_VER_50
|
||||
select SYS_FSL_ERRATUM_A008044
|
||||
select SYS_FSL_ERRATUM_A008378
|
||||
|
|
@ -679,6 +691,7 @@ config ARCH_T1042
|
|||
bool
|
||||
select E500MC
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select SYS_FSL_DDR_VER_50
|
||||
select SYS_FSL_ERRATUM_A008044
|
||||
select SYS_FSL_ERRATUM_A008378
|
||||
|
|
@ -702,6 +715,7 @@ config ARCH_T2080
|
|||
select E500MC
|
||||
select E6500
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select SYS_FSL_DDR_VER_47
|
||||
select SYS_FSL_ERRATUM_A006379
|
||||
select SYS_FSL_ERRATUM_A006593
|
||||
|
|
@ -731,6 +745,7 @@ config ARCH_T4240
|
|||
select E500MC
|
||||
select E6500
|
||||
select FSL_LAW
|
||||
select SYS_CACHE_SHIFT_6
|
||||
select SYS_FSL_DDR_VER_47
|
||||
select SYS_FSL_ERRATUM_A004468
|
||||
select SYS_FSL_ERRATUM_A005871
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <clock_legacy.h>
|
||||
#include <init.h>
|
||||
#include <irq_func.h>
|
||||
#include <log.h>
|
||||
|
|
@ -52,7 +53,8 @@ int checkcpu (void)
|
|||
uint major, minor;
|
||||
struct cpu_type *cpu;
|
||||
char buf1[32], buf2[32];
|
||||
#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
|
||||
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
|
||||
defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
|
||||
ccsr_gur_t __iomem *gur =
|
||||
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
#endif
|
||||
|
|
@ -70,12 +72,12 @@ int checkcpu (void)
|
|||
>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
|
||||
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
|
||||
#else /* CONFIG_FSL_CORENET */
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
|
||||
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
|
||||
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
|
||||
#else
|
||||
u32 ddr_ratio = 0;
|
||||
#endif /* CONFIG_DDR_CLK_FREQ */
|
||||
#endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
|
||||
#endif /* CONFIG_FSL_CORENET */
|
||||
|
||||
unsigned int i, core, nr_cores = cpu_numcores();
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <clock_legacy.h>
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/global_data.h>
|
||||
#include <linux/compiler.h>
|
||||
|
|
@ -104,8 +105,8 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
|
||||
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
|
||||
sys_info->freq_ddrbus = get_board_ddr_clk();
|
||||
#else
|
||||
sys_info->freq_ddrbus = sysclk;
|
||||
#endif
|
||||
|
|
@ -538,12 +539,12 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
|
||||
sys_info->freq_ddrbus = sys_info->freq_systembus;
|
||||
|
||||
#ifdef CONFIG_DDR_CLK_FREQ
|
||||
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
|
||||
{
|
||||
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
|
||||
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
|
||||
if (ddr_ratio != 0x7)
|
||||
sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
|
||||
sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -19,9 +19,11 @@ choice
|
|||
|
||||
config MPC866
|
||||
bool "MPC866"
|
||||
select SYS_CACHE_SHIFT_4
|
||||
|
||||
config MPC885
|
||||
bool "MPC885"
|
||||
select SYS_CACHE_SHIFT_4
|
||||
|
||||
endchoice
|
||||
|
||||
|
|
|
|||
|
|
@ -25,13 +25,6 @@
|
|||
*/
|
||||
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
|
||||
|
||||
/*
|
||||
* For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
|
||||
*/
|
||||
#ifndef CONFIG_SYS_CACHELINE_SIZE
|
||||
#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
|
||||
#endif
|
||||
|
||||
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
|
||||
#define L1_CACHE_PAGES 8
|
||||
|
||||
|
|
|
|||
|
|
@ -26,15 +26,6 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
/* Check if boards need to enable FSL DMA engine for SDRAM init */
|
||||
#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
|
||||
#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
|
||||
((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
|
||||
!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
|
||||
#define CONFIG_FSL_DMA
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Provide a default boot page translation virtual address that lines up with
|
||||
* Freescale's default e500 reset page.
|
||||
|
|
|
|||
|
|
@ -22,9 +22,11 @@ config TARGET_SIFIVE_UNLEASHED
|
|||
|
||||
config TARGET_SIFIVE_UNMATCHED
|
||||
bool "Support SiFive Unmatched Board"
|
||||
select SYS_CACHE_SHIFT_6
|
||||
|
||||
config TARGET_SIPEED_MAIX
|
||||
bool "Support Sipeed Maix Board"
|
||||
select SYS_CACHE_SHIFT_6
|
||||
|
||||
config TARGET_OPENPITON_RISCV64
|
||||
bool "Support RISC-V cores on OpenPiton SoC"
|
||||
|
|
@ -33,7 +35,6 @@ endchoice
|
|||
|
||||
config SYS_ICACHE_OFF
|
||||
bool "Do not enable icache"
|
||||
default n
|
||||
help
|
||||
Do not enable instruction cache in U-Boot.
|
||||
|
||||
|
|
@ -46,7 +47,6 @@ config SPL_SYS_ICACHE_OFF
|
|||
|
||||
config SYS_DCACHE_OFF
|
||||
bool "Do not enable dcache"
|
||||
default n
|
||||
help
|
||||
Do not enable data cache in U-Boot.
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,5 @@
|
|||
#else
|
||||
#define ARCH_DMA_MINALIGN 16
|
||||
#endif
|
||||
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
|
||||
|
||||
#endif /* __SANDBOX_CACHE_H__ */
|
||||
|
|
|
|||
|
|
@ -146,14 +146,12 @@ config HPET_ADDRESS
|
|||
|
||||
config SMM_TSEG
|
||||
bool
|
||||
default n
|
||||
|
||||
config SMM_TSEG_SIZE
|
||||
hex
|
||||
|
||||
config X86_RESET_VECTOR
|
||||
bool
|
||||
default n
|
||||
select BINMAN
|
||||
|
||||
# The following options control where the 16-bit and 32-bit init lies
|
||||
|
|
@ -490,7 +488,7 @@ config FSP_SYS_MALLOC_F_LEN
|
|||
config FSP_USE_UPD
|
||||
bool
|
||||
depends on FSP_VERSION1
|
||||
default y
|
||||
default y if !NORTHBRIDGE_INTEL_IVYBRIDGE
|
||||
help
|
||||
Most FSPs use UPD data region for some FSP customization. But there
|
||||
are still some FSPs that might not even have UPD. For such FSPs,
|
||||
|
|
@ -536,7 +534,6 @@ config HAVE_MRC
|
|||
config CACHE_MRC_BIN
|
||||
bool
|
||||
depends on HAVE_MRC
|
||||
default n
|
||||
help
|
||||
Enable caching for the memory reference code binary. This uses an
|
||||
MTRR (memory type range register) to turn on caching for the section
|
||||
|
|
@ -605,7 +602,6 @@ config HAVE_MICROCODE
|
|||
|
||||
config SMP
|
||||
bool "Enable Symmetric Multiprocessing"
|
||||
default n
|
||||
help
|
||||
Enable use of more than one CPU in U-Boot and the Operating System
|
||||
when loaded. Each CPU will be started up and information can be
|
||||
|
|
@ -745,7 +741,6 @@ menu "System tables"
|
|||
|
||||
config GENERATE_PIRQ_TABLE
|
||||
bool "Generate a PIRQ table"
|
||||
default n
|
||||
help
|
||||
Generate a PIRQ routing table for this board. The PIRQ routing table
|
||||
is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
|
||||
|
|
@ -769,7 +764,6 @@ config GENERATE_SFI_TABLE
|
|||
|
||||
config GENERATE_MP_TABLE
|
||||
bool "Generate an MP (Multi-Processor) table"
|
||||
default n
|
||||
help
|
||||
Generate an MP (Multi-Processor) table for this board. The MP table
|
||||
provides a way for the operating system to support for symmetric
|
||||
|
|
@ -778,7 +772,6 @@ config GENERATE_MP_TABLE
|
|||
|
||||
config GENERATE_ACPI_TABLE
|
||||
bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
|
||||
default n
|
||||
select QFW if QEMU
|
||||
help
|
||||
The Advanced Configuration and Power Interface (ACPI) specification
|
||||
|
|
|
|||
|
|
@ -45,7 +45,6 @@ config SMM_TSEG_SIZE
|
|||
|
||||
config ENABLE_VMX
|
||||
bool "Enable VMX for virtualization"
|
||||
default n
|
||||
help
|
||||
Virtual Machine Extensions are provided in many x86 CPUs. These
|
||||
provide various facilities for allowing a host OS to provide an
|
||||
|
|
@ -64,10 +63,6 @@ config FSP_ADDR
|
|||
hex
|
||||
default 0xfff80000
|
||||
|
||||
config FSP_USE_UPD
|
||||
bool
|
||||
default n
|
||||
|
||||
config FSP_BROKEN_HOB
|
||||
bool
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -7,13 +7,8 @@
|
|||
#define __X86_CACHE_H__
|
||||
|
||||
/*
|
||||
* If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
|
||||
* use 64-bytes, a safe default for x86.
|
||||
* Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment.
|
||||
*/
|
||||
#ifndef CONFIG_SYS_CACHELINE_SIZE
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#endif
|
||||
|
||||
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
||||
|
||||
static inline void wbinvd(void)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@ endchoice
|
|||
|
||||
config SYS_ICACHE_OFF
|
||||
bool "Do not enable icache"
|
||||
default n
|
||||
help
|
||||
Do not enable instruction cache in U-Boot.
|
||||
|
||||
|
|
@ -31,7 +30,6 @@ config SPL_SYS_ICACHE_OFF
|
|||
|
||||
config SYS_DCACHE_OFF
|
||||
bool "Do not enable dcache"
|
||||
default n
|
||||
help
|
||||
Do not enable data cache in U-Boot.
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8qm_rom7720"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/advantech/imx8qm_rom7720_a1/imximage.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -8,6 +8,9 @@ config SYS_BOARD
|
|||
config SYS_BOARD_VERSION
|
||||
default 5
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/aristainetos/aristainetos2.cfg"
|
||||
|
||||
endif
|
||||
|
||||
if TARGET_ARISTAINETOS2CCSLB
|
||||
|
|
@ -20,4 +23,7 @@ config SYS_BOARD
|
|||
config SYS_BOARD_VERSION
|
||||
default 6
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/aristainetos/aristainetos2.cfg"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,7 +9,4 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "opos6uldev"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "arch/arm/mach-imx/spl_sd.cfg"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8mm_beacon"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -11,11 +11,12 @@ config SYS_CONFIG_NAME
|
|||
|
||||
config IMX8MN_FORCE_NOM_SOC
|
||||
bool "Force to use nominal mode for SOC and ARM"
|
||||
default n
|
||||
|
||||
config IMX8MN_BEACON_2GB_LPDDR
|
||||
bool "Enable 2GB LPDDR"
|
||||
default n
|
||||
|
||||
config IMX_CONFIG
|
||||
default "arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
|
|
|
|||
|
|
@ -9,4 +9,7 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "mx53cx9020"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/beckhoff/mx53cx9020/imximage.cfg"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
# Copyright (C) 2018 Robert Bosch Power Tools GmbH
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
static const struct ddr_data ddr3_data = {
|
||||
|
|
|
|||
|
|
@ -9,4 +9,7 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "nitrogen6x"
|
||||
|
||||
config DDR_MB
|
||||
int "Memory size in MB"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,4 +9,7 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8mm-cl-iot-gate"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "cgtqmx8"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/congatec/cgtqmx8/imximage.cfg"
|
||||
|
||||
source "board/congatec/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@ endif
|
|||
config VOL_MONITOR_LTC3882_READ
|
||||
depends on VID
|
||||
bool "Enable the LTC3882 voltage monitor read"
|
||||
default n
|
||||
help
|
||||
This option enables LTC3882 voltage monitor read
|
||||
functionality. It is used by common VID driver.
|
||||
|
|
@ -36,13 +35,11 @@ config VOL_MONITOR_LTC3882_READ
|
|||
config VOL_MONITOR_LTC3882_SET
|
||||
depends on VID
|
||||
bool "Enable the LTC3882 voltage monitor set"
|
||||
default n
|
||||
help
|
||||
This option enables LTC3882 voltage monitor set
|
||||
functionality. It is used by common VID driver.
|
||||
|
||||
config USB_TCPC
|
||||
bool "USB Typec port controller simple driver"
|
||||
default n
|
||||
help
|
||||
Enable USB type-c port controller (TCPC) driver
|
||||
|
|
|
|||
|
|
@ -9,4 +9,7 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "mx7ulp_com"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/ea/mx7ulp_com/imximage.cfg"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
|
||||
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
|
||||
obj-y := mux.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ static void set_mpu_and_core_voltage(void)
|
|||
}
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
||||
static const struct ddr_data ddr2_data = {
|
||||
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
|
||||
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
|
||||
|
|
@ -235,7 +235,7 @@ void sdram_init(void)
|
|||
config_ddr(266, &ioregs, &ddr2_data,
|
||||
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
|
||||
}
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|
||||
|
||||
#ifdef CONFIG_DEBUG_UART
|
||||
void board_debug_uart_init(void)
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8mm_icore_mx8mm"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -23,7 +23,6 @@ config CMD_ESBC_VALIDATE
|
|||
|
||||
config FSL_USE_PCA9547_MUX
|
||||
bool "Enable PCA9547 I2C Mux on Freescale boards"
|
||||
default n
|
||||
help
|
||||
This option enables the PCA9547 I2C mux on Freescale boards.
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@
|
|||
#ifndef __ASSEMBLY__
|
||||
|
||||
extern unsigned long get_board_sys_clk(void);
|
||||
extern unsigned long get_board_ddr_clk(void);
|
||||
extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -9,4 +9,7 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8mm_evk"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -11,7 +11,9 @@ config SYS_CONFIG_NAME
|
|||
|
||||
config IMX8MN_LOW_DRIVE_MODE
|
||||
bool "Enable the low drive mode of iMX8MN on EVK board"
|
||||
default n
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8mp_evk"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,4 +9,7 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8mq_evk"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "arch/arm/mach-imx/imx8m/imximage.cfg"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8qm_mek"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/freescale/imx8qm_mek/imximage.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ config SYS_VENDOR
|
|||
config SYS_CONFIG_NAME
|
||||
default "imx8qxp_mek"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/freescale/imx8qxp_mek/imximage.cfg"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -113,6 +113,5 @@ Start Address End Address Description Size
|
|||
|
||||
LS1021a rev1.0 Soc specific Options/Settings
|
||||
--------------------------------------------
|
||||
If the LS1021a Soc is rev1.0, you need modify the configure file.
|
||||
Add the following define in include/configs/ls1021aqds.h:
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
If the LS1021a Soc is rev1.0, you need modify the configuration and enable
|
||||
CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar.
|
||||
|
|
|
|||
|
|
@ -127,6 +127,7 @@ unsigned long get_board_sys_clk(void)
|
|||
return 66666666;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
|
||||
unsigned long get_board_ddr_clk(void)
|
||||
{
|
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
|
||||
|
|
@ -141,6 +142,7 @@ unsigned long get_board_ddr_clk(void)
|
|||
}
|
||||
return 66666666;
|
||||
}
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -110,6 +110,5 @@ Start Address End Address Description Size
|
|||
|
||||
LS1021a rev1.0 Soc specific Options/Settings
|
||||
--------------------------------------------
|
||||
If the LS1021a Soc is rev1.0, you need modify the configure file.
|
||||
Add the following define in include/configs/ls1021atwr.h:
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
If the LS1021a Soc is rev1.0, you need modify the configuration and enable
|
||||
CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar.
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Reference in a new issue