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[ppc4xx] Fix problem with NAND booting on AMCC Acadia
The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
86ba99e341
commit
df8a24cdd3
8 changed files with 34 additions and 11 deletions
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o
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COBJS = $(BOARD).o cmd_acadia.o memory.o pll.o
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SOBJS =
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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@ -55,10 +55,12 @@ int board_early_init_f(void)
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{
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unsigned int reg;
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#if !defined(CONFIG_NAND_U_BOOT)
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/* don't reinit PLL when booting via I2C bootstrap option */
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mfsdr(SDR_PINSTP, reg);
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if (reg != 0xf0000000)
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board_pll_init_f();
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#endif
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acadia_gpio_init();
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@ -31,6 +31,8 @@
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#include <asm/io.h>
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#include <asm/gpio.h>
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extern void board_pll_init_f(void);
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/*
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* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
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*/
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@ -67,6 +69,15 @@ static void cram_bcr_write(u32 wr_val)
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long int initdram(int board_type)
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{
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#if defined(CONFIG_NAND_SPL)
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u32 reg;
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/* don't reinit PLL when booting via I2C bootstrap option */
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mfsdr(SDR_PINSTP, reg);
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if (reg != 0xf0000000)
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board_pll_init_f();
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#endif
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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int i;
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u32 val;
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@ -564,7 +564,7 @@ ProgramCheck:
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STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
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STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
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STD_EXCEPTION(0xa00, APU, UnknownException)
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#endif
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#endif
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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#ifdef CONFIG_440
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@ -889,7 +889,7 @@ _start:
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*/
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lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
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ori r3,r3,CFG_OCM_DATA_ADDR@l
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ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */
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ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
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mtdcr ocmplb3cr1,r3 /* Set PLB Access */
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ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
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mtdcr ocmplb3cr2,r3 /* Set PLB Access */
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@ -1623,7 +1623,7 @@ trap_init:
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li r7, .L_APU - _start + _START_OFFSET
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bl trap_reloc
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li r7, .L_InstructionTLBError - _start + _START_OFFSET
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bl trap_reloc
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@ -75,7 +75,7 @@
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#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
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/* On Chip Memory location */
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#define CFG_OCM_DATA_ADDR 0xF8000000
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#define CFG_OCM_DATA_ADDR 0xf8000000
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#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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@ -159,7 +159,7 @@
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*/
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#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
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#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/
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#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
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#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
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@ -30,7 +30,7 @@ AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o resetvec.o
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COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o
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COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -39,7 +39,8 @@ LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
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nandobj := $(OBJTREE)/nand_spl/
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ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
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ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
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$(nandobj)System.map
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all: $(obj).depend $(ALL)
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@ -54,6 +55,11 @@ $(nandobj)u-boot-spl: $(OBJS)
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-Map $(nandobj)u-boot-spl.map \
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-o $(nandobj)u-boot-spl
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$(nandobj)System.map: $(nandobj)u-boot-spl
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@$(NM) $< | \
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grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
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sort > $(nandobj)System.map
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# create symbolic links for common files
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# from cpu directory
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@ -78,6 +84,10 @@ $(obj)memory.c:
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@rm -f $(obj)memory.c
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ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c
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$(obj)pll.c:
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@rm -f $(obj)pll.c
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ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c
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# from nand_spl directory
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$(obj)nand_boot.c:
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@rm -f $(obj)nand_boot.c
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@ -32,11 +32,11 @@
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# We will copy this SPL into internal SRAM in start.S. So we set
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# TEXT_BASE to starting address in internal SRAM here.
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#
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TEXT_BASE = 0xF8003000
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TEXT_BASE = 0xf8004000
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# PAD_TO used to generate a 16kByte binary needed for the combined image
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# -> PAD_TO = TEXT_BASE + 0x4000
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PAD_TO = 0xF8007000
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PAD_TO = 0xf8008000
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG
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@ -24,7 +24,7 @@
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OUTPUT_ARCH(powerpc:common)
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SECTIONS
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{
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.resetvec 0xF8003FFC :
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.resetvec 0xf8004ffc :
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{
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*(.resetvec)
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} = 0xffff
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