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p4080/serdes: Implement the XAUI workaround for SERDES9 erratum
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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5 changed files with 116 additions and 0 deletions
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@ -44,6 +44,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
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puts("Work-around for Erratum SERDES8 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
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puts("Work-around for Erratum SERDES9 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
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puts("Work-around for Erratum CPU22 enabled\n");
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#endif
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@ -168,6 +168,90 @@ int serdes_get_first_lane(enum srds_prtcl device)
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return __serdes_get_first_lane(prtcl, device);
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}
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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/*
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* Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
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* SERDES protocol.
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*
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* Returns a negative error code if the given device is not supported for the
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* given SERDES protocol.
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*/
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static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
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{
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int lane;
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lane = __serdes_get_first_lane(prtcl, device);
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if (unlikely(lane < 0))
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return lane;
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return serdes_get_bank_by_lane(lane);
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}
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static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
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int first)
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{
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int lane;
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for (lane = first; lane < SRDS_MAX_LANES; lane++) {
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if (serdes_get_prtcl(prtcl, lane) != device)
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break;
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}
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return lane - first;
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}
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static void __serdes_reset_rx(serdes_corenet_t *regs,
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uint32_t prtcl,
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enum srds_prtcl device)
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{
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int lane, idx, first, last;
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lane = __serdes_get_first_lane(prtcl, device);
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if (unlikely(lane < 0))
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return;
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first = serdes_get_lane_idx(lane);
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last = first + __serdes_get_lane_count(prtcl, device, lane);
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/*
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* Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
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* selected as XAUI to place the lane into reset.
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*/
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for (idx = first; idx < last; idx++)
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clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
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/* Wait at least 250 ns */
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udelay(1);
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/*
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* Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
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* selected as XAUI to bring the lane out of reset.
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*/
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for (idx = first; idx < last; idx++)
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setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
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}
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void serdes_reset_rx(enum srds_prtcl device)
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{
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u32 prtcl;
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const ccsr_gur_t *gur;
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serdes_corenet_t *regs;
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if (unlikely(device == NONE))
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return;
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gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Is serdes enabled at all? */
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if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
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return;
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regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
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__serdes_reset_rx(regs, prtcl, device);
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}
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#endif
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#ifndef CONFIG_SYS_DCSRBAR_PHYS
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#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
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#define CONFIG_SYS_DCSRBAR 0x80000000
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@ -317,6 +401,9 @@ void fsl_serdes_init(void)
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char srds_lpd_opt[16];
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const char *srds_lpd_arg;
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size_t arglen;
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#endif
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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enum srds_prtcl device;
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#endif
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char buffer[HWCONFIG_BUFFER_SIZE];
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char *buf = NULL;
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@ -452,6 +539,17 @@ void fsl_serdes_init(void)
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break;
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case XAUI_FM1:
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case XAUI_FM2:
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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/*
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* Set BnTTLCRy0[FLT_SEL] = 000011 and set
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* BnTTLCRy0[17] = 1 for each of the SerDes lanes
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* selected as XAUI on each bank before XAUI is
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* initialized.
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*/
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clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
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SRDS_TTLCR0_FLT_SEL_MASK,
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0x03000000 | SRDS_TTLCR0_PM_DIS);
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#endif
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if (lane_prtcl == XAUI_FM1)
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
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FSL_CORENET_DEVDISR2_10GEC1;
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@ -470,6 +568,8 @@ void fsl_serdes_init(void)
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#ifdef DEBUG
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puts("\n");
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#endif
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#endif
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for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
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@ -527,4 +627,11 @@ void fsl_serdes_init(void)
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continue;
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}
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}
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
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if (is_serdes_configured(device))
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__serdes_reset_rx(srds_regs, cfg, device);
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}
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#endif
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}
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@ -304,6 +304,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
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#define CONFIG_SYS_P4080_ERRATUM_CPU22
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#define CONFIG_SYS_P4080_ERRATUM_SERDES8
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#define CONFIG_SYS_P4080_ERRATUM_SERDES9
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/* P5010 is single core version of P5020 */
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#elif defined(CONFIG_PPC_P5010)
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@ -55,6 +55,9 @@ void fsl_serdes_init(void);
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#ifdef CONFIG_FSL_CORENET
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int serdes_get_first_lane(enum srds_prtcl device);
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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void serdes_reset_rx(enum srds_prtcl device);
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#endif
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#endif
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#endif /* __FSL_SERDES_H */
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@ -2137,6 +2137,8 @@ typedef struct serdes_corenet {
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#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
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u32 res3;
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u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
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#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
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#define SRDS_TTLCR0_PM_DIS 0x00004000
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u32 res4[7];
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} lane[24];
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u32 res6[384];
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