MX: RTC13783 uses general function to access PMIC

The RTC is part of the Freescale's PMIC controller.
Use general function to access to PMIC internal registers.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
This commit is contained in:
Stefano Babic 2010-04-16 17:11:19 +02:00
parent 28bb6d34d3
commit dfe5e14fa2
4 changed files with 31 additions and 67 deletions

View file

@ -23,53 +23,30 @@
#include <common.h> #include <common.h>
#include <rtc.h> #include <rtc.h>
#include <spi.h> #include <spi.h>
#include <fsl_pmic.h>
static struct spi_slave *slave;
int rtc_get(struct rtc_time *rtc) int rtc_get(struct rtc_time *rtc)
{ {
u32 day1, day2, time; u32 day1, day2, time;
u32 reg; int tim, i = 0;
int err, tim, i = 0;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
CONFIG_MC13783_SPI_CS, 1000000,
SPI_MODE_2 | SPI_CS_HIGH);
if (!slave)
return -1;
}
if (spi_claim_bus(slave))
return -1;
do { do {
reg = 0x2c000000; day1 = pmic_reg_read(REG_RTC_DAY);
err = spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day1, if (day1 < 0)
SPI_XFER_BEGIN | SPI_XFER_END); return -1;
if (err) time = pmic_reg_read(REG_RTC_TIME);
return err; if (time < 0)
return -1;
reg = 0x28000000; day2 = pmic_reg_read(REG_RTC_DAY);
err = spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&time, if (day2 < 0)
SPI_XFER_BEGIN | SPI_XFER_END); return -1;
if (err)
return err;
reg = 0x2c000000;
err = spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day2,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
} while (day1 != day2 && i++ < 3); } while (day1 != day2 && i++ < 3);
spi_release_bus(slave);
tim = day1 * 86400 + time; tim = day1 * 86400 + time;
to_tm(tim, rtc); to_tm(tim, rtc);
rtc->tm_yday = 0; rtc->tm_yday = 0;
@ -80,34 +57,15 @@ int rtc_get(struct rtc_time *rtc)
int rtc_set(struct rtc_time *rtc) int rtc_set(struct rtc_time *rtc)
{ {
u32 time, day, reg; u32 time, day;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
CONFIG_MC13783_SPI_CS, 1000000,
SPI_MODE_2 | SPI_CS_HIGH);
if (!slave)
return -1;
}
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday, time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
rtc->tm_hour, rtc->tm_min, rtc->tm_sec); rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
day = time / 86400; day = time / 86400;
time %= 86400; time %= 86400;
if (spi_claim_bus(slave)) pmic_reg_write(REG_RTC_DAY, day);
return -1; pmic_reg_write(REG_RTC_TIME, time);
reg = 0x2c000000 | day | 0x80000000;
spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day,
SPI_XFER_BEGIN | SPI_XFER_END);
reg = 0x28000000 | time | 0x80000000;
spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&time,
SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
return 0; return 0;
} }

View file

@ -68,10 +68,13 @@
#define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1 #define CONFIG_RTC_MC13783 1
/* MC13783 connected to CSPI2 and SS0 */
#define CONFIG_MC13783_SPI_BUS 1
#define CONFIG_MC13783_SPI_CS 0
/* allow to overwrite serial and ethaddr */ /* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE

View file

@ -65,10 +65,12 @@
#define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1 #define CONFIG_RTC_MC13783 1
/* MC13783 connected to CSPI2 and SS0 */
#define CONFIG_MC13783_SPI_BUS 1
#define CONFIG_MC13783_SPI_CS 0
/* allow to overwrite serial and ethaddr */ /* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE

View file

@ -69,12 +69,13 @@
#define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 2
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13783 1 #define CONFIG_RTC_MC13783 1
/* MC13783 connected to CSPI2 and SS2 */
#define CONFIG_MC13783_SPI_BUS 1
#define CONFIG_MC13783_SPI_CS 2
/* allow to overwrite serial and ethaddr */ /* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1 #define CONFIG_CONS_INDEX 1