mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 13:41:31 +00:00
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: powerpc/ppc4xx: Remove typedefs for gdsys FPGA powerpc/ppc4xx: Fix typo in gdsys_fpga.h powerpc/ppc4xx: Update gdsys board configurations powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20 powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes powerpc/ppc4xx: Make gdsys 405ep boards reset more generic powerpc/ppc4xx: Adjust environment size on neo
This commit is contained in:
commit
e0f6a4e8b1
21 changed files with 507 additions and 301 deletions
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@ -28,12 +28,9 @@
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#include <asm/ppc4xx-gpio.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/global_data.h>
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#include <asm/global_data.h>
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#include "405ep.h"
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#include <gdsys_fpga.h>
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#include <gdsys_fpga.h>
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#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
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#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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#define REFLECTION_TESTPATTERN 0xdede
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#define REFLECTION_TESTPATTERN 0xdede
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#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
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#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
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@ -55,7 +52,6 @@ void print_fpga_state(unsigned dev)
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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unsigned k;
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unsigned k;
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unsigned ctr;
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->fpga_state[k] = 0;
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gd->fpga_state[k] = 0;
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@ -73,26 +69,29 @@ int board_early_init_f(void)
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* -> ca. 15 us
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* -> ca. 15 us
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*/
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*/
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mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
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mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
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return 0;
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}
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int board_early_init_r(void)
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{
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unsigned k;
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unsigned ctr;
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->fpga_state[k] = 0;
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/*
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/*
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* setup io-latches for reset
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* reset FPGA
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*/
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*/
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
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gd405ep_init();
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
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/*
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gd405ep_set_fpga_reset(1);
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* set "startup-finished"-gpios
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*/
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gd405ep_setup_hw();
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gpio_write_bit(21, 0);
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gpio_write_bit(22, 1);
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/*
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* wait for fpga-done
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*/
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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ctr = 0;
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ctr = 0;
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while (!(in_le16((void *)LATCH2_BASE)
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while (!gd405ep_get_fpga_done(k)) {
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& CONFIG_SYS_FPGA_DONE(k))) {
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udelay(100000);
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udelay(100000);
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if (ctr++ > 5) {
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if (ctr++ > 5) {
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gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
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gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
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@ -101,15 +100,13 @@ int board_early_init_f(void)
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}
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}
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}
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}
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/*
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* setup io-latches for boot (stop reset)
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*/
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udelay(10);
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udelay(10);
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
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gd405ep_set_fpga_reset(0);
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
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struct ihs_fpga *fpga =
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(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
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#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
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#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
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u16 *reflection_target = &fpga->reflection_low;
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u16 *reflection_target = &fpga->reflection_low;
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#else
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#else
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10
board/gdsys/405ep/405ep.h
Normal file
10
board/gdsys/405ep/405ep.h
Normal file
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@ -0,0 +1,10 @@
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#ifndef __405EP_H_
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#define __405EP_H_
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/* functions to be provided by board implementation */
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void gd405ep_init(void);
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void gd405ep_set_fpga_reset(unsigned state);
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void gd405ep_setup_hw(void);
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int gd405ep_get_fpga_done(unsigned fpga);
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#endif /* __405EP_H_ */
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@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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LIB = $(obj)lib$(BOARD).o
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COBJS-$(CONFIG_NEO) += neo.o
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COBJS-$(CONFIG_IO) += io.o
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COBJS-$(CONFIG_IO) += io.o
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COBJS-$(CONFIG_IOCON) += iocon.o
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COBJS-$(CONFIG_IOCON) += iocon.o
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COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
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COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
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@ -26,16 +26,20 @@
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/ppc4xx-gpio.h>
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#include <dtt.h>
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#include "405ep.h"
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#include <gdsys_fpga.h>
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#include <gdsys_fpga.h>
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#include "../common/osd.h"
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#include "../common/osd.h"
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#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
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#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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#define LATCH2_MC2_PRESENT_N 0x0080
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#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
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#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
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#define LATCH2_MC2_PRESENT_N 0x0080
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enum {
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enum {
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UNITTYPE_VIDEO_USER = 0,
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UNITTYPE_VIDEO_USER = 0,
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UNITTYPE_MAIN_USER = 1,
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UNITTYPE_MAIN_USER = 1,
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@ -46,6 +50,8 @@ enum {
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enum {
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enum {
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HWVER_101 = 0,
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HWVER_101 = 0,
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HWVER_110 = 1,
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HWVER_110 = 1,
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HWVER_120 = 2,
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HWVER_130 = 3,
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};
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};
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enum {
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enum {
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@ -65,6 +71,14 @@ enum {
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RAM_DDR2_64 = 2,
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RAM_DDR2_64 = 2,
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};
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};
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int misc_init_r(void)
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{
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/* startup fans */
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dtt_init();
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return 0;
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}
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static unsigned int get_hwver(void)
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static unsigned int get_hwver(void)
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{
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{
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u16 latch3 = in_le16((void *)LATCH3_BASE);
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u16 latch3 = in_le16((void *)LATCH3_BASE);
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@ -81,7 +95,7 @@ static unsigned int get_mc2_present(void)
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static void print_fpga_info(unsigned dev)
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static void print_fpga_info(unsigned dev)
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{
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{
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
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struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
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u16 versions = in_le16(&fpga->versions);
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u16 versions = in_le16(&fpga->versions);
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u16 fpga_version = in_le16(&fpga->fpga_version);
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u16 fpga_version = in_le16(&fpga->fpga_version);
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u16 fpga_features = in_le16(&fpga->fpga_features);
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u16 fpga_features = in_le16(&fpga->fpga_features);
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@ -146,7 +160,15 @@ static void print_fpga_info(unsigned dev)
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break;
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break;
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case HWVER_110:
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case HWVER_110:
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printf(" HW-Ver 1.10\n");
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printf(" HW-Ver 1.10-1.12\n");
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break;
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case HWVER_120:
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printf(" HW-Ver 1.20\n");
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break;
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case HWVER_130:
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printf(" HW-Ver 1.30\n");
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break;
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break;
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default:
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default:
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@ -223,32 +245,31 @@ static void print_fpga_info(unsigned dev)
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*/
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*/
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int checkboard(void)
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int checkboard(void)
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{
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{
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char buf[64];
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char *s = getenv("serial#");
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf("Board: ");
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puts("Board: ");
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printf("DLVision 10G");
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puts("DLVision 10G");
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if (i > 0) {
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if (s != NULL) {
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puts(", serial# ");
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puts(", serial# ");
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puts(buf);
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puts(s);
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}
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}
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puts("\n");
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puts("\n");
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print_fpga_info(0);
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if (get_mc2_present())
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print_fpga_info(1);
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return 0;
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return 0;
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}
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}
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int last_stage_init(void)
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int last_stage_init(void)
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{
|
{
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
|
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
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u16 versions = in_le16(&fpga->versions);
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u16 versions = in_le16(&fpga->versions);
|
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|
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||||||
|
print_fpga_info(0);
|
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|
if (get_mc2_present())
|
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|
print_fpga_info(1);
|
||||||
|
|
||||||
if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
|
if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
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return 0;
|
return 0;
|
||||||
|
|
||||||
|
@ -261,3 +282,32 @@ int last_stage_init(void)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void gd405ep_init(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void gd405ep_set_fpga_reset(unsigned state)
|
||||||
|
{
|
||||||
|
if (state) {
|
||||||
|
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
|
||||||
|
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
|
||||||
|
} else {
|
||||||
|
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
|
||||||
|
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void gd405ep_setup_hw(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* set "startup-finished"-gpios
|
||||||
|
*/
|
||||||
|
gpio_write_bit(21, 0);
|
||||||
|
gpio_write_bit(22, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
int gd405ep_get_fpga_done(unsigned fpga)
|
||||||
|
{
|
||||||
|
return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
|
||||||
|
}
|
||||||
|
|
|
@ -27,10 +27,16 @@
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/ppc4xx-gpio.h>
|
#include <asm/ppc4xx-gpio.h>
|
||||||
|
|
||||||
|
#include <dtt.h>
|
||||||
#include <miiphy.h>
|
#include <miiphy.h>
|
||||||
|
|
||||||
|
#include "405ep.h"
|
||||||
#include <gdsys_fpga.h>
|
#include <gdsys_fpga.h>
|
||||||
|
|
||||||
|
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
|
||||||
|
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
|
||||||
|
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
|
||||||
|
|
||||||
#define PHYREG_CONTROL 0
|
#define PHYREG_CONTROL 0
|
||||||
#define PHYREG_PAGE_ADDRESS 22
|
#define PHYREG_PAGE_ADDRESS 22
|
||||||
#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
|
#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
|
||||||
|
@ -47,6 +53,14 @@ enum {
|
||||||
HWVER_122 = 3,
|
HWVER_122 = 3,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
int misc_init_r(void)
|
||||||
|
{
|
||||||
|
/* startup fans */
|
||||||
|
dtt_init();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
int configure_gbit_phy(unsigned char addr)
|
int configure_gbit_phy(unsigned char addr)
|
||||||
{
|
{
|
||||||
unsigned short value;
|
unsigned short value;
|
||||||
|
@ -87,9 +101,23 @@ err_out:
|
||||||
*/
|
*/
|
||||||
int checkboard(void)
|
int checkboard(void)
|
||||||
{
|
{
|
||||||
char buf[64];
|
char *s = getenv("serial#");
|
||||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
|
||||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
|
puts("Board: CATCenter Io");
|
||||||
|
|
||||||
|
if (s != NULL) {
|
||||||
|
puts(", serial# ");
|
||||||
|
puts(s);
|
||||||
|
}
|
||||||
|
|
||||||
|
puts("\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void print_fpga_info(void)
|
||||||
|
{
|
||||||
|
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
|
||||||
u16 versions = in_le16(&fpga->versions);
|
u16 versions = in_le16(&fpga->versions);
|
||||||
u16 fpga_version = in_le16(&fpga->fpga_version);
|
u16 fpga_version = in_le16(&fpga->fpga_version);
|
||||||
u16 fpga_features = in_le16(&fpga->fpga_features);
|
u16 fpga_features = in_le16(&fpga->fpga_features);
|
||||||
|
@ -103,15 +131,7 @@ int checkboard(void)
|
||||||
feature_channels = fpga_features & 0x007f;
|
feature_channels = fpga_features & 0x007f;
|
||||||
feature_expansion = fpga_features & (1<<15);
|
feature_expansion = fpga_features & (1<<15);
|
||||||
|
|
||||||
printf("Board: ");
|
puts("FPGA: ");
|
||||||
|
|
||||||
printf("CATCenter Io");
|
|
||||||
|
|
||||||
if (i > 0) {
|
|
||||||
puts(", serial# ");
|
|
||||||
puts(buf);
|
|
||||||
}
|
|
||||||
puts("\n ");
|
|
||||||
|
|
||||||
switch (unit_type) {
|
switch (unit_type) {
|
||||||
case UNITTYPE_CCD_SWITCH:
|
case UNITTYPE_CCD_SWITCH:
|
||||||
|
@ -152,8 +172,6 @@ int checkboard(void)
|
||||||
printf(" %d channel(s)", feature_channels);
|
printf(" %d channel(s)", feature_channels);
|
||||||
|
|
||||||
printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
|
printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -161,9 +179,11 @@ int checkboard(void)
|
||||||
*/
|
*/
|
||||||
int last_stage_init(void)
|
int last_stage_init(void)
|
||||||
{
|
{
|
||||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
|
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
|
||||||
unsigned int k;
|
unsigned int k;
|
||||||
|
|
||||||
|
print_fpga_info();
|
||||||
|
|
||||||
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
|
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
|
||||||
bb_miiphy_read, bb_miiphy_write);
|
bb_miiphy_read, bb_miiphy_write);
|
||||||
|
|
||||||
|
@ -175,3 +195,32 @@ int last_stage_init(void)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void gd405ep_init(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void gd405ep_set_fpga_reset(unsigned state)
|
||||||
|
{
|
||||||
|
if (state) {
|
||||||
|
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
|
||||||
|
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
|
||||||
|
} else {
|
||||||
|
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
|
||||||
|
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void gd405ep_setup_hw(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* set "startup-finished"-gpios
|
||||||
|
*/
|
||||||
|
gpio_write_bit(21, 0);
|
||||||
|
gpio_write_bit(22, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
int gd405ep_get_fpga_done(unsigned fpga)
|
||||||
|
{
|
||||||
|
return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
|
||||||
|
}
|
||||||
|
|
|
@ -27,10 +27,15 @@
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/ppc4xx-gpio.h>
|
#include <asm/ppc4xx-gpio.h>
|
||||||
|
|
||||||
|
#include "405ep.h"
|
||||||
#include <gdsys_fpga.h>
|
#include <gdsys_fpga.h>
|
||||||
|
|
||||||
#include "../common/osd.h"
|
#include "../common/osd.h"
|
||||||
|
|
||||||
|
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
|
||||||
|
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
|
||||||
|
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
|
||||||
|
|
||||||
enum {
|
enum {
|
||||||
UNITTYPE_MAIN_SERVER = 0,
|
UNITTYPE_MAIN_SERVER = 0,
|
||||||
UNITTYPE_MAIN_USER = 1,
|
UNITTYPE_MAIN_USER = 1,
|
||||||
|
@ -69,9 +74,25 @@ enum {
|
||||||
*/
|
*/
|
||||||
int checkboard(void)
|
int checkboard(void)
|
||||||
{
|
{
|
||||||
char buf[64];
|
char *s = getenv("serial#");
|
||||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
|
||||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
|
puts("Board: ");
|
||||||
|
|
||||||
|
puts("IoCon");
|
||||||
|
|
||||||
|
if (s != NULL) {
|
||||||
|
puts(", serial# ");
|
||||||
|
puts(s);
|
||||||
|
}
|
||||||
|
|
||||||
|
puts("\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void print_fpga_info(void)
|
||||||
|
{
|
||||||
|
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
|
||||||
u16 versions = in_le16(&fpga->versions);
|
u16 versions = in_le16(&fpga->versions);
|
||||||
u16 fpga_version = in_le16(&fpga->fpga_version);
|
u16 fpga_version = in_le16(&fpga->fpga_version);
|
||||||
u16 fpga_features = in_le16(&fpga->fpga_features);
|
u16 fpga_features = in_le16(&fpga->fpga_features);
|
||||||
|
@ -95,16 +116,6 @@ int checkboard(void)
|
||||||
feature_carriers = (fpga_features & 0x000c) >> 2;
|
feature_carriers = (fpga_features & 0x000c) >> 2;
|
||||||
feature_video_channels = fpga_features & 0x0003;
|
feature_video_channels = fpga_features & 0x0003;
|
||||||
|
|
||||||
printf("Board: ");
|
|
||||||
|
|
||||||
printf("IoCon");
|
|
||||||
|
|
||||||
if (i > 0) {
|
|
||||||
puts(", serial# ");
|
|
||||||
puts(buf);
|
|
||||||
}
|
|
||||||
puts("\n ");
|
|
||||||
|
|
||||||
switch (unit_type) {
|
switch (unit_type) {
|
||||||
case UNITTYPE_MAIN_USER:
|
case UNITTYPE_MAIN_USER:
|
||||||
printf("Mainchannel");
|
printf("Mainchannel");
|
||||||
|
@ -205,12 +216,12 @@ int checkboard(void)
|
||||||
printf(", %d carrier(s)", feature_carriers);
|
printf(", %d carrier(s)", feature_carriers);
|
||||||
|
|
||||||
printf(", %d video channel(s)\n", feature_video_channels);
|
printf(", %d video channel(s)\n", feature_video_channels);
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int last_stage_init(void)
|
int last_stage_init(void)
|
||||||
{
|
{
|
||||||
|
print_fpga_info();
|
||||||
|
|
||||||
return osd_probe(0);
|
return osd_probe(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -231,3 +242,32 @@ int fpga_gpio_get(int pin)
|
||||||
{
|
{
|
||||||
return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
|
return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void gd405ep_init(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void gd405ep_set_fpga_reset(unsigned state)
|
||||||
|
{
|
||||||
|
if (state) {
|
||||||
|
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
|
||||||
|
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
|
||||||
|
} else {
|
||||||
|
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
|
||||||
|
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void gd405ep_setup_hw(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* set "startup-finished"-gpios
|
||||||
|
*/
|
||||||
|
gpio_write_bit(21, 0);
|
||||||
|
gpio_write_bit(22, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
int gd405ep_get_fpga_done(unsigned fpga)
|
||||||
|
{
|
||||||
|
return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
|
||||||
|
}
|
||||||
|
|
161
board/gdsys/405ep/neo.c
Normal file
161
board/gdsys/405ep/neo.c
Normal file
|
@ -0,0 +1,161 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2011
|
||||||
|
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <command.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/ppc4xx-gpio.h>
|
||||||
|
#include <dtt.h>
|
||||||
|
|
||||||
|
#include "405ep.h"
|
||||||
|
#include <gdsys_fpga.h>
|
||||||
|
|
||||||
|
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
|
||||||
|
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
|
||||||
|
#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
|
||||||
|
|
||||||
|
enum {
|
||||||
|
UNITTYPE_CCX16 = 1,
|
||||||
|
UNITTYPE_CCIP216 = 2,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
HWVER_300 = 3,
|
||||||
|
};
|
||||||
|
|
||||||
|
int misc_init_r(void)
|
||||||
|
{
|
||||||
|
/* startup fans */
|
||||||
|
dtt_init();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int checkboard(void)
|
||||||
|
{
|
||||||
|
char *s = getenv("serial#");
|
||||||
|
|
||||||
|
puts("Board: CATCenter Neo");
|
||||||
|
|
||||||
|
if (s != NULL) {
|
||||||
|
puts(", serial# ");
|
||||||
|
puts(s);
|
||||||
|
}
|
||||||
|
|
||||||
|
puts("\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void print_fpga_info(void)
|
||||||
|
{
|
||||||
|
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
|
||||||
|
u16 versions = in_le16(&fpga->versions);
|
||||||
|
u16 fpga_version = in_le16(&fpga->fpga_version);
|
||||||
|
u16 fpga_features = in_le16(&fpga->fpga_features);
|
||||||
|
int fpga_state = get_fpga_state(0);
|
||||||
|
unsigned unit_type;
|
||||||
|
unsigned hardware_version;
|
||||||
|
unsigned feature_channels;
|
||||||
|
|
||||||
|
puts("FPGA: ");
|
||||||
|
if (fpga_state & FPGA_STATE_DONE_FAILED) {
|
||||||
|
printf(" done timed out\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
|
||||||
|
printf(" refelectione test failed\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
unit_type = (versions & 0xf000) >> 12;
|
||||||
|
hardware_version = versions & 0x000f;
|
||||||
|
feature_channels = fpga_features & 0x007f;
|
||||||
|
|
||||||
|
switch (unit_type) {
|
||||||
|
case UNITTYPE_CCX16:
|
||||||
|
printf("CCX-Switch");
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
printf("UnitType %d(not supported)", unit_type);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (hardware_version) {
|
||||||
|
case HWVER_300:
|
||||||
|
printf(" HW-Ver 3.00-3.12\n");
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
printf(" HW-Ver %d(not supported)\n",
|
||||||
|
hardware_version);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
printf(" FPGA V %d.%02d, features:",
|
||||||
|
fpga_version / 100, fpga_version % 100);
|
||||||
|
|
||||||
|
printf(" %d channel(s)\n", feature_channels);
|
||||||
|
}
|
||||||
|
|
||||||
|
int last_stage_init(void)
|
||||||
|
{
|
||||||
|
print_fpga_info();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gd405ep_init(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void gd405ep_set_fpga_reset(unsigned state)
|
||||||
|
{
|
||||||
|
if (state) {
|
||||||
|
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
|
||||||
|
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
|
||||||
|
} else {
|
||||||
|
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
|
||||||
|
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void gd405ep_setup_hw(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* set "startup-finished"-gpios
|
||||||
|
*/
|
||||||
|
gpio_write_bit(21, 0);
|
||||||
|
gpio_write_bit(22, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
int gd405ep_get_fpga_done(unsigned fpga)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Neo hardware has no FPGA-DONE GPIO
|
||||||
|
*/
|
||||||
|
return 1;
|
||||||
|
}
|
|
@ -219,7 +219,8 @@ int board_early_init_r(void)
|
||||||
gd405ex_set_fpga_reset(0);
|
gd405ex_set_fpga_reset(0);
|
||||||
|
|
||||||
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
|
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
|
||||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
|
struct ihs_fpga *fpga =
|
||||||
|
(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
|
||||||
#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
|
#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
|
||||||
u16 *reflection_target = &fpga->reflection_low;
|
u16 *reflection_target = &fpga->reflection_low;
|
||||||
#else
|
#else
|
||||||
|
|
|
@ -100,7 +100,7 @@ int misc_init_r(void)
|
||||||
|
|
||||||
static void print_fpga_info(unsigned dev)
|
static void print_fpga_info(unsigned dev)
|
||||||
{
|
{
|
||||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
|
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
|
||||||
u16 versions = in_le16(&fpga->versions);
|
u16 versions = in_le16(&fpga->versions);
|
||||||
u16 fpga_version = in_le16(&fpga->fpga_version);
|
u16 fpga_version = in_le16(&fpga->fpga_version);
|
||||||
u16 fpga_features = in_le16(&fpga->fpga_features);
|
u16 fpga_features = in_le16(&fpga->fpga_features);
|
||||||
|
@ -242,8 +242,8 @@ int last_stage_init(void)
|
||||||
{
|
{
|
||||||
unsigned int k;
|
unsigned int k;
|
||||||
unsigned int fpga;
|
unsigned int fpga;
|
||||||
ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
|
struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
|
||||||
ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1);
|
struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1);
|
||||||
int failed = 0;
|
int failed = 0;
|
||||||
char str_phys[] = "Setup PHYs -";
|
char str_phys[] = "Setup PHYs -";
|
||||||
char str_serdes[] = "Start SERDES blocks";
|
char str_serdes[] = "Start SERDES blocks";
|
||||||
|
|
|
@ -70,8 +70,8 @@ enum {
|
||||||
#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
|
#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
|
||||||
static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
|
static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
|
||||||
{
|
{
|
||||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
|
struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
|
||||||
ihs_i2c_t *i2c = &fpga->i2c;
|
struct ihs_i2c *i2c = &fpga->i2c;
|
||||||
|
|
||||||
while (in_le16(&fpga->extended_interrupt) & (1 << 12))
|
while (in_le16(&fpga->extended_interrupt) & (1 << 12))
|
||||||
;
|
;
|
||||||
|
@ -81,8 +81,8 @@ static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
|
||||||
|
|
||||||
static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
|
static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
|
||||||
{
|
{
|
||||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
|
struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
|
||||||
ihs_i2c_t *i2c = &fpga->i2c;
|
struct ihs_i2c *i2c = &fpga->i2c;
|
||||||
unsigned int ctr = 0;
|
unsigned int ctr = 0;
|
||||||
|
|
||||||
while (in_le16(&fpga->extended_interrupt) & (1 << 12))
|
while (in_le16(&fpga->extended_interrupt) & (1 << 12))
|
||||||
|
@ -129,7 +129,7 @@ static void mpc92469ac_calc_parameters(unsigned int fout,
|
||||||
|
|
||||||
static void mpc92469ac_set(unsigned screen, unsigned int fout)
|
static void mpc92469ac_set(unsigned screen, unsigned int fout)
|
||||||
{
|
{
|
||||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
|
struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
|
||||||
unsigned int n;
|
unsigned int n;
|
||||||
unsigned int m;
|
unsigned int m;
|
||||||
unsigned int bitval = 0;
|
unsigned int bitval = 0;
|
||||||
|
@ -265,8 +265,8 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
|
||||||
static int osd_write_videomem(unsigned screen, unsigned offset,
|
static int osd_write_videomem(unsigned screen, unsigned offset,
|
||||||
u16 *data, size_t charcount)
|
u16 *data, size_t charcount)
|
||||||
{
|
{
|
||||||
ihs_fpga_t *fpga =
|
struct ihs_fpga *fpga =
|
||||||
(ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
|
(struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen);
|
||||||
unsigned int k;
|
unsigned int k;
|
||||||
|
|
||||||
for (k = 0; k < charcount; ++k) {
|
for (k = 0; k < charcount; ++k) {
|
||||||
|
@ -318,8 +318,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||||
|
|
||||||
int osd_probe(unsigned screen)
|
int osd_probe(unsigned screen)
|
||||||
{
|
{
|
||||||
ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
|
struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
|
||||||
ihs_osd_t *osd = &fpga->osd;
|
struct ihs_osd *osd = &fpga->osd;
|
||||||
u16 version = in_le16(&osd->version);
|
u16 version = in_le16(&osd->version);
|
||||||
u16 features = in_le16(&osd->features);
|
u16 features = in_le16(&osd->features);
|
||||||
unsigned width;
|
unsigned width;
|
||||||
|
|
|
@ -1,45 +0,0 @@
|
||||||
#
|
|
||||||
# (C) Copyright 2007
|
|
||||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
|
||||||
#
|
|
||||||
# See file CREDITS for list of people who contributed to this
|
|
||||||
# project.
|
|
||||||
#
|
|
||||||
# This program is free software; you can redistribute it and/or
|
|
||||||
# modify it under the terms of the GNU General Public License as
|
|
||||||
# published by the Free Software Foundation; either version 2 of
|
|
||||||
# the License, or (at your option) any later version.
|
|
||||||
#
|
|
||||||
# This program is distributed in the hope that it will be useful,
|
|
||||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
# GNU General Public License for more details.
|
|
||||||
#
|
|
||||||
# You should have received a copy of the GNU General Public License
|
|
||||||
# along with this program; if not, write to the Free Software
|
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
# MA 02111-1307 USA
|
|
||||||
#
|
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
|
||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).o
|
|
||||||
|
|
||||||
COBJS = $(BOARD).o
|
|
||||||
SOBJS =
|
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
|
||||||
|
|
||||||
$(LIB): $(OBJS) $(SOBJS)
|
|
||||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
|
||||||
|
|
||||||
#########################################################################
|
|
||||||
|
|
||||||
# defines $(obj).depend target
|
|
||||||
include $(SRCTREE)/rules.mk
|
|
||||||
|
|
||||||
sinclude $(obj).depend
|
|
||||||
|
|
||||||
#########################################################################
|
|
|
@ -1,102 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2007-2008
|
|
||||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
|
|
||||||
#define HWTYPE_CCX16 1
|
|
||||||
#define HWREV_300 3
|
|
||||||
|
|
||||||
int board_early_init_f(void)
|
|
||||||
{
|
|
||||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
|
||||||
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
|
|
||||||
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
|
|
||||||
mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
|
|
||||||
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
|
|
||||||
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
|
|
||||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* EBC Configuration Register: set ready timeout to 512 ebc-clks
|
|
||||||
* -> ca. 15 us
|
|
||||||
*/
|
|
||||||
mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Check Board Identity:
|
|
||||||
*/
|
|
||||||
int checkboard(void)
|
|
||||||
{
|
|
||||||
char buf[64];
|
|
||||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
|
||||||
u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2);
|
|
||||||
u8 unit_type;
|
|
||||||
u8 hardware_cpu_ports;
|
|
||||||
u8 hardware_con_ports;
|
|
||||||
u8 hardware_version;
|
|
||||||
|
|
||||||
printf("Board: CATCenter Neo");
|
|
||||||
|
|
||||||
if (i > 0) {
|
|
||||||
puts(", serial# ");
|
|
||||||
puts(buf);
|
|
||||||
}
|
|
||||||
puts("\n ");
|
|
||||||
|
|
||||||
unit_type = (val & 0xf000) >> 12;
|
|
||||||
hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8;
|
|
||||||
hardware_con_ports = ((val & 0x00f0) >> 4) * 2;
|
|
||||||
hardware_version = val & 0x000f;
|
|
||||||
|
|
||||||
switch (unit_type) {
|
|
||||||
case HWTYPE_CCX16:
|
|
||||||
printf("CCX16-FPGA (80 UARTs)");
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
printf("UnitType %d, unsupported", unit_type);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
printf(", %d cpu ports, %d console ports,",
|
|
||||||
hardware_cpu_ports, hardware_con_ports);
|
|
||||||
|
|
||||||
switch (hardware_version) {
|
|
||||||
case HWREV_300:
|
|
||||||
printf(" HW-Ver 3.00\n");
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
printf(" HW-Ver %d, unsupported\n",
|
|
||||||
hardware_version);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
|
@ -990,7 +990,7 @@ intip powerpc ppc4xx intip gdsys
|
||||||
io powerpc ppc4xx 405ep gdsys
|
io powerpc ppc4xx 405ep gdsys
|
||||||
io64 powerpc ppc4xx 405ex gdsys
|
io64 powerpc ppc4xx 405ex gdsys
|
||||||
iocon powerpc ppc4xx 405ep gdsys
|
iocon powerpc ppc4xx 405ep gdsys
|
||||||
neo powerpc ppc4xx - gdsys
|
neo powerpc ppc4xx 405ep gdsys
|
||||||
icon powerpc ppc4xx - mosaixtech
|
icon powerpc ppc4xx - mosaixtech
|
||||||
MIP405 powerpc ppc4xx mip405 mpl
|
MIP405 powerpc ppc4xx mip405 mpl
|
||||||
MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T
|
MIP405T powerpc ppc4xx mip405 mpl - MIP405:MIP405T
|
||||||
|
|
|
@ -34,10 +34,12 @@
|
||||||
* Include common defines/options for all AMCC eval boards
|
* Include common defines/options for all AMCC eval boards
|
||||||
*/
|
*/
|
||||||
#define CONFIG_HOSTNAME dlvsion-10g
|
#define CONFIG_HOSTNAME dlvsion-10g
|
||||||
#define CONFIG_IDENT_STRING " dlvision-10g 0.02"
|
#define CONFIG_IDENT_STRING " dlvision-10g 0.03"
|
||||||
#include "amcc-common.h"
|
#include "amcc-common.h"
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_R
|
||||||
|
#define CONFIG_MISC_INIT_R
|
||||||
#define CONFIG_LAST_STAGE_INIT
|
#define CONFIG_LAST_STAGE_INIT
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||||
|
@ -80,6 +82,7 @@
|
||||||
* Commands additional to the ones defined in amcc-common.h
|
* Commands additional to the ones defined in amcc-common.h
|
||||||
*/
|
*/
|
||||||
#define CONFIG_CMD_CACHE
|
#define CONFIG_CMD_CACHE
|
||||||
|
#define CONFIG_CMD_DTT
|
||||||
#undef CONFIG_CMD_EEPROM
|
#undef CONFIG_CMD_EEPROM
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -115,7 +118,7 @@
|
||||||
|
|
||||||
/* Temp sensor/hwmon/dtt */
|
/* Temp sensor/hwmon/dtt */
|
||||||
#define CONFIG_DTT_LM63 1 /* National LM63 */
|
#define CONFIG_DTT_LM63 1 /* National LM63 */
|
||||||
#define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */
|
#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */
|
||||||
#define CONFIG_DTT_PWM_LOOKUPTABLE \
|
#define CONFIG_DTT_PWM_LOOKUPTABLE \
|
||||||
{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
|
{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
|
||||||
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
|
{ 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
|
||||||
|
|
|
@ -50,6 +50,10 @@
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/
|
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/
|
||||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
||||||
|
|
||||||
|
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
|
||||||
|
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
|
||||||
|
#define CONFIG_AUTOBOOT_STOP_STR " "
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Base addresses -- Note these are effective addresses where the
|
* Base addresses -- Note these are effective addresses where the
|
||||||
* actual resources get mapped (not physical addresses)
|
* actual resources get mapped (not physical addresses)
|
||||||
|
|
|
@ -37,10 +37,10 @@
|
||||||
#define CONFIG_460EX 1 /* Specific PPC460EX */
|
#define CONFIG_460EX 1 /* Specific PPC460EX */
|
||||||
#ifdef CONFIG_DEVCONCENTER
|
#ifdef CONFIG_DEVCONCENTER
|
||||||
#define CONFIG_HOSTNAME devconcenter
|
#define CONFIG_HOSTNAME devconcenter
|
||||||
#define CONFIG_IDENT_STRING " devconcenter 0.05"
|
#define CONFIG_IDENT_STRING " devconcenter 0.06"
|
||||||
#else
|
#else
|
||||||
#define CONFIG_HOSTNAME intip
|
#define CONFIG_HOSTNAME intip
|
||||||
#define CONFIG_IDENT_STRING " intip 0.05"
|
#define CONFIG_IDENT_STRING " intip 0.06"
|
||||||
#endif
|
#endif
|
||||||
#define CONFIG_440 1
|
#define CONFIG_440 1
|
||||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||||
|
|
|
@ -34,11 +34,13 @@
|
||||||
* Include common defines/options for all AMCC eval boards
|
* Include common defines/options for all AMCC eval boards
|
||||||
*/
|
*/
|
||||||
#define CONFIG_HOSTNAME io
|
#define CONFIG_HOSTNAME io
|
||||||
#define CONFIG_IDENT_STRING " io 0.04"
|
#define CONFIG_IDENT_STRING " io 0.05"
|
||||||
#include "amcc-common.h"
|
#include "amcc-common.h"
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
#define CONFIG_LAST_STAGE_INIT /* call last_stage_init */
|
#define CONFIG_BOARD_EARLY_INIT_R
|
||||||
|
#define CONFIG_MISC_INIT_R
|
||||||
|
#define CONFIG_LAST_STAGE_INIT
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||||
|
|
||||||
|
@ -48,6 +50,10 @@
|
||||||
#define PLLMR0_DEFAULT PLLMR0_266_133_66
|
#define PLLMR0_DEFAULT PLLMR0_266_133_66
|
||||||
#define PLLMR1_DEFAULT PLLMR1_266_133_66
|
#define PLLMR1_DEFAULT PLLMR1_266_133_66
|
||||||
|
|
||||||
|
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
|
||||||
|
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
|
||||||
|
#define CONFIG_AUTOBOOT_STOP_STR " "
|
||||||
|
|
||||||
/* new uImage format support */
|
/* new uImage format support */
|
||||||
#define CONFIG_FIT
|
#define CONFIG_FIT
|
||||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||||
|
@ -76,6 +82,7 @@
|
||||||
* Commands additional to the ones defined in amcc-common.h
|
* Commands additional to the ones defined in amcc-common.h
|
||||||
*/
|
*/
|
||||||
#define CONFIG_CMD_CACHE
|
#define CONFIG_CMD_CACHE
|
||||||
|
#define CONFIG_CMD_DTT
|
||||||
#undef CONFIG_CMD_EEPROM
|
#undef CONFIG_CMD_EEPROM
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -53,7 +53,7 @@
|
||||||
* Include common defines/options for all AMCC eval boards
|
* Include common defines/options for all AMCC eval boards
|
||||||
*/
|
*/
|
||||||
#define CONFIG_HOSTNAME io64
|
#define CONFIG_HOSTNAME io64
|
||||||
#define CONFIG_IDENT_STRING " io64 0.01"
|
#define CONFIG_IDENT_STRING " io64 0.02"
|
||||||
#include "amcc-common.h"
|
#include "amcc-common.h"
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
|
|
|
@ -34,10 +34,11 @@
|
||||||
* Include common defines/options for all AMCC eval boards
|
* Include common defines/options for all AMCC eval boards
|
||||||
*/
|
*/
|
||||||
#define CONFIG_HOSTNAME iocon
|
#define CONFIG_HOSTNAME iocon
|
||||||
#define CONFIG_IDENT_STRING " iocon 0.03"
|
#define CONFIG_IDENT_STRING " iocon 0.04"
|
||||||
#include "amcc-common.h"
|
#include "amcc-common.h"
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_R
|
||||||
#define CONFIG_LAST_STAGE_INIT
|
#define CONFIG_LAST_STAGE_INIT
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||||
|
@ -48,6 +49,10 @@
|
||||||
#define PLLMR0_DEFAULT PLLMR0_266_133_66
|
#define PLLMR0_DEFAULT PLLMR0_266_133_66
|
||||||
#define PLLMR1_DEFAULT PLLMR1_266_133_66
|
#define PLLMR1_DEFAULT PLLMR1_266_133_66
|
||||||
|
|
||||||
|
#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
|
||||||
|
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
|
||||||
|
#define CONFIG_AUTOBOOT_STOP_STR " "
|
||||||
|
|
||||||
/* new uImage format support */
|
/* new uImage format support */
|
||||||
#define CONFIG_FIT
|
#define CONFIG_FIT
|
||||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||||
|
|
|
@ -35,9 +35,13 @@
|
||||||
* Include common defines/options for all AMCC eval boards
|
* Include common defines/options for all AMCC eval boards
|
||||||
*/
|
*/
|
||||||
#define CONFIG_HOSTNAME neo
|
#define CONFIG_HOSTNAME neo
|
||||||
|
#define CONFIG_IDENT_STRING " neo 0.01"
|
||||||
#include "amcc-common.h"
|
#include "amcc-common.h"
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_R
|
||||||
|
#define CONFIG_MISC_INIT_R
|
||||||
|
#define CONFIG_LAST_STAGE_INIT
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||||
|
|
||||||
|
@ -149,53 +153,53 @@
|
||||||
|
|
||||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
|
||||||
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
|
#define CONFIG_ENV_ADDR 0xFFF00000
|
||||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
|
||||||
|
|
||||||
/* Address and size of Redundant Environment Sector */
|
/* Address and size of Redundant Environment Sector */
|
||||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
|
#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
|
||||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* PPC405 GPIO Configuration
|
* PPC405 GPIO Configuration
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
|
#define CONFIG_SYS_4xx_GPIO_TABLE { \
|
||||||
{ \
|
{ \
|
||||||
/* GPIO Core 0 */ \
|
/* GPIO Core 0 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
|
||||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
|
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
|
||||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
|
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
|
||||||
} \
|
} \
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -226,12 +230,22 @@
|
||||||
#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
|
#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
|
||||||
|
|
||||||
/* Memory Bank 2 (FPGA) initialization */
|
/* Memory Bank 2 (FPGA) initialization */
|
||||||
#define CONFIG_FPGA_BASE 0x7f100000
|
#define CONFIG_SYS_FPGA0_BASE 0x7f100000
|
||||||
#define CONFIG_SYS_EBC_PB2AP 0x92015480
|
#define CONFIG_SYS_EBC_PB2AP 0x92015480
|
||||||
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
|
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
|
||||||
|
|
||||||
|
#define CONFIG_SYS_FPGA_COUNT 1
|
||||||
|
|
||||||
/* Memory Bank 3 (Latches) initialization */
|
/* Memory Bank 3 (Latches) initialization */
|
||||||
|
#define CONFIG_SYS_LATCH_BASE 0x7f200000
|
||||||
#define CONFIG_SYS_EBC_PB3AP 0x92015480
|
#define CONFIG_SYS_EBC_PB3AP 0x92015480
|
||||||
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
|
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_LATCH0_RESET 0xffff
|
||||||
|
#define CONFIG_SYS_LATCH0_BOOT 0xffff
|
||||||
|
#define CONFIG_SYS_LATCH1_RESET 0xffbf
|
||||||
|
#define CONFIG_SYS_LATCH1_BOOT 0xffff
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
#endif /* __CONFIG_H */
|
||||||
|
|
|
@ -35,20 +35,20 @@ enum {
|
||||||
int get_fpga_state(unsigned dev);
|
int get_fpga_state(unsigned dev);
|
||||||
void print_fpga_state(unsigned dev);
|
void print_fpga_state(unsigned dev);
|
||||||
|
|
||||||
typedef struct ihs_gpio {
|
struct ihs_gpio {
|
||||||
u16 read;
|
u16 read;
|
||||||
u16 clear;
|
u16 clear;
|
||||||
u16 set;
|
u16 set;
|
||||||
} ihs_gpio_t;
|
};
|
||||||
|
|
||||||
typedef struct ihs_i2c {
|
struct ihs_i2c {
|
||||||
u16 write_mailbox;
|
u16 write_mailbox;
|
||||||
u16 write_mailbox_ext;
|
u16 write_mailbox_ext;
|
||||||
u16 read_mailbox;
|
u16 read_mailbox;
|
||||||
u16 read_mailbox_ext;
|
u16 read_mailbox_ext;
|
||||||
} ihs_i2c_t;
|
};
|
||||||
|
|
||||||
typedef struct ihs_osd {
|
struct ihs_osd {
|
||||||
u16 version;
|
u16 version;
|
||||||
u16 features;
|
u16 features;
|
||||||
u16 control;
|
u16 control;
|
||||||
|
@ -56,10 +56,21 @@ typedef struct ihs_osd {
|
||||||
u16 xy_scale;
|
u16 xy_scale;
|
||||||
u16 x_pos;
|
u16 x_pos;
|
||||||
u16 y_pos;
|
u16 y_pos;
|
||||||
} ihs_osd_t;
|
};
|
||||||
|
|
||||||
|
#ifdef CONFIG_NEO
|
||||||
|
struct ihs_fpga {
|
||||||
|
u16 reflection_low; /* 0x0000 */
|
||||||
|
u16 versions; /* 0x0002 */
|
||||||
|
u16 fpga_features; /* 0x0004 */
|
||||||
|
u16 fpga_version; /* 0x0006 */
|
||||||
|
u16 reserved_0[8187]; /* 0x0008 */
|
||||||
|
u16 reflection_high; /* 0x3ffe */
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_IO
|
#ifdef CONFIG_IO
|
||||||
typedef struct ihs_fpga {
|
struct ihs_fpga {
|
||||||
u16 reflection_low; /* 0x0000 */
|
u16 reflection_low; /* 0x0000 */
|
||||||
u16 versions; /* 0x0002 */
|
u16 versions; /* 0x0002 */
|
||||||
u16 fpga_features; /* 0x0004 */
|
u16 fpga_features; /* 0x0004 */
|
||||||
|
@ -68,11 +79,11 @@ typedef struct ihs_fpga {
|
||||||
u16 quad_serdes_reset; /* 0x0012 */
|
u16 quad_serdes_reset; /* 0x0012 */
|
||||||
u16 reserved_1[8181]; /* 0x0014 */
|
u16 reserved_1[8181]; /* 0x0014 */
|
||||||
u16 reflection_high; /* 0x3ffe */
|
u16 reflection_high; /* 0x3ffe */
|
||||||
} ihs_fpga_t;
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_IO64
|
#ifdef CONFIG_IO64
|
||||||
typedef struct ihs_fpga {
|
struct ihs_fpga {
|
||||||
u16 reflection_low; /* 0x0000 */
|
u16 reflection_low; /* 0x0000 */
|
||||||
u16 versions; /* 0x0002 */
|
u16 versions; /* 0x0002 */
|
||||||
u16 fpga_features; /* 0x0004 */
|
u16 fpga_features; /* 0x0004 */
|
||||||
|
@ -87,30 +98,30 @@ typedef struct ihs_fpga {
|
||||||
u16 ch0_hicb_config_int;/* 0x0502 */
|
u16 ch0_hicb_config_int;/* 0x0502 */
|
||||||
u16 reserved_3[7549]; /* 0x0504 */
|
u16 reserved_3[7549]; /* 0x0504 */
|
||||||
u16 reflection_high; /* 0x3ffe */
|
u16 reflection_high; /* 0x3ffe */
|
||||||
} ihs_fpga_t;
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_IOCON
|
#ifdef CONFIG_IOCON
|
||||||
typedef struct ihs_fpga {
|
struct ihs_fpga {
|
||||||
u16 reflection_low; /* 0x0000 */
|
u16 reflection_low; /* 0x0000 */
|
||||||
u16 versions; /* 0x0002 */
|
u16 versions; /* 0x0002 */
|
||||||
u16 fpga_version; /* 0x0004 */
|
u16 fpga_version; /* 0x0004 */
|
||||||
u16 fpga_features; /* 0x0006 */
|
u16 fpga_features; /* 0x0006 */
|
||||||
u16 reserved_0[6]; /* 0x0008 */
|
u16 reserved_0[6]; /* 0x0008 */
|
||||||
ihs_gpio_t gpio; /* 0x0014 */
|
struct ihs_gpio gpio; /* 0x0014 */
|
||||||
u16 mpc3w_control; /* 0x001a */
|
u16 mpc3w_control; /* 0x001a */
|
||||||
u16 reserved_1[19]; /* 0x001c */
|
u16 reserved_1[19]; /* 0x001c */
|
||||||
u16 videocontrol; /* 0x0042 */
|
u16 videocontrol; /* 0x0042 */
|
||||||
u16 reserved_2[93]; /* 0x0044 */
|
u16 reserved_2[93]; /* 0x0044 */
|
||||||
u16 reflection_high; /* 0x00fe */
|
u16 reflection_high; /* 0x00fe */
|
||||||
ihs_osd_t osd; /* 0x0100 */
|
struct ihs_osd osd; /* 0x0100 */
|
||||||
u16 reserved_3[88]; /* 0x010e */
|
u16 reserved_3[889]; /* 0x010e */
|
||||||
u16 videomem; /* 0x0800 */
|
u16 videomem; /* 0x0800 */
|
||||||
} ihs_fpga_t;
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_DLVISION_10G
|
#ifdef CONFIG_DLVISION_10G
|
||||||
typedef struct ihs_fpga {
|
struct ihs_fpga {
|
||||||
u16 reflection_low; /* 0x0000 */
|
u16 reflection_low; /* 0x0000 */
|
||||||
u16 versions; /* 0x0002 */
|
u16 versions; /* 0x0002 */
|
||||||
u16 fpga_version; /* 0x0004 */
|
u16 fpga_version; /* 0x0004 */
|
||||||
|
@ -118,16 +129,16 @@ typedef struct ihs_fpga {
|
||||||
u16 reserved_0[10]; /* 0x0008 */
|
u16 reserved_0[10]; /* 0x0008 */
|
||||||
u16 extended_interrupt; /* 0x001c */
|
u16 extended_interrupt; /* 0x001c */
|
||||||
u16 reserved_1[9]; /* 0x001e */
|
u16 reserved_1[9]; /* 0x001e */
|
||||||
ihs_i2c_t i2c; /* 0x0030 */
|
struct ihs_i2c i2c; /* 0x0030 */
|
||||||
u16 reserved_2[16]; /* 0x0038 */
|
u16 reserved_2[16]; /* 0x0038 */
|
||||||
u16 mpc3w_control; /* 0x0058 */
|
u16 mpc3w_control; /* 0x0058 */
|
||||||
u16 reserved_3[34]; /* 0x005a */
|
u16 reserved_3[34]; /* 0x005a */
|
||||||
u16 videocontrol; /* 0x009e */
|
u16 videocontrol; /* 0x009e */
|
||||||
u16 reserved_4[176]; /* 0x00a0 */
|
u16 reserved_4[176]; /* 0x00a0 */
|
||||||
ihs_osd_t osd; /* 0x0200 */
|
struct ihs_osd osd; /* 0x0200 */
|
||||||
u16 reserved_5[761]; /* 0x020e */
|
u16 reserved_5[761]; /* 0x020e */
|
||||||
u16 videomem; /* 0x0800 */
|
u16 videomem; /* 0x0800 */
|
||||||
} ihs_fpga_t;
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Add table
Reference in a new issue