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clk: rk3399: Enable/Disable TCPHY clocks

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Enable/Disable TCPHY clock for rk3399 platform.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki 2020-05-26 11:32:07 +08:00 • committed by Kever Yang
parent 80e191119e
commit e1b413d1a9
1 changed files with 24 additions and 0 deletions
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24
drivers/clk/rockchip/clk_rk3399.c
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@ -1147,6 +1147,18 @@ static int rk3399_clk_enable(struct clk *clk)
case HCLK_HOST1_ARB:
rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
break;
case SCLK_UPHY0_TCPDPHY_REF:
rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
break;
case SCLK_UPHY0_TCPDCORE:
rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
break;
case SCLK_UPHY1_TCPDPHY_REF:
rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
break;
case SCLK_UPHY1_TCPDCORE:
rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
break;
case SCLK_PCIEPHY_REF:
rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
break;
@ -1229,6 +1241,18 @@ static int rk3399_clk_disable(struct clk *clk)
case HCLK_HOST1_ARB:
rk_setreg(&priv->cru->clksel_con[20], BIT(8));
break;
case SCLK_UPHY0_TCPDPHY_REF:
rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
break;
case SCLK_UPHY0_TCPDCORE:
rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
break;
case SCLK_UPHY1_TCPDPHY_REF:
rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
break;
case SCLK_UPHY1_TCPDCORE:
rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
break;
case SCLK_PCIEPHY_REF:
rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
break;