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32bit BUg fix for DDR2 on 8572
This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
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2 changed files with 25 additions and 1 deletions
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@ -19,6 +19,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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{
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{
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unsigned int i;
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unsigned int i;
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volatile ccsr_ddr_t *ddr;
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volatile ccsr_ddr_t *ddr;
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u32 temp_sdram_cfg;
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switch (ctrl_num) {
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switch (ctrl_num) {
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case 0:
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case 0:
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@ -78,6 +79,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
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out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
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out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
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out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
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/* Do not enable the memory */
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temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
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temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
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/*
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/*
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* For 8572 DDR1 erratum - DDR controller may enter illegal state
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* For 8572 DDR1 erratum - DDR controller may enter illegal state
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* when operatiing in 32-bit bus mode with 4-beat bursts,
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* when operatiing in 32-bit bus mode with 4-beat bursts,
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@ -99,7 +104,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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udelay(200);
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udelay(200);
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asm volatile("sync;isync");
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asm volatile("sync;isync");
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out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
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/* Let the controller go */
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temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
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/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
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/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
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while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
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while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
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@ -51,6 +51,23 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
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#define FSL_DDR_BANK_INTERLEAVING 0x2
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#define FSL_DDR_BANK_INTERLEAVING 0x2
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#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
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#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
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/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
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*/
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#define SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG_SREN 0x40000000
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#define SDRAM_CFG_ECC_EN 0x20000000
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#define SDRAM_CFG_RD_EN 0x10000000
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#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
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#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
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#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
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#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
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#define SDRAM_CFG_DYN_PWR 0x00200000
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#define SDRAM_CFG_32_BE 0x00080000
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#define SDRAM_CFG_8_BE 0x00040000
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#define SDRAM_CFG_NCAP 0x00020000
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#define SDRAM_CFG_2T_EN 0x00008000
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#define SDRAM_CFG_BI 0x00000001
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/* Record of register values computed */
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/* Record of register values computed */
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typedef struct fsl_ddr_cfg_regs_s {
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typedef struct fsl_ddr_cfg_regs_s {
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struct {
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struct {
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