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powerpc/mpc85xx: Use GOT when loading IVORs post-relocation
Commit96d2bb952b
("powerpc/mpc85xx: Don't relocate exception vectors") simplified IVOR initialization a bit too much, failing to use the post-relocation offset. This doesn't cause a problem with normal NOR boot, in which both the pre-relocation and post-relocation addresses are 64 KiB aligned. However, if TEXT_BASE is only 4 KiB aligned, such as for NAND/SD/etc. boot on some targets, as well as the QEMU target, the post-relocation address will not be the same in the lower 16 bits, as reserve_uboot() ensures that the relocation address is always 64 KiB aligned even if the pre-relocation address was not. Use the GOT to get the proper post-relocation offsets. Fixes:96d2bb952b
("powerpc/mpc85xx: Don't relocate exception vectors") Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Alexander Graf <agraf@suse.de> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Tested-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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1 changed files with 20 additions and 15 deletions
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@ -1664,41 +1664,46 @@ clear_bss:
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*/
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.globl trap_init
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trap_init:
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mflr r11
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bl _GLOBAL_OFFSET_TABLE_-4
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mflr r12
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/* Update IVORs as per relocation */
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mtspr IVPR,r3
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li r4,CriticalInput@l
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lwz r4,CriticalInput@got(r12)
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mtspr IVOR0,r4 /* 0: Critical input */
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li r4,MachineCheck@l
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lwz r4,MachineCheck@got(r12)
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mtspr IVOR1,r4 /* 1: Machine check */
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li r4,DataStorage@l
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lwz r4,DataStorage@got(r12)
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mtspr IVOR2,r4 /* 2: Data storage */
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li r4,InstStorage@l
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lwz r4,InstStorage@got(r12)
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mtspr IVOR3,r4 /* 3: Instruction storage */
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li r4,ExtInterrupt@l
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lwz r4,ExtInterrupt@got(r12)
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mtspr IVOR4,r4 /* 4: External interrupt */
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li r4,Alignment@l
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lwz r4,Alignment@got(r12)
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mtspr IVOR5,r4 /* 5: Alignment */
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li r4,ProgramCheck@l
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lwz r4,ProgramCheck@got(r12)
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mtspr IVOR6,r4 /* 6: Program check */
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li r4,FPUnavailable@l
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lwz r4,FPUnavailable@got(r12)
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mtspr IVOR7,r4 /* 7: floating point unavailable */
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li r4,SystemCall@l
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lwz r4,SystemCall@got(r12)
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mtspr IVOR8,r4 /* 8: System call */
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/* 9: Auxiliary processor unavailable(unsupported) */
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li r4,Decrementer@l
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lwz r4,Decrementer@got(r12)
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mtspr IVOR10,r4 /* 10: Decrementer */
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li r4,IntervalTimer@l
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lwz r4,IntervalTimer@got(r12)
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mtspr IVOR11,r4 /* 11: Interval timer */
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li r4,WatchdogTimer@l
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lwz r4,WatchdogTimer@got(r12)
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mtspr IVOR12,r4 /* 12: Watchdog timer */
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li r4,DataTLBError@l
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lwz r4,DataTLBError@got(r12)
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mtspr IVOR13,r4 /* 13: Data TLB error */
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li r4,InstructionTLBError@l
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lwz r4,InstructionTLBError@got(r12)
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mtspr IVOR14,r4 /* 14: Instruction TLB error */
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li r4,DebugBreakpoint@l
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lwz r4,DebugBreakpoint@got(r12)
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mtspr IVOR15,r4 /* 15: Debug */
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mtlr r11
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blr
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.globl unlock_ram_in_cache
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