mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 14:41:31 +00:00
arm64: dts: rockchip: Add PCIe for RockPI N10
This patch adds support to enable PCIe for RockPI N10. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
parent
5217f4991e
commit
e1e1c3de24
1 changed files with 38 additions and 2 deletions
|
@ -11,6 +11,18 @@
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
|
compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
|
||||||
|
|
||||||
|
vcc3v3_pcie: vcc-pcie-regulator {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
enable-active-high;
|
||||||
|
gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pcie_pwr>;
|
||||||
|
regulator-name = "vcc3v3_pcie";
|
||||||
|
regulator-always-on;
|
||||||
|
regulator-boot-on;
|
||||||
|
vin-supply = <&vcc5v0_sys>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&cpu_l0 {
|
&cpu_l0 {
|
||||||
|
@ -142,7 +154,8 @@
|
||||||
regulator-min-microvolt = <900000>;
|
regulator-min-microvolt = <900000>;
|
||||||
regulator-max-microvolt = <900000>;
|
regulator-max-microvolt = <900000>;
|
||||||
regulator-state-mem {
|
regulator-state-mem {
|
||||||
regulator-off-in-suspend;
|
regulator-on-in-suspend;
|
||||||
|
regulator-suspend-microvolt = <900000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -177,7 +190,8 @@
|
||||||
regulator-min-microvolt = <1850000>;
|
regulator-min-microvolt = <1850000>;
|
||||||
regulator-max-microvolt = <1850000>;
|
regulator-max-microvolt = <1850000>;
|
||||||
regulator-state-mem {
|
regulator-state-mem {
|
||||||
regulator-off-in-suspend;
|
regulator-on-in-suspend;
|
||||||
|
regulator-suspend-microvolt = <1850000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -304,6 +318,22 @@
|
||||||
sdmmc-supply = <&vccio_sd>;
|
sdmmc-supply = <&vccio_sd>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&pcie_phy {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pcie0 {
|
||||||
|
ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||||
|
max-link-speed = <2>;
|
||||||
|
num-lanes = <4>;
|
||||||
|
pinctrl-0 = <&pcie_clkreqnb_cpm>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */
|
||||||
|
vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */
|
||||||
|
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
&pinctrl {
|
&pinctrl {
|
||||||
hym8563 {
|
hym8563 {
|
||||||
hym8563_int: hym8563-int {
|
hym8563_int: hym8563-int {
|
||||||
|
@ -311,6 +341,12 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pcie {
|
||||||
|
pcie_pwr: pcie-pwr {
|
||||||
|
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
pmic {
|
pmic {
|
||||||
pmic_int_l: pmic-int-l {
|
pmic_int_l: pmic-int-l {
|
||||||
rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>;
|
rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>;
|
||||||
|
|
Loading…
Add table
Reference in a new issue