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https://github.com/Fishwaldo/u-boot.git
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Tegra114: Add common CPU (shared) files
These files are used by both SPL and main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Tom Warren
Tom Warren
parent
ec1885cee1
commit
e23bb6a438
6 changed files with 1291 additions and 4 deletions
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@ -31,6 +31,7 @@
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#include <asm/arch-tegra/fuse.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/scu.h>
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#include <asm/arch-tegra/tegra.h>
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#include <asm/arch-tegra/warmboot.h>
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int tegra_get_chip_type(void)
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@ -42,7 +43,7 @@ int tegra_get_chip_type(void)
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/*
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* This is undocumented, Chip ID is bits 15:8 of the register
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* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
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* Tegra30
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* Tegra30, and 0x35 for T114.
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*/
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gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
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@ -68,6 +69,12 @@ int tegra_get_chip_type(void)
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return TEGRA_SOC_T30;
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}
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break;
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case CHIPID_TEGRA114:
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switch (tegra_sku_id) {
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case SKU_ID_T114_ENG:
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return TEGRA_SOC_T114;
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}
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break;
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}
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/* unknown sku id */
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return TEGRA_SOC_UNKNOWN;
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@ -37,8 +37,10 @@ enum {
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/* UARTs which we can enable */
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UARTA = 1 << 0,
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UARTB = 1 << 1,
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UARTC = 1 << 2,
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UARTD = 1 << 3,
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UART_COUNT = 4,
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UARTE = 1 << 4,
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UART_COUNT = 5,
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};
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/*
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@ -68,7 +70,7 @@ unsigned int query_sdram_size(void)
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case 3:
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return 0x40000000; /* 1GB */
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}
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#else /* Tegra30 */
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#else /* Tegra30/Tegra114 */
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/* bits 31:28 in OdmData are used for RAM size on T30 */
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switch ((reg) >> 28) {
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case 0:
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@ -117,12 +119,18 @@ static int uart_configs[] = {
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-1,
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FUNCMUX_UART4_GMC,
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-1,
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#else /* Tegra30 */
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#elif defined(CONFIG_TEGRA30)
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FUNCMUX_UART1_ULPI, /* UARTA */
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-1,
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-1,
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-1,
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-1,
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#else /* Tegra114 */
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-1,
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-1,
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-1,
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FUNCMUX_UART4_GMI, /* UARTD */
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-1,
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#endif
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};
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@ -138,6 +146,7 @@ static void setup_uarts(int uart_ids)
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PERIPH_ID_UART2,
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PERIPH_ID_UART3,
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PERIPH_ID_UART4,
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PERIPH_ID_UART5,
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};
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size_t i;
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@ -161,8 +170,14 @@ void board_init_uart_f(void)
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#ifdef CONFIG_TEGRA_ENABLE_UARTB
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uart_ids |= UARTB;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTC
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uart_ids |= UARTC;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTD
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uart_ids |= UARTD;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTE
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uart_ids |= UARTE;
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#endif
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setup_uarts(uart_ids);
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}
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41
arch/arm/cpu/tegra114-common/Makefile
Normal file
41
arch/arm/cpu/tegra114-common/Makefile
Normal file
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@ -0,0 +1,41 @@
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#
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# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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#
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# (C) Copyright 2000-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC)-common.o
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COBJS-y += clock.o funcmux.o pinmux.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
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all: $(obj).depend $(LIB)
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$(LIB): $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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655
arch/arm/cpu/tegra114-common/clock.c
Normal file
655
arch/arm/cpu/tegra114-common/clock.c
Normal file
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@ -0,0 +1,655 @@
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* Tegra114 Clock control functions */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/timer.h>
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#include <div64.h>
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#include <fdtdec.h>
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/*
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* Clock types that we can use as a source. The Tegra114 has muxes for the
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* peripheral clocks, and in most cases there are four options for the clock
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* source. This gives us a clock 'type' and exploits what commonality exists
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* in the device.
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*
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* Letters are obvious, except for T which means CLK_M, and S which means the
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* clock derived from 32KHz. Beware that CLK_M (also called OSC in the
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* datasheet) and PLL_M are different things. The former is the basic
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* clock supplied to the SOC from an external oscillator. The latter is the
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* memory clock PLL.
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*
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* See definitions in clock_id in the header file.
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*/
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enum clock_type_id {
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CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
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CLOCK_TYPE_MCPA, /* and so on */
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CLOCK_TYPE_MCPT,
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CLOCK_TYPE_PCM,
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CLOCK_TYPE_PCMT,
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CLOCK_TYPE_PCMT16,
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CLOCK_TYPE_PDCT,
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CLOCK_TYPE_ACPT,
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CLOCK_TYPE_ASPTE,
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CLOCK_TYPE_PMDACD2T,
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CLOCK_TYPE_PCST,
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CLOCK_TYPE_COUNT,
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CLOCK_TYPE_NONE = -1, /* invalid clock type */
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};
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enum {
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CLOCK_MAX_MUX = 8 /* number of source options for each clock */
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};
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enum {
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MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
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MASK_BITS_31_29,
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MASK_BITS_29_28,
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};
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/*
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* Clock source mux for each clock type. This just converts our enum into
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* a list of mux sources for use by the code.
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*
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* Note:
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* The extra column in each clock source array is used to store the mask
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* bits in its register for the source.
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*/
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#define CLK(x) CLOCK_ID_ ## x
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static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
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{ CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
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CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_29},
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{ CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
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CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
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MASK_BITS_31_29},
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{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_29_28}
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};
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/*
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* Clock type for each peripheral clock source. We put the name in each
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* record just so it is easy to match things up
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*/
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#define TYPE(name, type) type
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static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
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/* 0x00 */
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TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
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TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
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/* 0x08 */
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
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TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
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/* 0x10 */
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TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
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/* 0x18 */
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TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
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TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
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/* 0x20 */
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TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
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/* 0x28 */
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TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
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/* 0x30 */
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TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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/* 0x38h */ /* Jumps to reg offset 0x3B0h */
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TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
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TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
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/* 0x40 */
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TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
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TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
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TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
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TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
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TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
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/* 0x48 */
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TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
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TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
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TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
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TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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/* 0x50 */
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
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TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
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};
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/*
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* This array translates a periph_id to a periphc_internal_id
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*
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* Not present/matched up:
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* uint vi_sensor; _VI_SENSOR_0, 0x1A8
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* SPDIF - which is both 0x08 and 0x0c
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*
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*/
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#define NONE(name) (-1)
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#define OFFSET(name, value) PERIPHC_ ## name
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static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
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/* Low word: 31:0 */
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NONE(CPU),
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NONE(COP),
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NONE(TRIGSYS),
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NONE(RESERVED3),
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NONE(RTC),
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NONE(TMR),
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PERIPHC_UART1,
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PERIPHC_UART2, /* and vfir 0x68 */
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/* 8 */
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NONE(GPIO),
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PERIPHC_SDMMC2,
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NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
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PERIPHC_I2S1,
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PERIPHC_I2C1,
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PERIPHC_NDFLASH,
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PERIPHC_SDMMC1,
|
||||
PERIPHC_SDMMC4,
|
||||
|
||||
/* 16 */
|
||||
NONE(RESERVED16),
|
||||
PERIPHC_PWM,
|
||||
PERIPHC_I2S2,
|
||||
PERIPHC_EPP,
|
||||
PERIPHC_VI,
|
||||
PERIPHC_G2D,
|
||||
NONE(USBD),
|
||||
NONE(ISP),
|
||||
|
||||
/* 24 */
|
||||
PERIPHC_G3D,
|
||||
NONE(RESERVED25),
|
||||
PERIPHC_DISP2,
|
||||
PERIPHC_DISP1,
|
||||
PERIPHC_HOST1X,
|
||||
NONE(VCP),
|
||||
PERIPHC_I2S0,
|
||||
NONE(CACHE2),
|
||||
|
||||
/* Middle word: 63:32 */
|
||||
NONE(MEM),
|
||||
NONE(AHBDMA),
|
||||
NONE(APBDMA),
|
||||
NONE(RESERVED35),
|
||||
NONE(RESERVED36),
|
||||
NONE(STAT_MON),
|
||||
NONE(RESERVED38),
|
||||
NONE(RESERVED39),
|
||||
|
||||
/* 40 */
|
||||
NONE(KFUSE),
|
||||
NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
|
||||
PERIPHC_NOR,
|
||||
NONE(RESERVED43),
|
||||
PERIPHC_SBC2,
|
||||
NONE(RESERVED45),
|
||||
PERIPHC_SBC3,
|
||||
PERIPHC_I2C5,
|
||||
|
||||
/* 48 */
|
||||
NONE(DSI),
|
||||
PERIPHC_TVO, /* also CVE 0x40 */
|
||||
PERIPHC_MIPI,
|
||||
PERIPHC_HDMI,
|
||||
NONE(CSI),
|
||||
PERIPHC_TVDAC,
|
||||
PERIPHC_I2C2,
|
||||
PERIPHC_UART3,
|
||||
|
||||
/* 56 */
|
||||
NONE(RESERVED56),
|
||||
PERIPHC_EMC,
|
||||
NONE(USB2),
|
||||
NONE(USB3),
|
||||
PERIPHC_MPE,
|
||||
PERIPHC_VDE,
|
||||
NONE(BSEA),
|
||||
NONE(BSEV),
|
||||
|
||||
/* Upper word 95:64 */
|
||||
PERIPHC_SPEEDO,
|
||||
PERIPHC_UART4,
|
||||
PERIPHC_UART5,
|
||||
PERIPHC_I2C3,
|
||||
PERIPHC_SBC4,
|
||||
PERIPHC_SDMMC3,
|
||||
NONE(PCIE),
|
||||
PERIPHC_OWR,
|
||||
|
||||
/* 72 */
|
||||
NONE(AFI),
|
||||
PERIPHC_CSITE,
|
||||
NONE(PCIEXCLK),
|
||||
NONE(AVPUCQ),
|
||||
NONE(RESERVED76),
|
||||
NONE(RESERVED77),
|
||||
NONE(RESERVED78),
|
||||
NONE(DTV),
|
||||
|
||||
/* 80 */
|
||||
PERIPHC_NANDSPEED,
|
||||
PERIPHC_I2CSLOW,
|
||||
NONE(DSIB),
|
||||
NONE(RESERVED83),
|
||||
NONE(IRAMA),
|
||||
NONE(IRAMB),
|
||||
NONE(IRAMC),
|
||||
NONE(IRAMD),
|
||||
|
||||
/* 88 */
|
||||
NONE(CRAM2),
|
||||
NONE(RESERVED89),
|
||||
NONE(MDOUBLER),
|
||||
NONE(RESERVED91),
|
||||
NONE(SUSOUT),
|
||||
NONE(RESERVED93),
|
||||
NONE(RESERVED94),
|
||||
NONE(RESERVED95),
|
||||
|
||||
/* V word: 31:0 */
|
||||
NONE(CPUG),
|
||||
NONE(CPULP),
|
||||
PERIPHC_G3D2,
|
||||
PERIPHC_MSELECT,
|
||||
PERIPHC_TSENSOR,
|
||||
PERIPHC_I2S3,
|
||||
PERIPHC_I2S4,
|
||||
PERIPHC_I2C4,
|
||||
|
||||
/* 08 */
|
||||
PERIPHC_SBC5,
|
||||
PERIPHC_SBC6,
|
||||
PERIPHC_AUDIO,
|
||||
NONE(APBIF),
|
||||
PERIPHC_DAM0,
|
||||
PERIPHC_DAM1,
|
||||
PERIPHC_DAM2,
|
||||
PERIPHC_HDA2CODEC2X,
|
||||
|
||||
/* 16 */
|
||||
NONE(ATOMICS),
|
||||
NONE(RESERVED17),
|
||||
NONE(RESERVED18),
|
||||
NONE(RESERVED19),
|
||||
NONE(RESERVED20),
|
||||
NONE(RESERVED21),
|
||||
NONE(RESERVED22),
|
||||
PERIPHC_ACTMON,
|
||||
|
||||
/* 24 */
|
||||
NONE(RESERVED24),
|
||||
NONE(RESERVED25),
|
||||
NONE(RESERVED26),
|
||||
NONE(RESERVED27),
|
||||
PERIPHC_SATA,
|
||||
PERIPHC_HDA,
|
||||
NONE(RESERVED30),
|
||||
NONE(RESERVED31),
|
||||
|
||||
/* W word: 31:0 */
|
||||
NONE(HDA2HDMICODEC),
|
||||
NONE(RESERVED1_SATACOLD),
|
||||
NONE(RESERVED2_PCIERX0),
|
||||
NONE(RESERVED3_PCIERX1),
|
||||
NONE(RESERVED4_PCIERX2),
|
||||
NONE(RESERVED5_PCIERX3),
|
||||
NONE(RESERVED6_PCIERX4),
|
||||
NONE(RESERVED7_PCIERX5),
|
||||
|
||||
/* 40 */
|
||||
NONE(CEC),
|
||||
NONE(PCIE2_IOBIST),
|
||||
NONE(EMC_IOBIST),
|
||||
NONE(HDMI_IOBIST),
|
||||
NONE(SATA_IOBIST),
|
||||
NONE(MIPI_IOBIST),
|
||||
NONE(EMC1_IOBIST),
|
||||
NONE(XUSB),
|
||||
|
||||
/* 48 */
|
||||
NONE(CILAB),
|
||||
NONE(CILCD),
|
||||
NONE(CILE),
|
||||
NONE(DSIA_LP),
|
||||
NONE(DSIB_LP),
|
||||
NONE(RESERVED21_ENTROPY),
|
||||
NONE(RESERVED22_W),
|
||||
NONE(RESERVED23_W),
|
||||
|
||||
/* 56 */
|
||||
NONE(RESERVED24_W),
|
||||
NONE(AMX0),
|
||||
NONE(ADX0),
|
||||
NONE(DVFS),
|
||||
NONE(XUSB_SS),
|
||||
NONE(EMC_DLL),
|
||||
NONE(MC1),
|
||||
NONE(EMC1),
|
||||
};
|
||||
|
||||
/*
|
||||
* Get the oscillator frequency, from the corresponding hardware configuration
|
||||
* field. Note that T30/T114 support 3 new higher freqs, but we map back
|
||||
* to the old T20 freqs. Support for the higher oscillators is TBD.
|
||||
*/
|
||||
enum clock_osc_freq clock_get_osc_freq(void)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
u32 reg;
|
||||
|
||||
reg = readl(&clkrst->crc_osc_ctrl);
|
||||
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
|
||||
|
||||
if (reg & 1) /* one of the newer freqs */
|
||||
printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
|
||||
|
||||
return reg >> 2; /* Map to most common (T20) freqs */
|
||||
}
|
||||
|
||||
/* Returns a pointer to the clock source register for a peripheral */
|
||||
u32 *get_periph_source_reg(enum periph_id periph_id)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
enum periphc_internal_id internal_id;
|
||||
|
||||
/* Coresight is a special case */
|
||||
if (periph_id == PERIPH_ID_CSI)
|
||||
return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
|
||||
|
||||
assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
|
||||
internal_id = periph_id_to_internal_id[periph_id];
|
||||
assert(internal_id != -1);
|
||||
if (internal_id >= PERIPHC_VW_FIRST) {
|
||||
internal_id -= PERIPHC_VW_FIRST;
|
||||
return &clkrst->crc_clk_src_vw[internal_id];
|
||||
} else
|
||||
return &clkrst->crc_clk_src[internal_id];
|
||||
}
|
||||
|
||||
/**
|
||||
* Given a peripheral ID and the required source clock, this returns which
|
||||
* value should be programmed into the source mux for that peripheral.
|
||||
*
|
||||
* There is special code here to handle the one source type with 5 sources.
|
||||
*
|
||||
* @param periph_id peripheral to start
|
||||
* @param source PLL id of required parent clock
|
||||
* @param mux_bits Set to number of bits in mux register: 2 or 4
|
||||
* @param divider_bits Set to number of divider bits (8 or 16)
|
||||
* @return mux value (0-4, or -1 if not found)
|
||||
*/
|
||||
int get_periph_clock_source(enum periph_id periph_id,
|
||||
enum clock_id parent, int *mux_bits, int *divider_bits)
|
||||
{
|
||||
enum clock_type_id type;
|
||||
enum periphc_internal_id internal_id;
|
||||
int mux;
|
||||
|
||||
assert(clock_periph_id_isvalid(periph_id));
|
||||
|
||||
internal_id = periph_id_to_internal_id[periph_id];
|
||||
assert(periphc_internal_id_isvalid(internal_id));
|
||||
|
||||
type = clock_periph_type[internal_id];
|
||||
assert(clock_type_id_isvalid(type));
|
||||
|
||||
*mux_bits = clock_source[type][CLOCK_MAX_MUX];
|
||||
|
||||
if (type == CLOCK_TYPE_PCMT16)
|
||||
*divider_bits = 16;
|
||||
else
|
||||
*divider_bits = 8;
|
||||
|
||||
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
|
||||
if (clock_source[type][mux] == parent)
|
||||
return mux;
|
||||
|
||||
/* if we get here, either us or the caller has made a mistake */
|
||||
printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
|
||||
parent);
|
||||
return -1;
|
||||
}
|
||||
|
||||
void clock_set_enable(enum periph_id periph_id, int enable)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
u32 *clk;
|
||||
u32 reg;
|
||||
|
||||
/* Enable/disable the clock to this peripheral */
|
||||
assert(clock_periph_id_isvalid(periph_id));
|
||||
if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
|
||||
clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
|
||||
else
|
||||
clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
|
||||
reg = readl(clk);
|
||||
if (enable)
|
||||
reg |= PERIPH_MASK(periph_id);
|
||||
else
|
||||
reg &= ~PERIPH_MASK(periph_id);
|
||||
writel(reg, clk);
|
||||
}
|
||||
|
||||
void reset_set_enable(enum periph_id periph_id, int enable)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
u32 *reset;
|
||||
u32 reg;
|
||||
|
||||
/* Enable/disable reset to the peripheral */
|
||||
assert(clock_periph_id_isvalid(periph_id));
|
||||
if (periph_id < PERIPH_ID_VW_FIRST)
|
||||
reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
|
||||
else
|
||||
reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
|
||||
reg = readl(reset);
|
||||
if (enable)
|
||||
reg |= PERIPH_MASK(periph_id);
|
||||
else
|
||||
reg &= ~PERIPH_MASK(periph_id);
|
||||
writel(reg, reset);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
/*
|
||||
* Convert a device tree clock ID to our peripheral ID. They are mostly
|
||||
* the same but we are very cautious so we check that a valid clock ID is
|
||||
* provided.
|
||||
*
|
||||
* @param clk_id Clock ID according to tegra114 device tree binding
|
||||
* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
|
||||
*/
|
||||
enum periph_id clk_id_to_periph_id(int clk_id)
|
||||
{
|
||||
if (clk_id > PERIPH_ID_COUNT)
|
||||
return PERIPH_ID_NONE;
|
||||
|
||||
switch (clk_id) {
|
||||
case PERIPH_ID_RESERVED3:
|
||||
case PERIPH_ID_RESERVED16:
|
||||
case PERIPH_ID_RESERVED24:
|
||||
case PERIPH_ID_RESERVED35:
|
||||
case PERIPH_ID_RESERVED43:
|
||||
case PERIPH_ID_RESERVED45:
|
||||
case PERIPH_ID_RESERVED56:
|
||||
case PERIPH_ID_RESERVED76:
|
||||
case PERIPH_ID_RESERVED77:
|
||||
case PERIPH_ID_RESERVED78:
|
||||
case PERIPH_ID_RESERVED83:
|
||||
case PERIPH_ID_RESERVED89:
|
||||
case PERIPH_ID_RESERVED91:
|
||||
case PERIPH_ID_RESERVED93:
|
||||
case PERIPH_ID_RESERVED94:
|
||||
case PERIPH_ID_RESERVED95:
|
||||
return PERIPH_ID_NONE;
|
||||
default:
|
||||
return clk_id;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_OF_CONTROL */
|
||||
|
||||
void clock_early_init(void)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
|
||||
/*
|
||||
* PLLP output frequency set to 408Mhz
|
||||
* PLLC output frequency set to 600Mhz
|
||||
* PLLD output frequency set to 925Mhz
|
||||
*/
|
||||
switch (clock_get_osc_freq()) {
|
||||
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
|
||||
clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
|
||||
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
|
||||
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
|
||||
break;
|
||||
|
||||
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
|
||||
clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
|
||||
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
|
||||
clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
|
||||
break;
|
||||
|
||||
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
|
||||
clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
|
||||
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
|
||||
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
|
||||
break;
|
||||
case CLOCK_OSC_FREQ_19_2:
|
||||
default:
|
||||
/*
|
||||
* These are not supported. It is too early to print a
|
||||
* message and the UART likely won't work anyway due to the
|
||||
* oscillator being wrong.
|
||||
*/
|
||||
break;
|
||||
}
|
||||
|
||||
/* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
|
||||
writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
|
||||
|
||||
/* PLLC_MISC: Set LOCK_ENABLE */
|
||||
writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
|
||||
udelay(2);
|
||||
|
||||
/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
|
||||
writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
|
||||
udelay(2);
|
||||
}
|
||||
63
arch/arm/cpu/tegra114-common/funcmux.c
Normal file
63
arch/arm/cpu/tegra114-common/funcmux.c
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Tegra114 high-level function multiplexing */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/funcmux.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
|
||||
int funcmux_select(enum periph_id id, int config)
|
||||
{
|
||||
int bad_config = config != FUNCMUX_DEFAULT;
|
||||
|
||||
switch (id) {
|
||||
case PERIPH_ID_UART4:
|
||||
switch (config) {
|
||||
case FUNCMUX_UART4_GMI:
|
||||
pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD);
|
||||
pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD);
|
||||
pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD);
|
||||
pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD);
|
||||
|
||||
pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT);
|
||||
pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT);
|
||||
pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT);
|
||||
pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT);
|
||||
|
||||
pinmux_tristate_disable(PINGRP_GMI_A16);
|
||||
pinmux_tristate_disable(PINGRP_GMI_A17);
|
||||
pinmux_tristate_disable(PINGRP_GMI_A18);
|
||||
pinmux_tristate_disable(PINGRP_GMI_A19);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
/* Add other periph IDs here as needed */
|
||||
|
||||
default:
|
||||
debug("%s: invalid periph_id %d", __func__, id);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (bad_config) {
|
||||
debug("%s: invalid config %d for periph_id %d", __func__,
|
||||
config, id);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
506
arch/arm/cpu/tegra114-common/pinmux.c
Normal file
506
arch/arm/cpu/tegra114-common/pinmux.c
Normal file
|
|
@ -0,0 +1,506 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Tegra114 pin multiplexing functions */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
|
||||
struct tegra_pingroup_desc {
|
||||
const char *name;
|
||||
enum pmux_func funcs[4];
|
||||
enum pmux_func func_safe;
|
||||
enum pmux_vddio vddio;
|
||||
enum pmux_pin_io io;
|
||||
};
|
||||
|
||||
#define PMUX_MUXCTL_SHIFT 0
|
||||
#define PMUX_PULL_SHIFT 2
|
||||
#define PMUX_TRISTATE_SHIFT 4
|
||||
#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
|
||||
#define PMUX_IO_SHIFT 5
|
||||
#define PMUX_OD_SHIFT 6
|
||||
#define PMUX_LOCK_SHIFT 7
|
||||
#define PMUX_IO_RESET_SHIFT 8
|
||||
|
||||
/* Convenient macro for defining pin group properties */
|
||||
#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
|
||||
{ \
|
||||
.vddio = PMUX_VDDIO_ ## vdd, \
|
||||
.funcs = { \
|
||||
PMUX_FUNC_ ## f0, \
|
||||
PMUX_FUNC_ ## f1, \
|
||||
PMUX_FUNC_ ## f2, \
|
||||
PMUX_FUNC_ ## f3, \
|
||||
}, \
|
||||
.func_safe = PMUX_FUNC_RSVD1, \
|
||||
.io = PMUX_PIN_ ## iod, \
|
||||
}
|
||||
|
||||
/* Input and output pins */
|
||||
#define PINI(pg_name, vdd, f0, f1, f2, f3) \
|
||||
PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
|
||||
#define PINO(pg_name, vdd, f0, f1, f2, f3) \
|
||||
PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
|
||||
|
||||
const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
|
||||
/* NAME VDD f0 f1 f2 f3 */
|
||||
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
|
||||
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
|
||||
PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
|
||||
PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
|
||||
PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
|
||||
PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
|
||||
PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
|
||||
PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
|
||||
PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
|
||||
PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
|
||||
PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
|
||||
PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
|
||||
PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
|
||||
PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
|
||||
PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
|
||||
PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
|
||||
PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
|
||||
PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
|
||||
PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
|
||||
PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
|
||||
PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
|
||||
PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
|
||||
PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
|
||||
PINI(GPIO_PV2, BB, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(GPIO_PV3, BB, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_PWR1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_PWR2, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_SDIN, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_SDOUT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_WR_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_CS0_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_DC0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_SCK, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_PWR0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_PCLK, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_DE, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D2, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D3, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D4, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D5, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D6, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D7, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D8, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D9, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D10, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D11, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D12, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D13, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D14, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D15, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D16, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D17, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D18, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D19, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D20, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D21, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D22, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_D23, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_CS1_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_M1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINO(LCD_DC1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
|
||||
PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CRT_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CRT_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D0, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D1, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D2, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D3, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D4, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D5, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D6, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D7, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D8, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D9, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D10, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_D11, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_PCLK, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_MCLK, VI, RSVD1, RSVD3, RSVD3, RSVD4),
|
||||
PINI(VI_VSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(VI_HSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
|
||||
PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
|
||||
PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
|
||||
PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
|
||||
PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
|
||||
PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
|
||||
PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
|
||||
PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
|
||||
PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
|
||||
PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
|
||||
PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
|
||||
PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
|
||||
PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
|
||||
PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
|
||||
PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
|
||||
PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
|
||||
PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
|
||||
PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
|
||||
PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
|
||||
PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
|
||||
PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
|
||||
PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
|
||||
PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
|
||||
PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
|
||||
PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
|
||||
PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
|
||||
PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
|
||||
PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
|
||||
PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
|
||||
PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
|
||||
PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
|
||||
PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
|
||||
PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
|
||||
PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
|
||||
PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
|
||||
PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
|
||||
PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
|
||||
PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
|
||||
PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
|
||||
PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
|
||||
PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
|
||||
PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
|
||||
PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
|
||||
PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
|
||||
PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
|
||||
PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
|
||||
PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
|
||||
PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
|
||||
PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
|
||||
PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
|
||||
PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
|
||||
PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
|
||||
PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
|
||||
PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
|
||||
PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
|
||||
PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
|
||||
PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
|
||||
PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
|
||||
PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
|
||||
PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
|
||||
PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
|
||||
PINI(SDMMC4_RST_N, SDMMC4, RSVD1, RSVD2, RSVD3, SDMMC4),
|
||||
PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4),
|
||||
PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
|
||||
PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
|
||||
PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
|
||||
PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
|
||||
PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
|
||||
PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
|
||||
PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
|
||||
PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
|
||||
PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
|
||||
PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
|
||||
PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
|
||||
PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
|
||||
PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
|
||||
PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
|
||||
PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
|
||||
PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
|
||||
PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
|
||||
PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
|
||||
PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
|
||||
PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
|
||||
PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
|
||||
PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
|
||||
PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
|
||||
PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
|
||||
PINI(KB_ROW11, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(KB_ROW12, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(KB_ROW13, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(KB_ROW14, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(KB_ROW15, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
|
||||
PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
|
||||
PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
|
||||
PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
|
||||
PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
|
||||
PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
|
||||
PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
|
||||
PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
|
||||
PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
|
||||
PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
|
||||
PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
|
||||
PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
|
||||
PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
|
||||
PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
|
||||
PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
|
||||
PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
|
||||
PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
|
||||
PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
|
||||
PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
|
||||
PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
|
||||
PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
|
||||
PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
|
||||
PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
|
||||
PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
|
||||
PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
|
||||
PINI(SPI2_MOSI, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
|
||||
PINI(SPI2_MISO, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SPI2_CS0_N, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
|
||||
PINI(SPI2_SCK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
|
||||
PINI(SPI1_MOSI, AUDIO, RSVD1, SPI1, SPI2, DAP2),
|
||||
PINI(SPI1_SCK, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
|
||||
PINI(SPI1_CS0_N, AUDIO, SPI6, SPI1, SPI2, RSVD4),
|
||||
PINI(SPI1_MISO, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
|
||||
PINI(SPI2_CS1_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SPI2_CS2_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
|
||||
PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
|
||||
PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
|
||||
PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
|
||||
PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
|
||||
PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
|
||||
PINI(SDMMC3_DAT4, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SDMMC3_DAT5, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SDMMC3_DAT6, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SDMMC3_DAT7, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
|
||||
PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
|
||||
PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
|
||||
PINI(SDMMC3_CD_N, SDMMC3, SDMMC3, OWR, RSVD3, RSVD4),
|
||||
PINI(SPI1_CS1_N, AUDIO, SPI6, RSVD2, SPI2, I2C1),
|
||||
PINI(SPI1_CS2_N, AUDIO, SPI6, SPI1, SPI2, I2C1),
|
||||
PINI(USB_VBUS_EN0, SYS, USB, RSVD2, RSVD3, RSVD4),
|
||||
PINI(USB_VBUS_EN1, SYS, USB, RSVD2, RSVD3, RSVD4),
|
||||
PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
|
||||
PINO(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
|
||||
PINO(NAND_GMI_CLK_LB, GMI, SDMMC2, NAND, GMI, RSVD4),
|
||||
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
|
||||
};
|
||||
|
||||
void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
u32 *tri = &pmt->pmt_ctl[pin];
|
||||
u32 reg;
|
||||
|
||||
/* Error check on pin */
|
||||
assert(pmux_pingrp_isvalid(pin));
|
||||
|
||||
reg = readl(tri);
|
||||
if (enable)
|
||||
reg |= PMUX_TRISTATE_MASK;
|
||||
else
|
||||
reg &= ~PMUX_TRISTATE_MASK;
|
||||
writel(reg, tri);
|
||||
}
|
||||
|
||||
void pinmux_tristate_enable(enum pmux_pingrp pin)
|
||||
{
|
||||
pinmux_set_tristate(pin, 1);
|
||||
}
|
||||
|
||||
void pinmux_tristate_disable(enum pmux_pingrp pin)
|
||||
{
|
||||
pinmux_set_tristate(pin, 0);
|
||||
}
|
||||
|
||||
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
u32 *pull = &pmt->pmt_ctl[pin];
|
||||
u32 reg;
|
||||
|
||||
/* Error check on pin and pupd */
|
||||
assert(pmux_pingrp_isvalid(pin));
|
||||
assert(pmux_pin_pupd_isvalid(pupd));
|
||||
|
||||
reg = readl(pull);
|
||||
reg &= ~(0x3 << PMUX_PULL_SHIFT);
|
||||
reg |= (pupd << PMUX_PULL_SHIFT);
|
||||
writel(reg, pull);
|
||||
}
|
||||
|
||||
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
u32 *muxctl = &pmt->pmt_ctl[pin];
|
||||
int i, mux = -1;
|
||||
u32 reg;
|
||||
|
||||
/* Error check on pin and func */
|
||||
assert(pmux_pingrp_isvalid(pin));
|
||||
assert(pmux_func_isvalid(func));
|
||||
|
||||
/* Handle special values */
|
||||
if (func == PMUX_FUNC_SAFE)
|
||||
func = tegra_soc_pingroups[pin].func_safe;
|
||||
|
||||
if (func & PMUX_FUNC_RSVD1) {
|
||||
mux = func & 0x3;
|
||||
} else {
|
||||
/* Search for the appropriate function */
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (tegra_soc_pingroups[pin].funcs[i] == func) {
|
||||
mux = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
assert(mux != -1);
|
||||
|
||||
reg = readl(muxctl);
|
||||
reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
|
||||
reg |= (mux << PMUX_MUXCTL_SHIFT);
|
||||
writel(reg, muxctl);
|
||||
|
||||
}
|
||||
|
||||
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
u32 *pin_io = &pmt->pmt_ctl[pin];
|
||||
u32 reg;
|
||||
|
||||
/* Error check on pin and io */
|
||||
assert(pmux_pingrp_isvalid(pin));
|
||||
assert(pmux_pin_io_isvalid(io));
|
||||
|
||||
reg = readl(pin_io);
|
||||
reg &= ~(0x1 << PMUX_IO_SHIFT);
|
||||
reg |= (io & 0x1) << PMUX_IO_SHIFT;
|
||||
writel(reg, pin_io);
|
||||
}
|
||||
|
||||
static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
u32 *pin_lock = &pmt->pmt_ctl[pin];
|
||||
u32 reg;
|
||||
|
||||
/* Error check on pin and lock */
|
||||
assert(pmux_pingrp_isvalid(pin));
|
||||
assert(pmux_pin_lock_isvalid(lock));
|
||||
|
||||
if (lock == PMUX_PIN_LOCK_DEFAULT)
|
||||
return 0;
|
||||
|
||||
reg = readl(pin_lock);
|
||||
reg &= ~(0x1 << PMUX_LOCK_SHIFT);
|
||||
if (lock == PMUX_PIN_LOCK_ENABLE)
|
||||
reg |= (0x1 << PMUX_LOCK_SHIFT);
|
||||
else {
|
||||
/* lock == DISABLE, which isn't possible */
|
||||
printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
|
||||
__func__, lock);
|
||||
}
|
||||
writel(reg, pin_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
u32 *pin_od = &pmt->pmt_ctl[pin];
|
||||
u32 reg;
|
||||
|
||||
/* Error check on pin and od */
|
||||
assert(pmux_pingrp_isvalid(pin));
|
||||
assert(pmux_pin_od_isvalid(od));
|
||||
|
||||
if (od == PMUX_PIN_OD_DEFAULT)
|
||||
return 0;
|
||||
|
||||
reg = readl(pin_od);
|
||||
reg &= ~(0x1 << PMUX_OD_SHIFT);
|
||||
if (od == PMUX_PIN_OD_ENABLE)
|
||||
reg |= (0x1 << PMUX_OD_SHIFT);
|
||||
writel(reg, pin_od);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pinmux_set_ioreset(enum pmux_pingrp pin,
|
||||
enum pmux_pin_ioreset ioreset)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt =
|
||||
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
u32 *pin_ioreset = &pmt->pmt_ctl[pin];
|
||||
u32 reg;
|
||||
|
||||
/* Error check on pin and ioreset */
|
||||
assert(pmux_pingrp_isvalid(pin));
|
||||
assert(pmux_pin_ioreset_isvalid(ioreset));
|
||||
|
||||
if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
|
||||
return 0;
|
||||
|
||||
reg = readl(pin_ioreset);
|
||||
reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
|
||||
if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
|
||||
reg |= (0x1 << PMUX_IO_RESET_SHIFT);
|
||||
writel(reg, pin_ioreset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pinmux_config_pingroup(struct pingroup_config *config)
|
||||
{
|
||||
enum pmux_pingrp pin = config->pingroup;
|
||||
|
||||
pinmux_set_func(pin, config->func);
|
||||
pinmux_set_pullupdown(pin, config->pull);
|
||||
pinmux_set_tristate(pin, config->tristate);
|
||||
pinmux_set_io(pin, config->io);
|
||||
pinmux_set_lock(pin, config->lock);
|
||||
pinmux_set_od(pin, config->od);
|
||||
pinmux_set_ioreset(pin, config->ioreset);
|
||||
}
|
||||
|
||||
void pinmux_config_table(struct pingroup_config *config, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
pinmux_config_pingroup(&config[i]);
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue