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gw_ventana: Move the DCD settings to spl code
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR. Move the configuration to the spl code. CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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3 changed files with 28 additions and 48 deletions
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@ -1,42 +0,0 @@
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2013 Gateworks Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* set the default clock gate to save power */
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DATA 4, CCM_CCGR0, 0x00C03F3F
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DATA 4, CCM_CCGR1, 0x0030FC03
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DATA 4, CCM_CCGR2, 0x0FFFC000
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DATA 4, CCM_CCGR3, 0x3FF00000
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DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
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DATA 4, CCM_CCGR5, 0x0F0000C3
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DATA 4, CCM_CCGR6, 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
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DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
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/*
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* Setup CCM_CCOSR register as follows:
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*
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* cko1_en = 1 --> CKO1 enabled
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* cko1_div = 111 --> divide by 8
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* cko1_sel = 1011 --> ahb_clk_root
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*
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* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
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*/
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DATA 4, CCM_CCOSR, 0x000000fb
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@ -21,9 +21,3 @@ BOOT_FROM spi
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#else
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#else
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BOOT_FROM nand
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BOOT_FROM nand
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#endif
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#endif
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#define __ASSEMBLY__
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#include <config.h>
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#include "asm/arch/iomux.h"
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#include "asm/arch/crm_regs.h"
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#include "clocks.cfg"
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@ -8,6 +8,7 @@
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#include <common.h>
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#include <common.h>
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#include <i2c.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/mx6-pins.h>
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@ -392,6 +393,30 @@ static void spl_dram_init(int width, int size_mb, int board_model)
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mx6_dram_cfg(&sysinfo, calib, mem);
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mx6_dram_cfg(&sysinfo, calib, mem);
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}
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}
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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static void gpr_init(void)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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/* enable AXI cache for VDOA/VPU/IPU */
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writel(0xF00000CF, &iomux->gpr[4]);
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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writel(0x007F007F, &iomux->gpr[6]);
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writel(0x007F007F, &iomux->gpr[7]);
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}
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/*
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/*
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* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
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* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
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* - we have a stack and a place to store GD, both in SRAM
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* - we have a stack and a place to store GD, both in SRAM
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@ -405,6 +430,9 @@ void board_init_f(ulong dummy)
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/* setup AIPS and disable watchdog */
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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arch_cpu_init();
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ccgr_init();
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gpr_init();
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/* iomux and setup of i2c */
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/* iomux and setup of i2c */
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board_early_init_f();
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board_early_init_f();
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i2c_setup_iomux();
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i2c_setup_iomux();
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