mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 06:31:31 +00:00
Xilinx/FPGA changes for v2020.01 part 2
common: - Fix manual relocation for repeatable commands arm: - Also clean up generated dtbos microblaze: - Add support for Manual relocation in crypto framework - Tune and align architecture bootm support zynq: - DT sync ups - Some defconfig updates - Remove empty board_early_init_f() zynqmp: - Clean firmware handing via drivers/firmware/ - DT/defconfig name alignments - DT cleanups with using firmware based clock driver - Some defconfig updates - Add IIO ina226 DT description - Tune zynqmp_psu_init_minimalize.sh script - Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216 versal: - Clean firmware handing via drivers/firmware/ - Add gpio support - Enable DT overlay/USB/CLK/FPGA - DT updates - Tune mini configuration spi: - gqspi - Remove unused headers -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXbKa4QAKCRDKSWXLKUoM ISzJAJ0YpGS7HziGFVRBlcsyRH8QlWCqOQCfb0jIWzhL8pvj9TA01CdU0Axdbwk= =GIpp -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2020.01-part2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 part 2 common: - Fix manual relocation for repeatable commands arm: - Also clean up generated dtbos microblaze: - Add support for Manual relocation in crypto framework - Tune and align architecture bootm support zynq: - DT sync ups - Some defconfig updates - Remove empty board_early_init_f() zynqmp: - Clean firmware handing via drivers/firmware/ - DT/defconfig name alignments - DT cleanups with using firmware based clock driver - Some defconfig updates - Add IIO ina226 DT description - Tune zynqmp_psu_init_minimalize.sh script - Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216 versal: - Clean firmware handing via drivers/firmware/ - Add gpio support - Enable DT overlay/USB/CLK/FPGA - DT updates - Tune mini configuration spi: - gqspi - Remove unused headers
This commit is contained in:
Tom Rini
commit
e382713d22
97 changed files with 4079 additions and 481 deletions
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@ -1008,7 +1008,6 @@ config ARCH_VF610
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config ARCH_ZYNQ
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bool "Xilinx Zynq based platform"
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select BOARD_EARLY_INIT_F if WDT
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select CLK
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select CLK_ZYNQ
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select CPU_V7A
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@ -250,9 +250,12 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
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avnet-ultra96-rev1.dtb \
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avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
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zynqmp-a2197-revA.dtb \
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zynqmp-a2197-g-revA.dtb \
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zynqmp-a2197-m-revA.dtb \
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zynqmp-a2197-p-revA.dtb \
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zynqmp-e-a2197-00-revA.dtb \
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zynqmp-g-a2197-00-revA.dtb \
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zynqmp-m-a2197-01-revA.dtb \
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zynqmp-m-a2197-02-revA.dtb \
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zynqmp-m-a2197-03-revA.dtb \
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zynqmp-p-a2197-00-revA.dtb \
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zynqmp-mini.dtb \
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zynqmp-mini-emmc0.dtb \
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zynqmp-mini-emmc1.dtb \
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@ -268,6 +271,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
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zynqmp-zcu111-revA.dtb \
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zynqmp-zcu1275-revA.dtb \
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zynqmp-zcu1275-revB.dtb \
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zynqmp-zcu216-revA.dtb \
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zynqmp-zc1232-revA.dtb \
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zynqmp-zc1254-revA.dtb \
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zynqmp-zc1751-xm015-dc1.dtb \
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@ -833,4 +837,4 @@ PHONY += dtbs
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dtbs: $(addprefix $(obj)/, $(dtb-y))
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@:
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clean-files := *.dtb *_HS
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clean-files := *.dtb *.dtbo *_HS
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@ -35,7 +35,7 @@
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#size-cells = <0x2>;
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ranges;
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sdhci1: sdhci@f105000 {
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sdhci1: sdhci@f1050000 {
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compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
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status = "okay";
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reg = <0x0 0xf1050000 0x0 0x10000>;
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@ -213,6 +213,33 @@
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#size-cells = <0>;
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};
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smcc: memory-controller@e000e000 {
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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clock-names = "memclk", "apb_pclk";
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clocks = <&clkc 11>, <&clkc 44>;
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compatible = "arm,pl353-smc-r2p1", "arm,primecell";
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interrupt-parent = <&intc>;
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interrupts = <0 18 4>;
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ranges ;
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reg = <0xe000e000 0x1000>;
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nand0: flash@e1000000 {
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status = "disabled";
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compatible = "arm,pl353-nand-r2p1";
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reg = <0xe1000000 0x1000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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nor0: flash@e2000000 {
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status = "disabled";
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compatible = "cfi-flash";
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reg = <0xe2000000 0x2000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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gem0: ethernet@e000b000 {
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compatible = "cdns,zynq-gem", "cdns,gem";
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reg = <0xe000b000 0x1000>;
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@ -7,29 +7,30 @@
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
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/ {
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fclk0: fclk0 {
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status = "disabled";
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status = "okay";
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compatible = "xlnx,fclk";
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clocks = <&clkc 71>;
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clocks = <&zynqmp_clk PL0_REF>;
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};
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fclk1: fclk1 {
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status = "disabled";
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status = "okay";
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compatible = "xlnx,fclk";
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clocks = <&clkc 72>;
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clocks = <&zynqmp_clk PL1_REF>;
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};
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fclk2: fclk2 {
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status = "disabled";
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status = "okay";
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compatible = "xlnx,fclk";
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clocks = <&clkc 73>;
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clocks = <&zynqmp_clk PL2_REF>;
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};
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fclk3: fclk3 {
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status = "disabled";
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status = "okay";
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compatible = "xlnx,fclk";
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clocks = <&clkc 74>;
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clocks = <&zynqmp_clk PL3_REF>;
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};
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pss_ref_clk: pss_ref_clk {
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@ -67,35 +68,6 @@
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clock-frequency = <27000000>;
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};
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clkc: clkc {
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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compatible = "xlnx,zynqmp-clkc";
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clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
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clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
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clock-output-names = "iopll", "rpll", "apll", "dpll",
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"vpll", "iopll_to_fpd", "rpll_to_fpd",
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"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
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"acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
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"dbg_trace", "dbg_tstmp", "dp_video_ref",
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"dp_audio_ref", "dp_stc_ref", "gdma_ref",
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"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
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"gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
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"topsw_main", "topsw_lsbus", "gtgref0_ref",
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"lpd_switch", "lpd_lsbus", "usb0_bus_ref",
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"usb1_bus_ref", "usb3_dual_ref", "usb0",
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"usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
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"csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
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"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
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"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
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"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
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"uart0_ref", "uart1_ref", "spi0_ref",
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"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
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"can0_ref", "can1_ref", "can0", "can1",
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"dll_ref", "adma_ref", "timestamp_ref",
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"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
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};
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dp_aclk: dp_aclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@ -104,202 +76,214 @@
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};
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};
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&zynqmp_firmware {
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zynqmp_clk: clock-controller {
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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compatible = "xlnx,zynqmp-clk";
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clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
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<&aux_ref_clk>, <>_crx_ref_clk>;
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clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
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"aux_ref_clk", "gt_crx_ref_clk";
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};
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};
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&can0 {
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clocks = <&clkc 63>, <&clkc 31>;
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clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&can1 {
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clocks = <&clkc 64>, <&clkc 31>;
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clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&cpu0 {
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clocks = <&clkc 10>;
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clocks = <&zynqmp_clk ACPU>;
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};
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&fpd_dma_chan1 {
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clocks = <&clkc 19>, <&clkc 31>;
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan2 {
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clocks = <&clkc 19>, <&clkc 31>;
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan3 {
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clocks = <&clkc 19>, <&clkc 31>;
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan4 {
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clocks = <&clkc 19>, <&clkc 31>;
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan5 {
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clocks = <&clkc 19>, <&clkc 31>;
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan6 {
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clocks = <&clkc 19>, <&clkc 31>;
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan7 {
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clocks = <&clkc 19>, <&clkc 31>;
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&fpd_dma_chan8 {
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clocks = <&clkc 19>, <&clkc 31>;
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clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&gpu {
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clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;
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clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
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};
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&lpd_dma_chan1 {
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clocks = <&clkc 68>, <&clkc 31>;
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&lpd_dma_chan2 {
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clocks = <&clkc 68>, <&clkc 31>;
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&lpd_dma_chan3 {
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clocks = <&clkc 68>, <&clkc 31>;
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&lpd_dma_chan4 {
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clocks = <&clkc 68>, <&clkc 31>;
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&lpd_dma_chan5 {
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clocks = <&clkc 68>, <&clkc 31>;
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&lpd_dma_chan6 {
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clocks = <&clkc 68>, <&clkc 31>;
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&lpd_dma_chan7 {
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clocks = <&clkc 68>, <&clkc 31>;
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&lpd_dma_chan8 {
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clocks = <&clkc 68>, <&clkc 31>;
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clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&nand0 {
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clocks = <&clkc 60>, <&clkc 31>;
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clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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&gem0 {
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clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>;
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>,
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<&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gem1 {
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clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>;
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>,
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<&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gem2 {
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clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>;
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>,
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<&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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&gem3 {
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clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>;
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clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>,
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<&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>;
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clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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};
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|
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&gpio {
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clocks = <&clkc 31>;
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clocks = <&zynqmp_clk LPD_LSBUS>;
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};
|
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|
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&i2c0 {
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clocks = <&clkc 61>;
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clocks = <&zynqmp_clk I2C0_REF>;
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};
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&i2c1 {
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clocks = <&clkc 62>;
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clocks = <&zynqmp_clk I2C1_REF>;
|
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};
|
||||
|
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&pcie {
|
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clocks = <&clkc 23>;
|
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clocks = <&zynqmp_clk PCIE_REF>;
|
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};
|
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|
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&qspi {
|
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clocks = <&clkc 53>, <&clkc 31>;
|
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clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&sata {
|
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clocks = <&clkc 22>;
|
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clocks = <&zynqmp_clk SATA_REF>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
clocks = <&clkc 54>, <&clkc 31>;
|
||||
clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
clocks = <&clkc 55>, <&clkc 31>;
|
||||
clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
clocks = <&clkc 58>, <&clkc 31>;
|
||||
clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
clocks = <&clkc 59>, <&clkc 31>;
|
||||
clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&ttc0 {
|
||||
clocks = <&clkc 31>;
|
||||
clocks = <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&ttc1 {
|
||||
clocks = <&clkc 31>;
|
||||
clocks = <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&ttc2 {
|
||||
clocks = <&clkc 31>;
|
||||
clocks = <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&ttc3 {
|
||||
clocks = <&clkc 31>;
|
||||
clocks = <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clocks = <&clkc 56>, <&clkc 31>;
|
||||
clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
clocks = <&clkc 57>, <&clkc 31>;
|
||||
clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
clocks = <&clkc 32>, <&clkc 34>;
|
||||
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
clocks = <&clkc 33>, <&clkc 34>;
|
||||
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
clocks = <&clkc 75>;
|
||||
clocks = <&zynqmp_clk WDT>;
|
||||
};
|
||||
|
||||
&lpd_watchdog {
|
||||
clocks = <&zynqmp_clk LPD_WDT>;
|
||||
};
|
||||
|
||||
&xilinx_ams {
|
||||
clocks = <&clkc 70>;
|
||||
};
|
||||
|
||||
&xilinx_drm {
|
||||
clocks = <&clkc 16>;
|
||||
};
|
||||
|
||||
&xlnx_dp {
|
||||
clocks = <&dp_aclk>, <&clkc 17>;
|
||||
clocks = <&zynqmp_clk AMS_REF>;
|
||||
};
|
||||
|
||||
&xlnx_dpdma {
|
||||
clocks = <&clkc 20>;
|
||||
clocks = <&zynqmp_clk DPDMA_REF>;
|
||||
};
|
||||
|
||||
&xlnx_dp_snd_codec0 {
|
||||
clocks = <&clkc 17>;
|
||||
clocks = <&zynqmp_clk DP_AUDIO_REF>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -223,6 +223,10 @@
|
|||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&lpd_watchdog {
|
||||
clocks = <&clk250>;
|
||||
};
|
||||
|
||||
&xilinx_drm {
|
||||
clocks = <&drm_clock>;
|
||||
};
|
||||
|
|
|
|||
559
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
Normal file
559
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
Normal file
|
|
@ -0,0 +1,559 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx Versal a2197 RevA System Controller
|
||||
*
|
||||
* (C) Copyright 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
|
||||
compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
|
||||
"xlnx,zynqmp-a2197", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem0;
|
||||
gpio0 = &gpio;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &dcc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
xlnx,eeprom = <&eeprom>;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ina226-vccint {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
|
||||
};
|
||||
ina226-vcc-soc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
|
||||
};
|
||||
ina226-vcc-pmc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
|
||||
};
|
||||
ina226-vcc-ram {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
|
||||
};
|
||||
ina226-vcc-pslp {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
|
||||
};
|
||||
ina226-vcc-psfp {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
|
||||
};
|
||||
ina226-vccaux {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
|
||||
};
|
||||
ina226-vccaux-pmc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
|
||||
};
|
||||
ina226-vcco-500 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
|
||||
};
|
||||
ina226-vcco-501 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
|
||||
};
|
||||
ina226-vcco-502 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
|
||||
};
|
||||
ina226-vcco-503 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
|
||||
};
|
||||
ina226-vcc-1v8 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
|
||||
};
|
||||
ina226-vcc-3v3 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
|
||||
};
|
||||
ina226-vcc-1v2-ddr4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
|
||||
};
|
||||
ina226-vcc-1v1-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
|
||||
};
|
||||
ina226-vadj-fmc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
|
||||
};
|
||||
ina226-mgtyavcc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
|
||||
};
|
||||
ina226-mgtyavtt {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
|
||||
};
|
||||
ina226-mgtyvccaux {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 { /* uart0 MIO38-39 */
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&sdhci1 { /* sd1 MIO45-51 cd in place */
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
is-internal-pcspma;
|
||||
phy0: ethernet-phy@0 { /* u131 M88E1512 */
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
gpio-line-names = "", "", "", "", "", /* 0 - 4 */
|
||||
"", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
|
||||
"DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
|
||||
"", "", "", "", "", /* 15 - 19 */
|
||||
"", "", "", "", "", /* 20 - 24 */
|
||||
"", "", "", "", "", /* 25 - 29 */
|
||||
"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
|
||||
"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
|
||||
"", "", "ETH_RESET_B", "", "", /* 40 - 44 */
|
||||
"SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
|
||||
"SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
|
||||
"", "", "", "", "", /* 55 - 59 */
|
||||
"", "", "", "", "", /* 60 - 64 */
|
||||
"", "", "", "", "", /* 65 - 69 */
|
||||
"", "", "", "", "", /* 70 - 74 */
|
||||
"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
|
||||
"", "", /* 78 - 79 */
|
||||
"", "", "", "", "", /* 80 - 84 */
|
||||
"", "", "", "", "", /* 85 -89 */
|
||||
"", "", "", "", "", /* 90 - 94 */
|
||||
"", "", "", "", "", /* 95 - 99 */
|
||||
"", "", "", "", "", /* 100 - 104 */
|
||||
"", "", "", "", "", /* 105 - 109 */
|
||||
"", "", "", "", "", /* 110 - 114 */
|
||||
"", "", "", "", "", /* 115 - 119 */
|
||||
"", "", "", "", "", /* 120 - 124 */
|
||||
"", "", "", "", "", /* 125 - 129 */
|
||||
"", "", "", "", "", /* 130 - 134 */
|
||||
"", "", "", "", "", /* 135 - 139 */
|
||||
"", "", "", "", "", /* 140 - 144 */
|
||||
"", "", "", "", "", /* 145 - 149 */
|
||||
"", "", "", "", "", /* 150 - 154 */
|
||||
"", "", "", "", "", /* 155 - 159 */
|
||||
"", "", "", "", "", /* 160 - 164 */
|
||||
"", "", "", "", "", /* 165 - 169 */
|
||||
"", "", "", ""; /* 170 - 174 */
|
||||
};
|
||||
|
||||
&i2c0 { /* MIO 34-35 - can't stay here */
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
i2c-mux@74 { /* u33 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
i2c@0 { /* PMBUS */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* u152 IR35215 0x16/0x46 vcc_soc */
|
||||
/* u160 IRPS5401 0x17/0x47 */
|
||||
/* u167 IRPS5401 0x1c/0x4c */
|
||||
/* u175 IRPS5401 0x1d/0x4d */
|
||||
/* u179 ir38164 0x19/0x49 vcco_500 */
|
||||
/* u181 ir38164 0x1a/0x4a vcco_501 */
|
||||
/* u183 ir38164 0x1b/0x4b vcco_502 */
|
||||
/* u185 ir38164 0x1e/0x4e vadj_fmc */
|
||||
/* u187 ir38164 0x1F/0x4f mgtyavcc */
|
||||
/* u189 ir38164 0x20/0x50 mgtyavtt */
|
||||
/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
|
||||
/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
|
||||
};
|
||||
i2c@1 { /* PMBUS1_INA226 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* FIXME check alerts coming to SC */
|
||||
vccint: ina226@40 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccint";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>; /* R440 */
|
||||
/* 0.78V @ 32A 1 of 6 Phases*/
|
||||
};
|
||||
vcc_soc: ina226@41 { /* u161 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-soc";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <2000>; /* R1186 */
|
||||
/* 0.78V @ 18A */
|
||||
};
|
||||
vcc_pmc: ina226@42 { /* u163 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-pmc";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>; /* R1214 */
|
||||
/* 0.78V @ 500mA */
|
||||
};
|
||||
vcc_ram: ina226@43 { /* u162 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-ram";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>; /* r1221 */
|
||||
/* 0.78V @ 4A */
|
||||
};
|
||||
vcc_pslp: ina226@44 { /* u165 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-pslp";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>; /* R1216 */
|
||||
/* 0.78V @ 1A */
|
||||
};
|
||||
vcc_psfp: ina226@45 { /* u164 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-psfp";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>; /* R1219 */
|
||||
/* 0.78V @ 2A */
|
||||
};
|
||||
};
|
||||
i2c@2 { /* PCIE_CLK */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */
|
||||
#clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
|
||||
compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
|
||||
reg = <0xd8>;
|
||||
/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
|
||||
/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
|
||||
};
|
||||
};
|
||||
i2c@3 { /* PMBUS2_INA226 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* FIXME check alerts coming to SC */
|
||||
vccaux: ina226@40 { /* u166 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccaux";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>; /* R382 */
|
||||
/* 1.5V @ 3A */
|
||||
};
|
||||
vccaux_pmc: ina226@41 { /* u168 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccaux-pmc";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>; /* R1246 */
|
||||
/* 1.5V @ 500mA */
|
||||
};
|
||||
vcco_500: ina226@42 { /* u178 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcco-500";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <2000>; /* R1300 */
|
||||
/* 3.3V @ 5A */
|
||||
};
|
||||
vcco_501: ina226@43 { /* u180 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcco-501";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <2000>; /* R1313 */
|
||||
/* 3.3V @ 5A */
|
||||
};
|
||||
vcco_502: ina226@44 { /* u182 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcco-502";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <2000>; /* R1330 */
|
||||
/* 3.3V @ 5A */
|
||||
};
|
||||
vcco_503: ina226@45 { /* u172 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcco-503";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>; /* R1229 */
|
||||
/* 1.8V @ 2A */
|
||||
};
|
||||
vcc_1v8: ina226@46 { /* u173 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-1v8";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>; /* R400 */
|
||||
/* 1.8V @ 6A */
|
||||
};
|
||||
vcc_3v3: ina226@47 { /* u174 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-3v3";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>; /* R1232 */
|
||||
/* 3.3V @ 500mA */
|
||||
};
|
||||
vcc_1v2_ddr4: ina226@48 { /* u176 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-1v2-ddr4";
|
||||
reg = <0x48>;
|
||||
shunt-resistor = <5000>; /* R1275 */
|
||||
/* 1.2V @ 4A */
|
||||
};
|
||||
vcc1v1_lp4: ina226@49 { /* u177 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v1-lp4";
|
||||
reg = <0x49>;
|
||||
shunt-resistor = <5000>; /* R1286 */
|
||||
/* 1.1V @ 4A */
|
||||
};
|
||||
vadj_fmc: ina226@4a { /* u184 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vadj-fmc";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <2000>; /* R1350 */
|
||||
/* 1.5V @ 10A */
|
||||
};
|
||||
mgtyavcc: ina226@4b { /* u186 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-mgtyavcc";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <2000>; /* R1367 */
|
||||
/* 0.88V @ 6A */
|
||||
};
|
||||
mgtyavtt: ina226@4c { /* u188 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-mgtyavtt";
|
||||
reg = <0x4c>;
|
||||
shunt-resistor = <2000>; /* R1384 */
|
||||
/* 1.2V @ 10A */
|
||||
};
|
||||
mgtyvccaux: ina226@4d { /* u234 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-mgtyvccaux";
|
||||
reg = <0x4d>;
|
||||
shunt-resistor = <5000>; /* r1679 */
|
||||
/* 1.5V @ 500mA */
|
||||
};
|
||||
};
|
||||
i2c@4 { /* LP_I2C_SM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* FIXME wires ready but chip is missing */
|
||||
};
|
||||
i2c@5 { /* zSFP_SI570 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
si570_zsfp: clock-generator@5d { /* u192 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <156250000>;
|
||||
clock-output-names = "si570_hsdp_clk";
|
||||
};
|
||||
};
|
||||
i2c@6 { /* USER_SI570_1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
si570_user1_clk: clock-generator@5d { /* u205 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5f>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <100000000>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "si570_user1";
|
||||
};
|
||||
|
||||
};
|
||||
i2c@7 { /* USER_SI570_2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
/* FIXME wires ready but chip is missing */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 { /* i2c1 MIO 36-37 */
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
i2c-mux@74 { /* u35 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
dc_i2c: i2c@0 { /* DC_I2C */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* Use for storing information about SC board */
|
||||
eeprom: eeprom@54 { /* u34 - m24128 16kB */
|
||||
compatible = "st,24c128", "atmel,24c128";
|
||||
reg = <0x54>; /* 0x5c too */
|
||||
};
|
||||
si570_ref_clk: clock-generator@5d { /* u32 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <33333333>;
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "ref_clk";
|
||||
};
|
||||
/* and connector J212D */
|
||||
};
|
||||
fmc1: i2c@1 { /* FMCP1_IIC */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* FIXME connection to Samtec J51C */
|
||||
/* expected eeprom 0x50 FMC cards */
|
||||
};
|
||||
fmc2: i2c@2 { /* FMCP2_IIC */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* FIXME connection to Samtec J53C */
|
||||
/* expected eeprom 0x50 FMC cards */
|
||||
};
|
||||
i2c@3 { /* DDR4_DIMM1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
si570_ddr_dimm1: clock-generator@60 { /* u2 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x60>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <200000000>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "si570_ddrdimm1_clk";
|
||||
};
|
||||
};
|
||||
i2c@4 { /* LPDDR4_SI570_CLK2 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
si570_ddr_dimm2: clock-generator@60 { /* u3 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x60>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <200000000>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "si570_lpddr4_clk2";
|
||||
};
|
||||
};
|
||||
i2c@5 { /* LPDDR4_SI570_CLK1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
si570_lpddr4: clock-generator@60 { /* u4 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x60>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <200000000>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "si570_lpddr4_clk1";
|
||||
};
|
||||
};
|
||||
i2c@6 { /* HSDP_SI570 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
si570_hsdp: clock-generator@5d { /* u5 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <156250000>;
|
||||
clock-output-names = "si570_hsdp_clk";
|
||||
};
|
||||
};
|
||||
i2c@7 { /* 8A34001 - U219B and J310 connector */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&xilinx_ams {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ams_pl {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
/ {
|
||||
model = "Versal System Controller on a2197 MGT Char board RevA";
|
||||
compatible = "xlnx,zynqmp-a2197-g-revA", "xlnx,zynqmp-a2197-revA",
|
||||
compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
|
||||
"xlnx,zynqmp-a2197", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
|
|
@ -38,6 +38,31 @@
|
|||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ina226-u74 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
|
||||
};
|
||||
ina226-u75 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
|
||||
};
|
||||
ina226-u78 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
|
||||
};
|
||||
ina226-u79 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
|
||||
};
|
||||
ina226-u82 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>;
|
||||
};
|
||||
ina226-u84 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 { /* emmc MIO 13-23 16GB */
|
||||
|
|
@ -58,7 +83,7 @@
|
|||
phy-handle = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
is-internal-pcspma;
|
||||
phy0: phy@0 { /* marwell m88e1512 */
|
||||
phy0: ethernet-phy@0 { /* marwell m88e1512 */
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
|
||||
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
|
||||
|
|
@ -198,38 +223,50 @@
|
|||
compatible = "ti,tps544b25";
|
||||
reg = <0x20>;
|
||||
};
|
||||
ina226@40 { /* u74 */
|
||||
u74: ina226@40 { /* u74 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u74";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
ina226@41 { /* u75 */
|
||||
u75: ina226@41 { /* u75 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u75";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
ina226@42 { /* u78 */
|
||||
u78: ina226@42 { /* u78 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u78";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u79 */
|
||||
u79: ina226@43 { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u79";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
ina226@44 { /* u82 */
|
||||
u82: ina226@44 { /* u82 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u82";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
ina226@45 { /* u84 */
|
||||
u84: ina226@45 { /* u84 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u84";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */
|
||||
compatible = "ti,tps53681"; /* FIXME no linux driver */
|
||||
compatible = "ti,tps53681", "ti,tps53679";
|
||||
reg = <0xc0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
/ {
|
||||
model = "Versal System Controller on a2197 Memory Char board RevA";
|
||||
compatible = "xlnx,zynqmp-a2197-m-revA", "xlnx,zynqmp-a2197-revA",
|
||||
compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA",
|
||||
"xlnx,zynqmp-a2197", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
|
|
@ -43,13 +43,38 @@
|
|||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
|
||||
};
|
||||
|
||||
ina226-vcc-aux {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
|
||||
};
|
||||
ina226-vcc-ram {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
|
||||
};
|
||||
ina226-vcc1v1-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
|
||||
};
|
||||
ina226-vcc1v2-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
|
||||
};
|
||||
ina226-vdd1-1v8-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
|
||||
};
|
||||
ina226-vcc0v6-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
is-dual = <1>;
|
||||
flash@0 {
|
||||
compatible = "m25p80", "spi-flash"; /* 32MB */
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
|
|
@ -89,7 +114,7 @@
|
|||
phy-handle = <&phy0>;
|
||||
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
|
||||
phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
|
||||
phy0: phy@0 { /* marwell m88e1512 - SGMII */
|
||||
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
|
||||
reg = <0>;
|
||||
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
|
||||
};
|
||||
|
|
@ -183,31 +208,43 @@
|
|||
reg = <1>;
|
||||
vcc_aux: ina226@42 { /* u86 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-aux";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc_ram: ina226@43 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-ram";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc1v1_lp4: ina226@46 { /* u96 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v1-lp4";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc1v2_lp4: ina226@47 { /* u98 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v2-lp4";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vdd1_1v8_lp4: ina226@48 { /* u100 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vdd1-1v8-lp4";
|
||||
reg = <0x48>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc0v6_lp4: ina226@49 { /* u101 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc0v6-lp4";
|
||||
reg = <0x49>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
@ -217,7 +254,7 @@
|
|||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
reg_vccint: tps53681@c0 { /* u69 */
|
||||
compatible = "ti,tps53681"; /* FIXME no linux driver */
|
||||
compatible = "ti,tps53681", "ti,tps53679";
|
||||
reg = <0xc0>;
|
||||
};
|
||||
reg_vcc_pmc: tps544@7 { /* u80 */
|
||||
|
|
@ -289,7 +326,7 @@
|
|||
reg = <0x51>;
|
||||
};
|
||||
|
||||
i2c-mux@74 { /* u35 */
|
||||
i2c-mux@74 { /* u47 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -354,19 +391,14 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
i2c@1 { /* UTIL_PMBUS - FIXME incorrect schematics */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* reg = <1>; */
|
||||
};
|
||||
i2c@2 { /* C0_LP4 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
si570_c0_lp4: clock-generator@5d { /* u10 */
|
||||
si570_c0_lp4: clock-generator@55 { /* u10 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* FIXME addr */
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
|
|
@ -391,10 +423,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
si570_c2_lp4: clock-generator@5d { /* u10 */
|
||||
si570_c2_lp4: clock-generator@55 { /* u10 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* FIXME addr */
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
|
|
@ -405,10 +437,10 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
si570_c3_lp4: clock-generator@5d { /* u15 */
|
||||
si570_c3_lp4: clock-generator@55 { /* u15 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* FIXME addr */
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
|
|
@ -424,8 +456,8 @@
|
|||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* FIXME addr */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
|
||||
clock-frequency = <33333333>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <156250000>;
|
||||
clock-output-names = "HSDP_SI570";
|
||||
};
|
||||
};
|
||||
496
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
Normal file
496
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
Normal file
|
|
@ -0,0 +1,496 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx Versal a2197 RevA System Controller
|
||||
*
|
||||
* (C) Copyright 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Versal System Controller on a2197 Memory Char board RevA";
|
||||
compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA",
|
||||
"xlnx,zynqmp-a2197", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem0;
|
||||
gpio0 = &gpio;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
spi0 = &qspi;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
xlnx,eeprom = <&eeprom>;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
|
||||
};
|
||||
|
||||
ina226-vcc-aux {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
|
||||
};
|
||||
ina226-vcc-ram {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
|
||||
};
|
||||
ina226-vcc1v1-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
|
||||
};
|
||||
ina226-vcc1v2-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
|
||||
};
|
||||
ina226-vdd1-1v8-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
is-dual = <1>;
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
|
||||
status = "okay";
|
||||
non-removable;
|
||||
disable-wp;
|
||||
bus-width = <8>;
|
||||
xlnx,mio_bank = <0>; /* FIXME tap delay */
|
||||
};
|
||||
|
||||
&uart0 { /* uart0 MIO38-39 */
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart1 { /* uart1 MIO40-41 */
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&sdhci1 { /* sd1 MIO45-51 cd in place */
|
||||
status = "disable";
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
|
||||
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
|
||||
"N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
|
||||
"SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
|
||||
"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
|
||||
"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
|
||||
"", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
|
||||
"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
|
||||
"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
|
||||
"UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
|
||||
"SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
|
||||
"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
|
||||
"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
|
||||
"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
|
||||
"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
|
||||
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
|
||||
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
|
||||
"", "", "", "", "", /* 78 - 79 */
|
||||
"", "", "", "", "", /* 80 - 84 */
|
||||
"", "", "", "", "", /* 85 -89 */
|
||||
"", "", "", "", "", /* 90 - 94 */
|
||||
"", "", "", "", "", /* 95 - 99 */
|
||||
"", "", "", "", "", /* 100 - 104 */
|
||||
"", "", "", "", "", /* 105 - 109 */
|
||||
"", "", "", "", "", /* 110 - 114 */
|
||||
"", "", "", "", "", /* 115 - 119 */
|
||||
"", "", "", "", "", /* 120 - 124 */
|
||||
"", "", "", "", "", /* 125 - 129 */
|
||||
"", "", "", "", "", /* 130 - 134 */
|
||||
"", "", "", "", "", /* 135 - 139 */
|
||||
"", "", "", "", "", /* 140 - 144 */
|
||||
"", "", "", "", "", /* 145 - 149 */
|
||||
"", "", "", "", "", /* 150 - 154 */
|
||||
"", "", "", "", "", /* 155 - 159 */
|
||||
"", "", "", "", "", /* 160 - 164 */
|
||||
"", "", "", "", "", /* 165 - 169 */
|
||||
"", "", "", ""; /* 170 - 174 */
|
||||
};
|
||||
|
||||
&i2c0 { /* MIO 34-35 - can't stay here */
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
i2c-mux@74 { /* u46 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
|
||||
i2c@0 { /* PMBUS must be enabled via SW21 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
reg_vcc1v2_lp4: tps544@15 { /* u97 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x15>;
|
||||
};
|
||||
reg_vcc1v1_lp4: tps544@16 { /* u95 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x16>;
|
||||
};
|
||||
reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x17>;
|
||||
};
|
||||
/* UTIL_PMBUS connection */
|
||||
reg_vcc1v8: tps544@13 { /* u92 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x13>;
|
||||
};
|
||||
reg_vcc3v3: tps544@14 { /* u93 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x14>;
|
||||
};
|
||||
reg_vcc5v0: tps544@1e { /* u94 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x1e>;
|
||||
};
|
||||
reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x17>; /* FIXME wrong in schematics */
|
||||
};
|
||||
};
|
||||
i2c@1 { /* PMBUS_INA226 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
vcc_aux: ina226@42 { /* u86 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-aux";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc_ram: ina226@43 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-ram";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc1v1_lp4: ina226@46 { /* u96 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v1-lp4";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc1v2_lp4: ina226@47 { /* u98 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v2-lp4";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vdd1_1v8_lp4: ina226@48 { /* u100 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vdd1-1v8-lp4";
|
||||
reg = <0x48>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
i2c@2 { /* PMBUS1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
reg_vccint: tps53681@c0 { /* u69 */
|
||||
compatible = "ti,tps53681", "ti,tps53679";
|
||||
reg = <0xc0>;
|
||||
};
|
||||
reg_vcc_pmc: tps544@7 { /* u80 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x7>;
|
||||
};
|
||||
reg_vcc_ram: tps544@8 { /* u82 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x8>;
|
||||
};
|
||||
reg_vcc_pslp: tps544@9 { /* u83 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x9>;
|
||||
};
|
||||
reg_vcc_psfp: tps544@a { /* u84 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0xa>;
|
||||
};
|
||||
reg_vccaux: tps544@d { /* u85 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0xd>;
|
||||
};
|
||||
reg_vccaux_pmc: tps544@e { /* u87 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0xe>;
|
||||
};
|
||||
reg_vcco_500: tps544@f { /* u88 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0xf>;
|
||||
};
|
||||
reg_vcco_501: tps544@10 { /* u89 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x10>;
|
||||
};
|
||||
reg_vcco_502: tps544@11 { /* u90 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x11>;
|
||||
};
|
||||
reg_vcco_503: tps544@12 { /* u91 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x12>;
|
||||
};
|
||||
};
|
||||
i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* reg = <3>; */
|
||||
};
|
||||
i2c@4 { /* LP_I2C_SM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* connected to U20G */
|
||||
};
|
||||
i2c@5 { /* C0_DDR4_RDIMM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
};
|
||||
i2c@6 { /* C2_DDR5_RDIMM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
};
|
||||
i2c@7 { /* C3_DDR4_UDIMM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* TODO sysctrl via J239 */
|
||||
/* TODO samtec J212G/H via J242 */
|
||||
/* TODO teensy via U30 PCA9543A bus 1 */
|
||||
&i2c1 { /* i2c1 MIO 36-37 */
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* Must be enabled via J242 */
|
||||
eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
i2c-mux@74 { /* u47 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
|
||||
dc_i2c: i2c@0 { /* DC_I2C */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* Use for storing information about SC board */
|
||||
eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
si570_ref_clk: clock-generator@5d { /* u26 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* FIXME addr */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different */
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "REF_CLK"; /* FIXME */
|
||||
};
|
||||
/* Connection via Samtec U20D */
|
||||
/* Use for storing information about X-PRC card */
|
||||
x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
/* Use for setting up certain features on X-PRC card */
|
||||
x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
|
||||
compatible = "nxp,pca9534";
|
||||
reg = <0x22>;
|
||||
gpio-controller; /* IRQ not connected */
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
|
||||
"", "", "", "";
|
||||
gtr_sel0 {
|
||||
gpio-hog;
|
||||
gpios = <0 0>;
|
||||
input; /* FIXME add meaning */
|
||||
line-name = "sw4_1";
|
||||
};
|
||||
gtr_sel1 {
|
||||
gpio-hog;
|
||||
gpios = <1 0>;
|
||||
input; /* FIXME add meaning */
|
||||
line-name = "sw4_2";
|
||||
};
|
||||
gtr_sel2 {
|
||||
gpio-hog;
|
||||
gpios = <2 0>;
|
||||
input; /* FIXME add meaning */
|
||||
line-name = "sw4_3";
|
||||
};
|
||||
gtr_sel3 {
|
||||
gpio-hog;
|
||||
gpios = <3 0>;
|
||||
input; /* FIXME add meaning */
|
||||
line-name = "sw4_4";
|
||||
};
|
||||
};
|
||||
};
|
||||
i2c@2 { /* C0_DDR4 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
si570_c0_ddr4: clock-generator@55 { /* u4 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
clock-output-names = "C0_DD4_SI570_CLK";
|
||||
};
|
||||
};
|
||||
i2c@3 { /* C1_RLD3 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
si570_c1_lp4: clock-generator@55 { /* u7 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
clock-output-names = "C1_RLD3_SI570_CLK";
|
||||
};
|
||||
};
|
||||
i2c@4 { /* C2_DDR5 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
si570_c2_lp4: clock-generator@55 { /* u10 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
clock-output-names = "C2_DDR5_SI570_CLK";
|
||||
};
|
||||
};
|
||||
i2c@5 { /* C3_DDR4 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
si570_c3_lp4: clock-generator@55 { /* u15 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
clock-output-names = "C3_LP4_SI570_CLK";
|
||||
};
|
||||
};
|
||||
i2c@6 { /* HSDP_SI570 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
si570_hsdp: clock-generator@5d { /* u19 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <156250000>;
|
||||
clock-output-names = "HSDP_SI570";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
xlnx,usb-polarity = <0>;
|
||||
xlnx,usb-reset-mode = <0>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
/* dr_mode = "peripheral"; */
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "disabled"; /* not at mem board */
|
||||
xlnx,usb-polarity = <0>;
|
||||
xlnx,usb-reset-mode = <0>;
|
||||
};
|
||||
|
||||
&dwc3_1 {
|
||||
/delete-property/ phy-names ;
|
||||
/delete-property/ phys ;
|
||||
maximum-speed = "high-speed";
|
||||
snps,dis_u2_susphy_quirk ;
|
||||
snps,dis_u3_susphy_quirk ;
|
||||
status = "disabled";
|
||||
};
|
||||
486
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
Normal file
486
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
Normal file
|
|
@ -0,0 +1,486 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx Versal a2197 RevA System Controller
|
||||
*
|
||||
* (C) Copyright 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Versal System Controller on a2197 Memory Char board RevA";
|
||||
compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA",
|
||||
"xlnx,zynqmp-a2197", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem0;
|
||||
gpio0 = &gpio;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
spi0 = &qspi;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
xlnx,eeprom = <&eeprom>;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
|
||||
};
|
||||
|
||||
ina226-vcc-aux {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
|
||||
};
|
||||
ina226-vcc-ram {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
|
||||
};
|
||||
ina226-vcc1v1-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
|
||||
};
|
||||
ina226-vcc1v2-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
|
||||
};
|
||||
ina226-vdd1-1v8-lp4 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
is-dual = <1>;
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
|
||||
status = "okay";
|
||||
non-removable;
|
||||
disable-wp;
|
||||
bus-width = <8>;
|
||||
xlnx,mio_bank = <0>; /* FIXME tap delay */
|
||||
};
|
||||
|
||||
&uart0 { /* uart0 MIO38-39 */
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&uart1 { /* uart1 MIO40-41 */
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&sdhci1 { /* sd1 MIO45-51 cd in place */
|
||||
status = "disable";
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
|
||||
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
|
||||
"N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
|
||||
"SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
|
||||
"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
|
||||
"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
|
||||
"", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
|
||||
"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
|
||||
"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
|
||||
"UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
|
||||
"SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
|
||||
"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
|
||||
"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
|
||||
"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
|
||||
"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
|
||||
"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
|
||||
"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
|
||||
"", "", "", "", "", /* 78 - 79 */
|
||||
"", "", "", "", "", /* 80 - 84 */
|
||||
"", "", "", "", "", /* 85 -89 */
|
||||
"", "", "", "", "", /* 90 - 94 */
|
||||
"", "", "", "", "", /* 95 - 99 */
|
||||
"", "", "", "", "", /* 100 - 104 */
|
||||
"", "", "", "", "", /* 105 - 109 */
|
||||
"", "", "", "", "", /* 110 - 114 */
|
||||
"", "", "", "", "", /* 115 - 119 */
|
||||
"", "", "", "", "", /* 120 - 124 */
|
||||
"", "", "", "", "", /* 125 - 129 */
|
||||
"", "", "", "", "", /* 130 - 134 */
|
||||
"", "", "", "", "", /* 135 - 139 */
|
||||
"", "", "", "", "", /* 140 - 144 */
|
||||
"", "", "", "", "", /* 145 - 149 */
|
||||
"", "", "", "", "", /* 150 - 154 */
|
||||
"", "", "", "", "", /* 155 - 159 */
|
||||
"", "", "", "", "", /* 160 - 164 */
|
||||
"", "", "", "", "", /* 165 - 169 */
|
||||
"", "", "", ""; /* 170 - 174 */
|
||||
};
|
||||
|
||||
&i2c0 { /* MIO 34-35 - can't stay here */
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
i2c-mux@74 { /* u46 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
|
||||
i2c@0 { /* PMBUS must be enabled via SW21 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
reg_vcc1v2_lp4: tps544@15 { /* u97 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x15>;
|
||||
};
|
||||
reg_vcc1v1_lp4: tps544@16 { /* u95 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x16>;
|
||||
};
|
||||
reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x17>;
|
||||
};
|
||||
/* UTIL_PMBUS connection */
|
||||
reg_vcc1v8: tps544@13 { /* u92 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x13>;
|
||||
};
|
||||
reg_vcc3v3: tps544@14 { /* u93 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x14>;
|
||||
};
|
||||
reg_vcc5v0: tps544@1e { /* u94 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x1e>;
|
||||
};
|
||||
reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x17>; /* FIXME wrong in schematics */
|
||||
};
|
||||
};
|
||||
i2c@1 { /* PMBUS_INA226 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
vcc_aux: ina226@42 { /* u86 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-aux";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc_ram: ina226@43 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc-ram";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc1v1_lp4: ina226@46 { /* u96 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v1-lp4";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vcc1v2_lp4: ina226@47 { /* u98 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v2-lp4";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vdd1_1v8_lp4: ina226@48 { /* u100 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vdd1-1v8-lp4";
|
||||
reg = <0x48>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
i2c@2 { /* PMBUS1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
reg_vccint: tps53681@c0 { /* u69 */
|
||||
compatible = "ti,tps53681", "ti,tps53679";
|
||||
reg = <0xc0>;
|
||||
};
|
||||
reg_vcc_pmc: tps544@7 { /* u80 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x7>;
|
||||
};
|
||||
reg_vcc_ram: tps544@8 { /* u82 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x8>;
|
||||
};
|
||||
reg_vcc_pslp: tps544@9 { /* u83 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x9>;
|
||||
};
|
||||
reg_vcc_psfp: tps544@a { /* u84 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0xa>;
|
||||
};
|
||||
reg_vccaux: tps544@d { /* u85 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0xd>;
|
||||
};
|
||||
reg_vccaux_pmc: tps544@e { /* u87 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0xe>;
|
||||
};
|
||||
reg_vcco_500: tps544@f { /* u88 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0xf>;
|
||||
};
|
||||
reg_vcco_501: tps544@10 { /* u89 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x10>;
|
||||
};
|
||||
reg_vcco_502: tps544@11 { /* u90 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x11>;
|
||||
};
|
||||
reg_vcco_503: tps544@12 { /* u91 */
|
||||
compatible = "ti,tps544b25";
|
||||
reg = <0x12>;
|
||||
};
|
||||
};
|
||||
i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* reg = <3>; */
|
||||
};
|
||||
i2c@4 { /* LP_I2C_SM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* connected to U20G */
|
||||
};
|
||||
i2c@5 { /* DDR4_SODIMM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* TODO sysctrl via J239 */
|
||||
/* TODO samtec J212G/H via J242 */
|
||||
/* TODO teensy via U30 PCA9543A bus 1 */
|
||||
&i2c1 { /* i2c1 MIO 36-37 */
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
/* Must be enabled via J242 */
|
||||
eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
i2c-mux@74 { /* u47 */
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
/* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
|
||||
dc_i2c: i2c@0 { /* DC_I2C */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* Use for storing information about SC board */
|
||||
eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
si570_ref_clk: clock-generator@5d { /* u26 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* FIXME addr */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different */
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "REF_CLK"; /* FIXME */
|
||||
};
|
||||
/* Connection via Samtec U20D */
|
||||
/* Use for storing information about X-PRC card */
|
||||
x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
/* Use for setting up certain features on X-PRC card */
|
||||
x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
|
||||
compatible = "nxp,pca9534";
|
||||
reg = <0x22>;
|
||||
gpio-controller; /* IRQ not connected */
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
|
||||
"", "", "", "";
|
||||
gtr_sel0 {
|
||||
gpio-hog;
|
||||
gpios = <0 0>;
|
||||
input; /* FIXME add meaning */
|
||||
line-name = "sw4_1";
|
||||
};
|
||||
gtr_sel1 {
|
||||
gpio-hog;
|
||||
gpios = <1 0>;
|
||||
input; /* FIXME add meaning */
|
||||
line-name = "sw4_2";
|
||||
};
|
||||
gtr_sel2 {
|
||||
gpio-hog;
|
||||
gpios = <2 0>;
|
||||
input; /* FIXME add meaning */
|
||||
line-name = "sw4_3";
|
||||
};
|
||||
gtr_sel3 {
|
||||
gpio-hog;
|
||||
gpios = <3 0>;
|
||||
input; /* FIXME add meaning */
|
||||
line-name = "sw4_4";
|
||||
};
|
||||
};
|
||||
};
|
||||
i2c@2 { /* C0_DDR4 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
si570_c0_ddr4: clock-generator@55 { /* u4 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
clock-output-names = "C0_DD4_SI570_CLK";
|
||||
};
|
||||
};
|
||||
i2c@3 { /* C1_SODIMM */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
si570_c1_lp4: clock-generator@55 { /* u7 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
clock-output-names = "C1_SODIMM_SI570_CLK";
|
||||
};
|
||||
};
|
||||
i2c@4 { /* C2_QDRIV */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
si570_c2_lp4: clock-generator@55 { /* u10 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
clock-output-names = "C2_QDRIV_SI570_CLK";
|
||||
};
|
||||
};
|
||||
i2c@5 { /* C3_DDR4 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
si570_c3_lp4: clock-generator@55 { /* u15 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x55>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <30000000>;
|
||||
clock-frequency = <30000000>;
|
||||
clock-output-names = "C3_LP4_SI570_CLK";
|
||||
};
|
||||
};
|
||||
i2c@6 { /* HSDP_SI570 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
si570_hsdp: clock-generator@5d { /* u19 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <156250000>;
|
||||
clock-output-names = "HSDP_SI570";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
xlnx,usb-polarity = <0>;
|
||||
xlnx,usb-reset-mode = <0>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
/* dr_mode = "peripheral"; */
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "disabled"; /* not at mem board */
|
||||
xlnx,usb-polarity = <0>;
|
||||
xlnx,usb-reset-mode = <0>;
|
||||
};
|
||||
|
||||
&dwc3_1 {
|
||||
/delete-property/ phy-names ;
|
||||
/delete-property/ phys ;
|
||||
maximum-speed = "high-speed";
|
||||
snps,dis_u2_susphy_quirk ;
|
||||
snps,dis_u3_susphy_quirk ;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
/ {
|
||||
model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
|
||||
compatible = "xlnx,zynqmp-a2197-p-revA", "xlnx,zynqmp-a2197-revA",
|
||||
compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
|
||||
"xlnx,zynqmp-a2197", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
|
|
@ -41,7 +41,7 @@
|
|||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -76,7 +76,7 @@
|
|||
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
|
||||
is-internal-pcspma;
|
||||
/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
|
||||
phy0: phy@0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -155,9 +155,9 @@
|
|||
compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
|
||||
reg = <0xa>;
|
||||
};
|
||||
reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */
|
||||
compatible = "ti,tps53681"; /* FIXME no linux driver */
|
||||
reg = <0xc0>;
|
||||
reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */
|
||||
compatible = "ti,tps53681", "ti,tps53679";
|
||||
reg = <0x60>;
|
||||
/* vccint, vcc_io_soc */
|
||||
};
|
||||
};
|
||||
|
|
@ -165,7 +165,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* FIXME check alerts comming to SC */
|
||||
/* FIXME check alerts coming to SC */
|
||||
vcc_fmc: ina226@42 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x42>;
|
||||
|
|
@ -387,9 +387,9 @@
|
|||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* 570JAC000900DG */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different */
|
||||
factory-fout = <33333333>;
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "REF_CLK"; /* FIXME */
|
||||
clock-output-names = "ref_clk";
|
||||
};
|
||||
/* Connection via Samtec J212D */
|
||||
/* Use for storing information about X-PRC card */
|
||||
|
|
@ -455,9 +455,9 @@
|
|||
compatible = "silabs,si570";
|
||||
reg = <0x60>; /* 570BAB000299DG */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "REF_CLK"; /* FIXME */
|
||||
factory-fout = <200000000>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "si570_ddrdimm1_clk";
|
||||
};
|
||||
/* 0x50 SPD? */
|
||||
};
|
||||
|
|
@ -470,9 +470,9 @@
|
|||
compatible = "silabs,si570";
|
||||
reg = <0x60>; /* 570BAB000299DG */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "REF_CLK"; /* FIXME */
|
||||
factory-fout = <200000000>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "si570_ddrdimm2_clk";
|
||||
};
|
||||
/* 0x50 SPD? */
|
||||
};
|
||||
|
|
@ -485,9 +485,9 @@
|
|||
compatible = "silabs,si570";
|
||||
reg = <0x60>; /* 570BAB000299DG */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "LPDDR4_SI570_CLK";
|
||||
factory-fout = <200000000>;
|
||||
clock-frequency = <200000000>;
|
||||
clock-output-names = "si570_lpddr4_clk";
|
||||
};
|
||||
};
|
||||
i2c@6 { /* HSDP_SI570 */
|
||||
|
|
@ -499,9 +499,9 @@
|
|||
compatible = "silabs,si570";
|
||||
reg = <0x5d>; /* 570JAC000900DG */
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
|
||||
clock-frequency = <33333333>;
|
||||
clock-output-names = "HSDP_SI570";
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <156250000>;
|
||||
clock-output-names = "si570_hsdp_clk";
|
||||
};
|
||||
};
|
||||
i2c@7 { /* PCIE_CLK */
|
||||
|
|
@ -75,7 +75,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -85,11 +85,12 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@5 {
|
||||
phy0: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -118,56 +119,66 @@
|
|||
&nand0 {
|
||||
status = "okay";
|
||||
arasan,has-mdma;
|
||||
num-cs = <2>;
|
||||
|
||||
partition@0 { /* for testing purpose */
|
||||
label = "nand-fsbl-uboot";
|
||||
reg = <0x0 0x0 0x400000>;
|
||||
};
|
||||
partition@1 { /* for testing purpose */
|
||||
label = "nand-linux";
|
||||
reg = <0x0 0x400000 0x1400000>;
|
||||
};
|
||||
partition@2 { /* for testing purpose */
|
||||
label = "nand-device-tree";
|
||||
reg = <0x0 0x1800000 0x400000>;
|
||||
};
|
||||
partition@3 { /* for testing purpose */
|
||||
label = "nand-rootfs";
|
||||
reg = <0x0 0x1C00000 0x1400000>;
|
||||
};
|
||||
partition@4 { /* for testing purpose */
|
||||
label = "nand-bitstream";
|
||||
reg = <0x0 0x3000000 0x400000>;
|
||||
};
|
||||
partition@5 { /* for testing purpose */
|
||||
label = "nand-misc";
|
||||
reg = <0x0 0x3400000 0xFCC00000>;
|
||||
};
|
||||
nand@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
partition@6 { /* for testing purpose */
|
||||
label = "nand1-fsbl-uboot";
|
||||
reg = <0x1 0x0 0x400000>;
|
||||
partition@0 { /* for testing purpose */
|
||||
label = "nand-fsbl-uboot";
|
||||
reg = <0x0 0x0 0x400000>;
|
||||
};
|
||||
partition@1 { /* for testing purpose */
|
||||
label = "nand-linux";
|
||||
reg = <0x0 0x400000 0x1400000>;
|
||||
};
|
||||
partition@2 { /* for testing purpose */
|
||||
label = "nand-device-tree";
|
||||
reg = <0x0 0x1800000 0x400000>;
|
||||
};
|
||||
partition@3 { /* for testing purpose */
|
||||
label = "nand-rootfs";
|
||||
reg = <0x0 0x1c00000 0x1400000>;
|
||||
};
|
||||
partition@4 { /* for testing purpose */
|
||||
label = "nand-bitstream";
|
||||
reg = <0x0 0x3000000 0x400000>;
|
||||
};
|
||||
partition@5 { /* for testing purpose */
|
||||
label = "nand-misc";
|
||||
reg = <0x0 0x3400000 0xfcc00000>;
|
||||
};
|
||||
};
|
||||
partition@7 { /* for testing purpose */
|
||||
label = "nand1-linux";
|
||||
reg = <0x1 0x400000 0x1400000>;
|
||||
};
|
||||
partition@8 { /* for testing purpose */
|
||||
label = "nand1-device-tree";
|
||||
reg = <0x1 0x1800000 0x400000>;
|
||||
};
|
||||
partition@9 { /* for testing purpose */
|
||||
label = "nand1-rootfs";
|
||||
reg = <0x1 0x1C00000 0x1400000>;
|
||||
};
|
||||
partition@10 { /* for testing purpose */
|
||||
label = "nand1-bitstream";
|
||||
reg = <0x1 0x3000000 0x400000>;
|
||||
};
|
||||
partition@11 { /* for testing purpose */
|
||||
label = "nand1-misc";
|
||||
reg = <0x1 0x3400000 0xFCC00000>;
|
||||
nand@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
partition@0 { /* for testing purpose */
|
||||
label = "nand1-fsbl-uboot";
|
||||
reg = <0x0 0x0 0x400000>;
|
||||
};
|
||||
partition@1 { /* for testing purpose */
|
||||
label = "nand1-linux";
|
||||
reg = <0x0 0x400000 0x1400000>;
|
||||
};
|
||||
partition@2 { /* for testing purpose */
|
||||
label = "nand1-device-tree";
|
||||
reg = <0x0 0x1800000 0x400000>;
|
||||
};
|
||||
partition@3 { /* for testing purpose */
|
||||
label = "nand1-rootfs";
|
||||
reg = <0x0 0x1c00000 0x1400000>;
|
||||
};
|
||||
partition@4 { /* for testing purpose */
|
||||
label = "nand1-bitstream";
|
||||
reg = <0x0 0x3000000 0x400000>;
|
||||
};
|
||||
partition@5 { /* for testing purpose */
|
||||
label = "nand1-misc";
|
||||
reg = <0x0 0x3400000 0xfcc00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 { /* VSC8211 */
|
||||
phy0: ethernet-phy@0 { /* VSC8211 */
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -124,6 +124,11 @@
|
|||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
|
||||
};
|
||||
|
||||
ina226 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
|
|
@ -216,8 +221,9 @@
|
|||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* PS_PMBUS */
|
||||
ina226@40 { /* u35 */
|
||||
u35: ina226@40 { /* u35 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <10000>;
|
||||
/* MIO31 is alert which should be routed to PMUFW */
|
||||
|
|
|
|||
|
|
@ -34,3 +34,7 @@
|
|||
reg = <0xe0 0x3>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
/delete-property/ no-1-8-v;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -64,6 +64,79 @@
|
|||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
ina226-u76 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
|
||||
};
|
||||
ina226-u77 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
|
||||
};
|
||||
ina226-u78 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
|
||||
};
|
||||
ina226-u87 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
|
||||
};
|
||||
ina226-u85 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
|
||||
};
|
||||
ina226-u86 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
|
||||
};
|
||||
ina226-u93 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
|
||||
};
|
||||
ina226-u88 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
|
||||
};
|
||||
ina226-u15 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
|
||||
};
|
||||
ina226-u92 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
|
||||
};
|
||||
ina226-u79 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
|
||||
};
|
||||
ina226-u81 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
|
||||
};
|
||||
ina226-u80 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
|
||||
};
|
||||
ina226-u84 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
|
||||
};
|
||||
ina226-u16 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
|
||||
};
|
||||
ina226-u65 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
|
||||
};
|
||||
ina226-u74 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
|
||||
};
|
||||
ina226-u75 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
|
|
@ -110,11 +183,13 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@21 {
|
||||
phy0: ethernet-phy@21 {
|
||||
reg = <21>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -133,21 +208,11 @@
|
|||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
gpio-controller; /* IRQ not connected */
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - PS_GTR_LAN_SEL0
|
||||
* 1 - PS_GTR_LAN_SEL1
|
||||
* 2 - PS_GTR_LAN_SEL2
|
||||
* 3 - PS_GTR_LAN_SEL3
|
||||
* 4 - PCI_CLK_DIR_SEL
|
||||
* 5 - IIC_MUX_RESET_B
|
||||
* 6 - GEM3_EXP_RESET_B
|
||||
* 7, 10 - 17 - not connected
|
||||
*/
|
||||
|
||||
gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
|
||||
"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
|
||||
"", "", "", "", "", "", "", "", "";
|
||||
gtr_sel0 {
|
||||
gpio-hog;
|
||||
gpios = <0 0>;
|
||||
|
|
@ -177,27 +242,12 @@
|
|||
tca6416_u61: gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
gpio-controller; /* IRQ not connected */
|
||||
#gpio-cells = <2>;
|
||||
/*
|
||||
* IRQ not connected
|
||||
* Lines:
|
||||
* 0 - VCCPSPLL_EN
|
||||
* 1 - MGTRAVCC_EN
|
||||
* 2 - MGTRAVTT_EN
|
||||
* 3 - VCCPSDDRPLL_EN
|
||||
* 4 - MIO26_PMU_INPUT_LS
|
||||
* 5 - PL_PMBUS_ALERT
|
||||
* 6 - PS_PMBUS_ALERT
|
||||
* 7 - MAXIM_PMBUS_ALERT
|
||||
* 10 - PL_DDR4_VTERM_EN
|
||||
* 11 - PL_DDR4_VPP_2V5_EN
|
||||
* 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
|
||||
* 13 - PS_DIMM_SUSPEND_EN
|
||||
* 14 - PS_DDR4_VTERM_EN
|
||||
* 15 - PS_DDR4_VPP_2V5_EN
|
||||
* 16 - 17 - not connected
|
||||
*/
|
||||
gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
|
||||
"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
|
||||
"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
|
||||
"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
|
||||
};
|
||||
|
||||
i2c-mux@75 { /* u60 */
|
||||
|
|
@ -210,53 +260,73 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
ina226@40 { /* u76 */
|
||||
u76: ina226@40 { /* u76 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u76";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@41 { /* u77 */
|
||||
u77: ina226@41 { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u77";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u78 */
|
||||
u78: ina226@42 { /* u78 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u78";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u87 */
|
||||
u87: ina226@43 { /* u87 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u87";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u85 */
|
||||
u85: ina226@44 { /* u85 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u85";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u86 */
|
||||
u86: ina226@45 { /* u86 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u86";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u93 */
|
||||
u93: ina226@46 { /* u93 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u93";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u88 */
|
||||
u88: ina226@47 { /* u88 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u88";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4a { /* u15 */
|
||||
u15: ina226@4a { /* u15 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u15";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4b { /* u92 */
|
||||
u92: ina226@4b { /* u92 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u92";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
@ -266,43 +336,59 @@
|
|||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* PL_PMBUS */
|
||||
ina226@40 { /* u79 */
|
||||
u79: ina226@40 { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u79";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@41 { /* u81 */
|
||||
u81: ina226@41 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u81";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u80 */
|
||||
u80: ina226@42 { /* u80 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u80";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u84 */
|
||||
u84: ina226@43 { /* u84 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u84";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u16 */
|
||||
u16: ina226@44 { /* u16 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u16";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u65 */
|
||||
u65: ina226@45 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u65";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u74 */
|
||||
u74: ina226@46 { /* u74 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u74";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u75 */
|
||||
u75: ina226@47 { /* u75 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u75";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,11 +16,13 @@
|
|||
|
||||
&gem3 {
|
||||
phy-handle = <&phyc>;
|
||||
phyc: phy@c {
|
||||
phyc: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
|
||||
};
|
||||
/* Cleanup from RevA */
|
||||
/delete-node/ phy@21;
|
||||
|
|
|
|||
|
|
@ -50,15 +50,48 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -41,6 +41,11 @@
|
|||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
ina226 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
|
|
@ -51,15 +56,48 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -150,8 +188,9 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
ina226@40 { /* u183 */
|
||||
u183: ina226@40 { /* u183 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -64,6 +64,79 @@
|
|||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
ina226-u76 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
|
||||
};
|
||||
ina226-u77 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
|
||||
};
|
||||
ina226-u78 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
|
||||
};
|
||||
ina226-u87 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
|
||||
};
|
||||
ina226-u85 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
|
||||
};
|
||||
ina226-u86 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
|
||||
};
|
||||
ina226-u93 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
|
||||
};
|
||||
ina226-u88 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
|
||||
};
|
||||
ina226-u15 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
|
||||
};
|
||||
ina226-u92 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
|
||||
};
|
||||
ina226-u79 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
|
||||
};
|
||||
ina226-u81 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
|
||||
};
|
||||
ina226-u80 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
|
||||
};
|
||||
ina226-u84 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
|
||||
};
|
||||
ina226-u16 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
|
||||
};
|
||||
ina226-u65 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
|
||||
};
|
||||
ina226-u74 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
|
||||
};
|
||||
ina226-u75 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
|
|
@ -110,11 +183,12 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -184,53 +258,73 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
ina226@40 { /* u76 */
|
||||
u76: ina226@40 { /* u76 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u76";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@41 { /* u77 */
|
||||
u77: ina226@41 { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u77";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u78 */
|
||||
u78: ina226@42 { /* u78 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u78";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u87 */
|
||||
u87: ina226@43 { /* u87 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u87";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u85 */
|
||||
u85: ina226@44 { /* u85 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u85";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u86 */
|
||||
u86: ina226@45 { /* u86 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u86";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u93 */
|
||||
u93: ina226@46 { /* u93 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u93";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u88 */
|
||||
u88: ina226@47 { /* u88 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u88";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4a { /* u15 */
|
||||
u15: ina226@4a { /* u15 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u15";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4b { /* u92 */
|
||||
u92: ina226@4b { /* u92 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u92";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
@ -240,43 +334,59 @@
|
|||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* PL_PMBUS */
|
||||
ina226@40 { /* u79 */
|
||||
u79: ina226@40 { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u79";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@41 { /* u81 */
|
||||
u81: ina226@41 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u81";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u80 */
|
||||
u80: ina226@42 { /* u80 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u80";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u84 */
|
||||
u84: ina226@43 { /* u84 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u84";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@44 { /* u16 */
|
||||
u16: ina226@44 { /* u16 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u16";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u65 */
|
||||
u65: ina226@45 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u65";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u74 */
|
||||
u74: ina226@46 { /* u74 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u74";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@47 { /* u75 */
|
||||
u75: ina226@47 { /* u75 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u75";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -64,6 +64,63 @@
|
|||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
ina226-u67 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
|
||||
};
|
||||
ina226-u59 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
|
||||
};
|
||||
ina226-u61 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
|
||||
};
|
||||
ina226-u60 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
|
||||
};
|
||||
ina226-u64 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
|
||||
};
|
||||
ina226-u69 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
|
||||
};
|
||||
ina226-u66 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
|
||||
};
|
||||
ina226-u65 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
|
||||
};
|
||||
ina226-u63 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
|
||||
};
|
||||
ina226-u3 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
|
||||
};
|
||||
ina226-u71 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
|
||||
};
|
||||
ina226-u77 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
|
||||
};
|
||||
ina226-u73 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
|
||||
};
|
||||
ina226-u79 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
|
|
@ -106,11 +163,12 @@
|
|||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@c {
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -160,73 +218,101 @@
|
|||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
/* PMBUS_ALERT done via pca9544 */
|
||||
ina226@40 { /* u67 */
|
||||
u67: ina226@40 { /* u67 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u67";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@41 { /* u59 */
|
||||
u59: ina226@41 { /* u59 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u59";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@42 { /* u61 */
|
||||
u61: ina226@42 { /* u61 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u61";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@43 { /* u60 */
|
||||
u60: ina226@43 { /* u60 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u60";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@45 { /* u64 */
|
||||
u64: ina226@45 { /* u64 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u64";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@46 { /* u69 */
|
||||
u69: ina226@46 { /* u69 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u69";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
ina226@47 { /* u66 */
|
||||
u66: ina226@47 { /* u66 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u66";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@48 { /* u65 */
|
||||
u65: ina226@48 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u65";
|
||||
reg = <0x48>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@49 { /* u63 */
|
||||
u63: ina226@49 { /* u63 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u63";
|
||||
reg = <0x49>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4a { /* u3 */
|
||||
u3: ina226@4a { /* u3 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u3";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4b { /* u71 */
|
||||
u71: ina226@4b { /* u71 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u71";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4c { /* u77 */
|
||||
u77: ina226@4c { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u77";
|
||||
reg = <0x4c>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4d { /* u73 */
|
||||
u73: ina226@4d { /* u73 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u73";
|
||||
reg = <0x4d>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
ina226@4e { /* u79 */
|
||||
u79: ina226@4e { /* u79 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-u79";
|
||||
reg = <0x4e>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
|
|
@ -332,7 +418,7 @@
|
|||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
clock-frequency = <156250000>;
|
||||
clock-output-names = "si570_mgt";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
592
arch/arm/dts/zynqmp-zcu216-revA.dts
Normal file
592
arch/arm/dts/zynqmp-zcu216-revA.dts
Normal file
|
|
@ -0,0 +1,592 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU216
|
||||
*
|
||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU216 RevA";
|
||||
compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gem3;
|
||||
gpio0 = &gpio;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &dcc;
|
||||
spi0 = &qspi;
|
||||
usb0 = &usb0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
stdout-path = "serial0:115200n8";
|
||||
xlnx,eeprom = <&eeprom>;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
sw19 {
|
||||
label = "sw19";
|
||||
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpio-key,wakeup;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat_led {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
ina226-vccint {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
|
||||
};
|
||||
ina226-vccint-io-bram-ps {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
|
||||
};
|
||||
ina226-vcc1v8 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
|
||||
};
|
||||
ina226-vcc1v2 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
|
||||
};
|
||||
ina226-vadj-fmc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
|
||||
};
|
||||
ina226-mgtavcc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
|
||||
};
|
||||
ina226-mgt1v2 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
|
||||
};
|
||||
ina226-mgt1v8 {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
|
||||
};
|
||||
ina226-vccint-ams {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
|
||||
};
|
||||
ina226-dac-avtt {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
|
||||
};
|
||||
ina226-dac-avccaux {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
|
||||
};
|
||||
ina226-adc-avcc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
|
||||
};
|
||||
ina226-adc-avccaux {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
|
||||
};
|
||||
ina226-dac-avcc {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
|
||||
"QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
|
||||
"QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
|
||||
"I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
|
||||
"", "", "BUTTON", "LED", "", /* 20 - 24 */
|
||||
"", "PMU_INPUT", "", "", "", /* 25 - 29 */
|
||||
"", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
|
||||
"PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
|
||||
"SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
|
||||
"SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
|
||||
"SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
|
||||
"USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
|
||||
"USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
|
||||
"ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
|
||||
"ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
|
||||
"ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
|
||||
"", "", /* 78 - 79 */
|
||||
"", "", "", "", "", /* 80 - 84 */
|
||||
"", "", "", "", "", /* 85 -89 */
|
||||
"", "", "", "", "", /* 90 - 94 */
|
||||
"", "", "", "", "", /* 95 - 99 */
|
||||
"", "", "", "", "", /* 100 - 104 */
|
||||
"", "", "", "", "", /* 105 - 109 */
|
||||
"", "", "", "", "", /* 110 - 114 */
|
||||
"", "", "", "", "", /* 115 - 119 */
|
||||
"", "", "", "", "", /* 120 - 124 */
|
||||
"", "", "", "", "", /* 125 - 129 */
|
||||
"", "", "", "", "", /* 130 - 134 */
|
||||
"", "", "", "", "", /* 135 - 139 */
|
||||
"", "", "", "", "", /* 140 - 144 */
|
||||
"", "", "", "", "", /* 145 - 149 */
|
||||
"", "", "", "", "", /* 150 - 154 */
|
||||
"", "", "", "", "", /* 155 - 159 */
|
||||
"", "", "", "", "", /* 160 - 164 */
|
||||
"", "", "", "", "", /* 165 - 169 */
|
||||
"", "", "", ""; /* 170 - 174 */
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tca6416_u15: gpio@20 { /* u15 */
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller; /* interrupt not connected */
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */
|
||||
"", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
|
||||
"FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
|
||||
"", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
|
||||
};
|
||||
|
||||
i2c-mux@75 { /* u17 */
|
||||
compatible = "nxp,pca9544";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* PS_PMBUS */
|
||||
/* PMBUS_ALERT done via pca9544 */
|
||||
vccint: ina226@40 { /* u65 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccint";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vccint_io_bram_ps: ina226@41 { /* u57 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccint-io-bram-ps";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
vcc1v8: ina226@42 { /* u60 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v8";
|
||||
reg = <0x42>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
vcc1v2: ina226@43 { /* u58 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vcc1v2";
|
||||
reg = <0x43>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vadj_fmc: ina226@45 { /* u62 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vadj-fmc";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
mgtavcc: ina226@46 { /* u67 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-mgtavcc";
|
||||
reg = <0x46>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
mgt1v2: ina226@47 { /* u63 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-mgt1v2";
|
||||
reg = <0x47>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
mgt1v8: ina226@48 { /* u64 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-mgt1v8";
|
||||
reg = <0x48>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
vccint_ams: ina226@49 { /* u61 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-vccint-ams";
|
||||
reg = <0x49>;
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
dac_avtt: ina226@4a { /* u59 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-dac-avtt";
|
||||
reg = <0x4a>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
dac_avccaux: ina226@4b { /* u124 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-dac-avccaux";
|
||||
reg = <0x4b>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
adc_avcc: ina226@4c { /* u75 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-adc-avcc";
|
||||
reg = <0x4c>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
adc_avccaux: ina226@4d { /* u71 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-adc-avccaux";
|
||||
reg = <0x4d>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
dac_avcc: ina226@4e { /* u77 */
|
||||
compatible = "ti,ina226";
|
||||
#io-channel-cells = <1>;
|
||||
label = "ina226-dac-avcc";
|
||||
reg = <0x4e>;
|
||||
shunt-resistor = <5000>;
|
||||
};
|
||||
};
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* NC */
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* u104 - ir35215 0x10/0x40 */
|
||||
/* u127 - ir38164 0x1b/0x4b */
|
||||
/* u112 - ir38164 0x13/0x43 */
|
||||
/* u123 - ir38164 0x1c/0x4c */
|
||||
|
||||
irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x44>; /* i2c addr 0x14 */
|
||||
};
|
||||
irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x45>; /* i2c addr 0x15 */
|
||||
};
|
||||
/* J21 header too */
|
||||
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* SYSMON */
|
||||
};
|
||||
};
|
||||
/* u38 MPS430 */
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
i2c-mux@74 {
|
||||
compatible = "nxp,pca9548"; /* u20 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
i2c_eeprom: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/*
|
||||
* IIC_EEPROM 1kB memory which uses 256B blocks
|
||||
* where every block has different address.
|
||||
* 0 - 256B address 0x54
|
||||
* 256B - 512B address 0x55
|
||||
* 512B - 768B address 0x56
|
||||
* 768B - 1024B address 0x57
|
||||
*/
|
||||
eeprom: eeprom@54 { /* u21 */
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
i2c_si5341: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
si5341: clock-generator@36 { /* SI5341 - u43 */
|
||||
compatible = "si5341";
|
||||
reg = <0x36>;
|
||||
};
|
||||
|
||||
};
|
||||
i2c_si570_user_c0: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
clock-output-names = "si570_user_c0";
|
||||
};
|
||||
};
|
||||
i2c_si570_mgt: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
clock-output-names = "si570_mgt";
|
||||
};
|
||||
};
|
||||
i2c_8a34001: i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* U409B - 8a34001 */
|
||||
};
|
||||
i2c_clk104: i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* CLK104_SDA */
|
||||
};
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/* RFMCP connector */
|
||||
};
|
||||
/* 7 NC */
|
||||
};
|
||||
|
||||
i2c-mux@75 {
|
||||
compatible = "nxp,pca9548"; /* u22 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x75>;
|
||||
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
/* FMCP_HSPC_IIC */
|
||||
};
|
||||
i2c_si570_user_c1: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
reg = <0x5d>;
|
||||
temperature-stability = <50>;
|
||||
factory-fout = <300000000>;
|
||||
clock-frequency = <300000000>;
|
||||
clock-output-names = "si570_user_c1";
|
||||
};
|
||||
};
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
/* SYSMON */
|
||||
};
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* DDR4 SODIMM */
|
||||
};
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
/* SFP3 */
|
||||
};
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
/* SFP2 */
|
||||
};
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
/* SFP1 */
|
||||
};
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
/* SFP0 */
|
||||
};
|
||||
};
|
||||
/* MSP430 */
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
is-dual = <1>;
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
disable-wp;
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
||||
&serdes {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
|
||||
};
|
||||
|
|
@ -12,6 +12,9 @@
|
|||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/power/xlnx-zynqmp-power.h>
|
||||
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,zynqmp";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -112,7 +115,7 @@
|
|||
<0x0 0xff9905e0 0x0 0x20>,
|
||||
<0x0 0xff990e80 0x0 0x20>,
|
||||
<0x0 0xff990ea0 0x0 0x20>;
|
||||
reg-names = "local_request_region" , "local_response_region",
|
||||
reg-names = "local_request_region", "local_response_region",
|
||||
"remote_request_region", "remote_response_region";
|
||||
#mbox-cells = <1>;
|
||||
xlnx,ipi-id = <4>;
|
||||
|
|
@ -140,7 +143,7 @@
|
|||
};
|
||||
|
||||
firmware {
|
||||
zynqmp-firmware {
|
||||
zynqmp_firmware: zynqmp-firmware {
|
||||
compatible = "xlnx,zynqmp-firmware";
|
||||
method = "smc";
|
||||
#power-domain-cells = <0x1>;
|
||||
|
|
@ -154,6 +157,11 @@
|
|||
mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
|
||||
mbox-names = "tx", "rx";
|
||||
};
|
||||
|
||||
zynqmp_reset: reset-controller {
|
||||
compatible = "xlnx,zynqmp-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -279,6 +287,7 @@
|
|||
interrupt-parent = <&gic>;
|
||||
tx-fifo-depth = <0x40>;
|
||||
rx-fifo-depth = <0x40>;
|
||||
power-domains = <&zynqmp_firmware PD_CAN_0>;
|
||||
};
|
||||
|
||||
can1: can@ff070000 {
|
||||
|
|
@ -290,6 +299,7 @@
|
|||
interrupt-parent = <&gic>;
|
||||
tx-fifo-depth = <0x40>;
|
||||
rx-fifo-depth = <0x40>;
|
||||
power-domains = <&zynqmp_firmware PD_CAN_1>;
|
||||
};
|
||||
|
||||
cci: cci@fd6e0000 {
|
||||
|
|
@ -322,6 +332,7 @@
|
|||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14e8>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan2: dma@fd510000 {
|
||||
|
|
@ -334,6 +345,7 @@
|
|||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14e9>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan3: dma@fd520000 {
|
||||
|
|
@ -346,6 +358,7 @@
|
|||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ea>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan4: dma@fd530000 {
|
||||
|
|
@ -358,6 +371,7 @@
|
|||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14eb>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan5: dma@fd540000 {
|
||||
|
|
@ -370,6 +384,7 @@
|
|||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ec>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan6: dma@fd550000 {
|
||||
|
|
@ -382,6 +397,7 @@
|
|||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ed>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan7: dma@fd560000 {
|
||||
|
|
@ -394,6 +410,7 @@
|
|||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ee>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
fpd_dma_chan8: dma@fd570000 {
|
||||
|
|
@ -406,6 +423,7 @@
|
|||
xlnx,bus-width = <128>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x14ef>;
|
||||
power-domains = <&zynqmp_firmware PD_GDMA>;
|
||||
};
|
||||
|
||||
gpu: gpu@fd4b0000 {
|
||||
|
|
@ -416,6 +434,7 @@
|
|||
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
|
||||
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
|
||||
clock-names = "gpu", "gpu_pp0", "gpu_pp1";
|
||||
power-domains = <&zynqmp_firmware PD_GPU>;
|
||||
};
|
||||
|
||||
/* LPDDMA default allows only secured access. inorder to enable
|
||||
|
|
@ -432,6 +451,7 @@
|
|||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x868>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan2: dma@ffa90000 {
|
||||
|
|
@ -444,6 +464,7 @@
|
|||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x869>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan3: dma@ffaa0000 {
|
||||
|
|
@ -456,6 +477,7 @@
|
|||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86a>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan4: dma@ffab0000 {
|
||||
|
|
@ -468,6 +490,7 @@
|
|||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86b>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan5: dma@ffac0000 {
|
||||
|
|
@ -480,6 +503,7 @@
|
|||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86c>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan6: dma@ffad0000 {
|
||||
|
|
@ -492,6 +516,7 @@
|
|||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86d>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan7: dma@ffae0000 {
|
||||
|
|
@ -504,6 +529,7 @@
|
|||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86e>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
lpd_dma_chan8: dma@ffaf0000 {
|
||||
|
|
@ -516,6 +542,7 @@
|
|||
xlnx,bus-width = <64>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x86f>;
|
||||
power-domains = <&zynqmp_firmware PD_ADMA>;
|
||||
};
|
||||
|
||||
mc: memory-controller@fd070000 {
|
||||
|
|
@ -532,14 +559,15 @@
|
|||
clock-names = "clk_sys", "clk_flash";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 14 4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x872>;
|
||||
power-domains = <&zynqmp_firmware PD_NAND>;
|
||||
};
|
||||
|
||||
gem0: ethernet@ff0b0000 {
|
||||
compatible = "cdns,zynqmp-gem";
|
||||
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 57 4>, <0 57 4>;
|
||||
|
|
@ -549,10 +577,11 @@
|
|||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x874>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_0>;
|
||||
};
|
||||
|
||||
gem1: ethernet@ff0c0000 {
|
||||
compatible = "cdns,zynqmp-gem";
|
||||
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 59 4>, <0 59 4>;
|
||||
|
|
@ -562,10 +591,11 @@
|
|||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x875>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_1>;
|
||||
};
|
||||
|
||||
gem2: ethernet@ff0d0000 {
|
||||
compatible = "cdns,zynqmp-gem";
|
||||
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 61 4>, <0 61 4>;
|
||||
|
|
@ -575,10 +605,11 @@
|
|||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x876>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_2>;
|
||||
};
|
||||
|
||||
gem3: ethernet@ff0e0000 {
|
||||
compatible = "cdns,zynqmp-gem";
|
||||
compatible = "cdns,zynqmp-gem", "cdns,gem";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 63 4>, <0 63 4>;
|
||||
|
|
@ -588,6 +619,7 @@
|
|||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x877>;
|
||||
power-domains = <&zynqmp_firmware PD_ETH_3>;
|
||||
};
|
||||
|
||||
gpio: gpio@ff0a0000 {
|
||||
|
|
@ -600,6 +632,7 @@
|
|||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0xff0a0000 0x0 0x1000>;
|
||||
gpio-controller;
|
||||
power-domains = <&zynqmp_firmware PD_GPIO>;
|
||||
};
|
||||
|
||||
i2c0: i2c@ff020000 {
|
||||
|
|
@ -610,6 +643,7 @@
|
|||
reg = <0x0 0xff020000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_I2C_0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@ff030000 {
|
||||
|
|
@ -620,6 +654,7 @@
|
|||
reg = <0x0 0xff030000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_I2C_1>;
|
||||
};
|
||||
|
||||
ocm: memory-controller@ff960000 {
|
||||
|
|
@ -658,6 +693,7 @@
|
|||
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
|
||||
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
|
||||
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
|
||||
power-domains = <&zynqmp_firmware PD_PCIE>;
|
||||
pcie_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
|
|
@ -679,6 +715,7 @@
|
|||
#size-cells = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x873>;
|
||||
power-domains = <&zynqmp_firmware PD_QSPI>;
|
||||
};
|
||||
|
||||
rtc: rtc@ffa60000 {
|
||||
|
|
@ -700,10 +737,18 @@
|
|||
reg-names = "serdes", "siou", "lpd";
|
||||
nvmem-cells = <&soc_revision>;
|
||||
nvmem-cell-names = "soc_revision";
|
||||
resets = <&rst 16>, <&rst 59>, <&rst 60>,
|
||||
<&rst 61>, <&rst 62>, <&rst 63>,
|
||||
<&rst 64>, <&rst 3>, <&rst 29>,
|
||||
<&rst 30>, <&rst 31>, <&rst 32>;
|
||||
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_DP>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_GEM0>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_GEM1>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_GEM2>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_GEM3>;
|
||||
reset-names = "sata_rst", "usb0_crst", "usb1_crst",
|
||||
"usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
|
||||
"usb1_apbrst", "dp_rst", "gem0_rst",
|
||||
|
|
@ -728,6 +773,7 @@
|
|||
reg = <0x0 0xfd0c0000 0x0 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 133 4>;
|
||||
power-domains = <&zynqmp_firmware PD_SATA>;
|
||||
#stream-id-cells = <4>;
|
||||
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
|
||||
<&smmu 0x4c2>, <&smmu 0x4c3>;
|
||||
|
|
@ -745,6 +791,7 @@
|
|||
xlnx,device_id = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x870>;
|
||||
power-domains = <&zynqmp_firmware PD_SD_0>;
|
||||
nvmem-cells = <&soc_revision>;
|
||||
nvmem-cell-names = "soc_revision";
|
||||
};
|
||||
|
|
@ -760,6 +807,7 @@
|
|||
xlnx,device_id = <1>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x871>;
|
||||
power-domains = <&zynqmp_firmware PD_SD_1>;
|
||||
nvmem-cells = <&soc_revision>;
|
||||
nvmem-cell-names = "soc_revision";
|
||||
};
|
||||
|
|
@ -793,6 +841,7 @@
|
|||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_SPI_0>;
|
||||
};
|
||||
|
||||
spi1: spi@ff050000 {
|
||||
|
|
@ -804,6 +853,7 @@
|
|||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
power-domains = <&zynqmp_firmware PD_SPI_1>;
|
||||
};
|
||||
|
||||
ttc0: timer@ff110000 {
|
||||
|
|
@ -813,6 +863,7 @@
|
|||
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
|
||||
reg = <0x0 0xff110000 0x0 0x1000>;
|
||||
timer-width = <32>;
|
||||
power-domains = <&zynqmp_firmware PD_TTC_0>;
|
||||
};
|
||||
|
||||
ttc1: timer@ff120000 {
|
||||
|
|
@ -822,6 +873,7 @@
|
|||
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
|
||||
reg = <0x0 0xff120000 0x0 0x1000>;
|
||||
timer-width = <32>;
|
||||
power-domains = <&zynqmp_firmware PD_TTC_1>;
|
||||
};
|
||||
|
||||
ttc2: timer@ff130000 {
|
||||
|
|
@ -831,6 +883,7 @@
|
|||
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
|
||||
reg = <0x0 0xff130000 0x0 0x1000>;
|
||||
timer-width = <32>;
|
||||
power-domains = <&zynqmp_firmware PD_TTC_2>;
|
||||
};
|
||||
|
||||
ttc3: timer@ff140000 {
|
||||
|
|
@ -840,6 +893,7 @@
|
|||
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
|
||||
reg = <0x0 0xff140000 0x0 0x1000>;
|
||||
timer-width = <32>;
|
||||
power-domains = <&zynqmp_firmware PD_TTC_3>;
|
||||
};
|
||||
|
||||
uart0: serial@ff000000 {
|
||||
|
|
@ -850,6 +904,7 @@
|
|||
interrupts = <0 21 4>;
|
||||
reg = <0x0 0xff000000 0x0 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
power-domains = <&zynqmp_firmware PD_UART_0>;
|
||||
};
|
||||
|
||||
uart1: serial@ff010000 {
|
||||
|
|
@ -860,6 +915,7 @@
|
|||
interrupts = <0 22 4>;
|
||||
reg = <0x0 0xff010000 0x0 0x1000>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
power-domains = <&zynqmp_firmware PD_UART_1>;
|
||||
};
|
||||
|
||||
usb0: usb0@ff9d0000 {
|
||||
|
|
@ -869,6 +925,7 @@
|
|||
compatible = "xlnx,zynqmp-dwc3";
|
||||
reg = <0x0 0xff9d0000 0x0 0x100>;
|
||||
clock-names = "bus_clk", "ref_clk";
|
||||
power-domains = <&zynqmp_firmware PD_USB_0>;
|
||||
ranges;
|
||||
nvmem-cells = <&soc_revision>;
|
||||
nvmem-cell-names = "soc_revision";
|
||||
|
|
@ -894,6 +951,7 @@
|
|||
compatible = "xlnx,zynqmp-dwc3";
|
||||
reg = <0x0 0xff9e0000 0x0 0x100>;
|
||||
clock-names = "bus_clk", "ref_clk";
|
||||
power-domains = <&zynqmp_firmware PD_USB_1>;
|
||||
ranges;
|
||||
nvmem-cells = <&soc_revision>;
|
||||
nvmem-cell-names = "soc_revision";
|
||||
|
|
@ -922,6 +980,15 @@
|
|||
reset-on-timeout;
|
||||
};
|
||||
|
||||
lpd_watchdog: watchdog@ff150000 {
|
||||
compatible = "cdns,wdt-r1p2";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 52 1>;
|
||||
reg = <0x0 0xff150000 0x0 0x1000>;
|
||||
timeout-sec = <10>;
|
||||
};
|
||||
|
||||
xilinx_ams: ams@ffa50000 {
|
||||
compatible = "xlnx,zynqmp-ams";
|
||||
status = "disabled";
|
||||
|
|
@ -986,6 +1053,7 @@
|
|||
interrupts = <0 122 4>;
|
||||
interrupt-parent = <&gic>;
|
||||
clock-names = "axi_clk";
|
||||
power-domains = <&zynqmp_firmware PD_DP>;
|
||||
dma-channels = <6>;
|
||||
#dma-cells = <1>;
|
||||
dma-video0channel {
|
||||
|
|
|
|||
|
|
@ -107,28 +107,3 @@ int reserve_mmu(void)
|
|||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
|
||||
u32 arg3, u32 *ret_payload)
|
||||
{
|
||||
struct pt_regs regs;
|
||||
|
||||
if (current_el() == 3)
|
||||
return 0;
|
||||
|
||||
regs.regs[0] = PM_SIP_SVC | api_id;
|
||||
regs.regs[1] = ((u64)arg1 << 32) | arg0;
|
||||
regs.regs[2] = ((u64)arg3 << 32) | arg2;
|
||||
|
||||
smc_call(®s);
|
||||
|
||||
if (ret_payload) {
|
||||
ret_payload[0] = (u32)regs.regs[0];
|
||||
ret_payload[1] = upper_32_bits(regs.regs[0]);
|
||||
ret_payload[2] = (u32)regs.regs[1];
|
||||
ret_payload[3] = upper_32_bits(regs.regs[1]);
|
||||
ret_payload[4] = (u32)regs.regs[2];
|
||||
}
|
||||
|
||||
return regs.regs[0];
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,65 +8,7 @@ enum {
|
|||
TCM_SPLIT,
|
||||
};
|
||||
|
||||
enum pm_api_id {
|
||||
PM_GET_API_VERSION = 1,
|
||||
PM_SET_CONFIGURATION,
|
||||
PM_GET_NODE_STATUS,
|
||||
PM_GET_OPERATING_CHARACTERISTIC,
|
||||
PM_REGISTER_NOTIFIER,
|
||||
PM_REQUEST_SUSPEND,
|
||||
PM_SELF_SUSPEND,
|
||||
PM_FORCE_POWERDOWN,
|
||||
PM_ABORT_SUSPEND,
|
||||
PM_REQUEST_WAKEUP,
|
||||
PM_SET_WAKEUP_SOURCE,
|
||||
PM_SYSTEM_SHUTDOWN,
|
||||
PM_REQUEST_NODE,
|
||||
PM_RELEASE_NODE,
|
||||
PM_SET_REQUIREMENT,
|
||||
PM_SET_MAX_LATENCY,
|
||||
PM_RESET_ASSERT,
|
||||
PM_RESET_GET_STATUS,
|
||||
PM_MMIO_WRITE,
|
||||
PM_MMIO_READ,
|
||||
PM_PM_INIT_FINALIZE,
|
||||
PM_FPGA_LOAD,
|
||||
PM_FPGA_GET_STATUS,
|
||||
PM_GET_CHIPID,
|
||||
PM_SECURE_SHA = 26,
|
||||
PM_SECURE_RSA,
|
||||
PM_PINCTRL_REQUEST,
|
||||
PM_PINCTRL_RELEASE,
|
||||
PM_PINCTRL_GET_FUNCTION,
|
||||
PM_PINCTRL_SET_FUNCTION,
|
||||
PM_PINCTRL_CONFIG_PARAM_GET,
|
||||
PM_PINCTRL_CONFIG_PARAM_SET,
|
||||
PM_IOCTL,
|
||||
PM_QUERY_DATA,
|
||||
PM_CLOCK_ENABLE,
|
||||
PM_CLOCK_DISABLE,
|
||||
PM_CLOCK_GETSTATE,
|
||||
PM_CLOCK_SETDIVIDER,
|
||||
PM_CLOCK_GETDIVIDER,
|
||||
PM_CLOCK_SETRATE,
|
||||
PM_CLOCK_GETRATE,
|
||||
PM_CLOCK_SETPARENT,
|
||||
PM_CLOCK_GETPARENT,
|
||||
PM_SECURE_IMAGE,
|
||||
PM_FPGA_READ = 46,
|
||||
PM_SECURE_AES,
|
||||
PM_CLOCK_PLL_GETPARAM = 49,
|
||||
PM_REGISTER_ACCESS = 52,
|
||||
PM_EFUSE_ACCESS,
|
||||
PM_FEATURE_CHECK = 63,
|
||||
PM_API_MAX,
|
||||
};
|
||||
|
||||
#define PM_SIP_SVC 0xC2000000
|
||||
#define PAYLOAD_ARG_CNT 4U
|
||||
|
||||
void tcm_init(u8 mode);
|
||||
void mem_map_fill(void);
|
||||
|
||||
int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
|
||||
u32 arg3, u32 *ret_payload);
|
||||
|
|
|
|||
|
|
@ -151,35 +151,6 @@ unsigned int zynqmp_get_silicon_version(void)
|
|||
return ZYNQMP_CSU_VERSION_SILICON;
|
||||
}
|
||||
|
||||
#define ZYNQMP_MMIO_READ 0xC2000014
|
||||
#define ZYNQMP_MMIO_WRITE 0xC2000013
|
||||
|
||||
int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
|
||||
u32 arg3, u32 *ret_payload)
|
||||
{
|
||||
/*
|
||||
* Added SIP service call Function Identifier
|
||||
* Make sure to stay in x0 register
|
||||
*/
|
||||
struct pt_regs regs;
|
||||
|
||||
regs.regs[0] = pm_api_id;
|
||||
regs.regs[1] = ((u64)arg1 << 32) | arg0;
|
||||
regs.regs[2] = ((u64)arg3 << 32) | arg2;
|
||||
|
||||
smc_call(®s);
|
||||
|
||||
if (ret_payload != NULL) {
|
||||
ret_payload[0] = (u32)regs.regs[0];
|
||||
ret_payload[1] = upper_32_bits(regs.regs[0]);
|
||||
ret_payload[2] = (u32)regs.regs[1];
|
||||
ret_payload[3] = upper_32_bits(regs.regs[1]);
|
||||
ret_payload[4] = (u32)regs.regs[2];
|
||||
}
|
||||
|
||||
return regs.regs[0];
|
||||
}
|
||||
|
||||
static int zynqmp_mmio_rawwrite(const u32 address,
|
||||
const u32 mask,
|
||||
const u32 value)
|
||||
|
|
@ -211,28 +182,34 @@ int zynqmp_mmio_write(const u32 address,
|
|||
{
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
|
||||
return zynqmp_mmio_rawwrite(address, mask, value);
|
||||
#if defined(CONFIG_ZYNQMP_FIRMWARE)
|
||||
else
|
||||
return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
|
||||
value, 0, NULL);
|
||||
return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
|
||||
value, 0, NULL);
|
||||
#endif
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int zynqmp_mmio_read(const u32 address, u32 *value)
|
||||
{
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
u32 ret;
|
||||
u32 ret = -EINVAL;
|
||||
|
||||
if (!value)
|
||||
return -EINVAL;
|
||||
return ret;
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
|
||||
ret = zynqmp_mmio_rawread(address, value);
|
||||
} else {
|
||||
ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
|
||||
0, ret_payload);
|
||||
}
|
||||
#if defined(CONFIG_ZYNQMP_FIRMWARE)
|
||||
else {
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
|
||||
ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
|
||||
0, ret_payload);
|
||||
*value = ret_payload[1];
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,8 +50,6 @@ void handoff_setup(void);
|
|||
|
||||
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
|
||||
int zynqmp_mmio_read(const u32 address, u32 *value);
|
||||
int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
|
||||
u32 *ret_payload);
|
||||
|
||||
void initialize_tcm(bool mode);
|
||||
void mem_map_fill(void);
|
||||
|
|
|
|||
|
|
@ -244,7 +244,7 @@ relocate_code:
|
|||
bneid r12, 1b
|
||||
addi r5, r5, 4 /* Increment to next loc - relocate code */
|
||||
|
||||
/* R23 points to the base address. */
|
||||
/* R23 points to the base address. */
|
||||
add r23, r0, r7 /* Move reloc addr to r23 */
|
||||
addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
|
||||
rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */
|
||||
|
|
|
|||
|
|
@ -66,12 +66,15 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
|
|||
|
||||
thekernel = (void (*)(char *, ulong, ulong))images->ep;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("## Transferring control to Linux (at address 0x%08lx) ",
|
||||
(ulong)thekernel);
|
||||
printf("cmdline 0x%08lx, ramdisk 0x%08lx, FDT 0x%08lx...\n",
|
||||
cmdline, rd_start, dt);
|
||||
#endif
|
||||
debug("## Transferring control to Linux (at address 0x%08lx) ",
|
||||
(ulong)thekernel);
|
||||
debug("cmdline 0x%08lx, ramdisk 0x%08lx, FDT 0x%08lx...\n",
|
||||
cmdline, rd_start, dt);
|
||||
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
|
||||
|
||||
printf("\nStarting kernel ...%s\n\n", fake ?
|
||||
"(fake run for tracing)" : "");
|
||||
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
|
||||
|
||||
#ifdef XILINX_USE_DCACHE
|
||||
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
|
||||
|
|
@ -92,7 +95,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
|
|||
static void boot_prep_linux(bootm_headers_t *images)
|
||||
{
|
||||
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
|
||||
printf("using: FDT\n");
|
||||
debug("using: FDT\n");
|
||||
if (image_setup_linux(images)) {
|
||||
printf("FDT creation failed! hanging...");
|
||||
hang();
|
||||
|
|
|
|||
|
|
@ -19,13 +19,6 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -51,8 +51,8 @@ static int do_zynqmp_verify_secure(cmd_tbl_t *cmdtp, int flag, int argc,
|
|||
(ulong)(key_ptr + KEY_PTR_LEN));
|
||||
}
|
||||
|
||||
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD, src_lo, src_hi,
|
||||
key_lo, key_hi, ret_payload);
|
||||
ret = xilinx_pm_request(PM_SECURE_IMAGE, src_lo, src_hi,
|
||||
key_lo, key_hi, ret_payload);
|
||||
if (ret) {
|
||||
printf("Failed: secure op status:0x%x\n", ret);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -496,6 +496,11 @@ void fixup_cmdtable(cmd_tbl_t *cmdtp, int size)
|
|||
for (i = 0; i < size; i++) {
|
||||
ulong addr;
|
||||
|
||||
addr = (ulong)(cmdtp->cmd_rep) + gd->reloc_off;
|
||||
cmdtp->cmd_rep =
|
||||
(int (*)(struct cmd_tbl_s *, int, int,
|
||||
char * const [], int *))addr;
|
||||
|
||||
addr = (ulong)(cmdtp->cmd) + gd->reloc_off;
|
||||
#ifdef DEBUG_COMMANDS
|
||||
printf("Command \"%s\": 0x%08lx => 0x%08lx\n",
|
||||
|
|
|
|||
|
|
@ -30,6 +30,12 @@
|
|||
#include <u-boot/sha256.h>
|
||||
#include <u-boot/md5.h>
|
||||
|
||||
#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#endif
|
||||
|
||||
static void reloc_update(void);
|
||||
|
||||
#if defined(CONFIG_SHA1) && !defined(CONFIG_SHA_PROG_HW_ACCEL)
|
||||
static int hash_init_sha1(struct hash_algo *algo, void **ctxp)
|
||||
{
|
||||
|
|
@ -215,10 +221,31 @@ static struct hash_algo hash_algo[] = {
|
|||
#define multi_hash() 0
|
||||
#endif
|
||||
|
||||
static void reloc_update(void)
|
||||
{
|
||||
#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
|
||||
int i;
|
||||
static bool done;
|
||||
|
||||
if (!done) {
|
||||
done = true;
|
||||
for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
|
||||
hash_algo[i].name += gd->reloc_off;
|
||||
hash_algo[i].hash_func_ws += gd->reloc_off;
|
||||
hash_algo[i].hash_init += gd->reloc_off;
|
||||
hash_algo[i].hash_update += gd->reloc_off;
|
||||
hash_algo[i].hash_finish += gd->reloc_off;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
int hash_lookup_algo(const char *algo_name, struct hash_algo **algop)
|
||||
{
|
||||
int i;
|
||||
|
||||
reloc_update();
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
|
||||
if (!strcmp(algo_name, hash_algo[i].name)) {
|
||||
*algop = &hash_algo[i];
|
||||
|
|
@ -235,6 +262,8 @@ int hash_progressive_lookup_algo(const char *algo_name,
|
|||
{
|
||||
int i;
|
||||
|
||||
reloc_update();
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
|
||||
if (!strcmp(algo_name, hash_algo[i].name)) {
|
||||
if (hash_algo[i].hash_init) {
|
||||
|
|
|
|||
|
|
@ -89,6 +89,21 @@ struct checksum_algo *image_get_checksum_algo(const char *full_name)
|
|||
int i;
|
||||
const char *name;
|
||||
|
||||
#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
|
||||
static bool done;
|
||||
|
||||
if (!done) {
|
||||
done = true;
|
||||
for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
|
||||
checksum_algos[i].name += gd->reloc_off;
|
||||
#if IMAGE_ENABLE_SIGN
|
||||
checksum_algos[i].calculate_sign += gd->reloc_off;
|
||||
#endif
|
||||
checksum_algos[i].calculate += gd->reloc_off;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
|
||||
name = checksum_algos[i].name;
|
||||
/* Make sure names match and next char is a comma */
|
||||
|
|
@ -105,6 +120,20 @@ struct crypto_algo *image_get_crypto_algo(const char *full_name)
|
|||
int i;
|
||||
const char *name;
|
||||
|
||||
#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
|
||||
static bool done;
|
||||
|
||||
if (!done) {
|
||||
done = true;
|
||||
for (i = 0; i < ARRAY_SIZE(crypto_algos); i++) {
|
||||
crypto_algos[i].name += gd->reloc_off;
|
||||
crypto_algos[i].sign += gd->reloc_off;
|
||||
crypto_algos[i].add_verify_data += gd->reloc_off;
|
||||
crypto_algos[i].verify += gd->reloc_off;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Move name to after the comma */
|
||||
name = strchr(full_name, ',');
|
||||
if (!name)
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ CONFIG_SUPPORT_EMMC_BOOT=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ CONFIG_SYS_ICACHE_OFF=y
|
|||
CONFIG_ARCH_VERSAL=y
|
||||
CONFIG_SYS_TEXT_BASE=0xFFFC0000
|
||||
CONFIG_ENV_SIZE=0x80
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000
|
||||
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
|
||||
CONFIG_COUNTER_FREQUENCY=2720000
|
||||
|
|
@ -20,7 +20,6 @@ CONFIG_BOARD_EARLY_INIT_R=y
|
|||
# CONFIG_SYS_LONGHELP is not set
|
||||
CONFIG_SYS_PROMPT="Versal> "
|
||||
# CONFIG_AUTOBOOT is not set
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_BOOTM is not set
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_VERSAL=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x100000
|
||||
CONFIG_COUNTER_FREQUENCY=62500000
|
||||
CONFIG_ENV_VARS_UBOOT_CONFIG=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_BOOTDELAY=-1
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
# CONFIG_BOARD_LATE_INIT is not set
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
|
|
@ -17,11 +17,15 @@ CONFIG_SYS_PROMPT="Versal> "
|
|||
CONFIG_CMD_BOOTMENU=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_DM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
|
@ -43,11 +47,19 @@ CONFIG_NET_RANDOM_ETHADDR=y
|
|||
CONFIG_IP_DEFRAG=y
|
||||
CONFIG_TFTP_BLOCKSIZE=4096
|
||||
CONFIG_CLK_VERSAL=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_VERSALPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
|
|
@ -68,5 +80,23 @@ CONFIG_ZYNQ_GEM=y
|
|||
CONFIG_PL01X_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ CONFIG_CMD_TIMER=y
|
|||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA"
|
||||
CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-a2197-g-revA zynqmp-a2197-p-revA zynqmp-a2197-m-revA"
|
||||
CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-g-a2197-00-revA zynqmp-p-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ CONFIG_CMD_TIME=y
|
|||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-m-revA"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-e-a2197-00-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
|
|
@ -42,7 +42,7 @@ CONFIG_CMD_TIME=y
|
|||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-g-revA"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-g-a2197-00-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
115
configs/xilinx_zynqmp_m_a2197_01_revA_defconfig
Normal file
115
configs/xilinx_zynqmp_m_a2197_01_revA_defconfig
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-01-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_ZYNQMP=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
115
configs/xilinx_zynqmp_m_a2197_02_revA_defconfig
Normal file
115
configs/xilinx_zynqmp_m_a2197_02_revA_defconfig
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-02-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_ZYNQMP=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
115
configs/xilinx_zynqmp_m_a2197_03_revA_defconfig
Normal file
115
configs/xilinx_zynqmp_m_a2197_03_revA_defconfig
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_SYS_ALT_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-03-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_XILINX_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_ZYNQMP=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
|
||||
CONFIG_USB_FUNCTION_THOR=y
|
||||
CONFIG_SPL_GZIP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
51
configs/xilinx_zynqmp_mini_nand_single_defconfig
Normal file
51
configs/xilinx_zynqmp_mini_nand_single_defconfig
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_nand"
|
||||
CONFIG_SYS_ICACHE_OFF=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x10000
|
||||
CONFIG_ENV_SIZE=0x80
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_CMD_ZYNQMP is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
# CONFIG_BOARD_LATE_INIT is not set
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
# CONFIG_CMDLINE_EDITING is not set
|
||||
# CONFIG_AUTO_COMPLETE is not set
|
||||
# CONFIG_SYS_LONGHELP is not set
|
||||
# CONFIG_AUTOBOOT is not set
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_BOOTM is not set
|
||||
# CONFIG_CMD_BOOTI is not set
|
||||
# CONFIG_CMD_GO is not set
|
||||
# CONFIG_CMD_RUN is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_SAVEENV is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
# CONFIG_CMD_DM is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
# CONFIG_CMD_ECHO is not set
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SOURCE is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_MP is not set
|
||||
# CONFIG_PARTITIONS is not set
|
||||
CONFIG_OF_EMBED=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
|
||||
# CONFIG_NET is not set
|
||||
# CONFIG_DM_WARN is not set
|
||||
# CONFIG_DM_DEVICE_REMOVE is not set
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_NAND=y
|
||||
CONFIG_NAND_ARASAN=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
@ -55,11 +55,13 @@ CONFIG_SPL_DM=y
|
|||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ CONFIG_CMD_TIME=y
|
|||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-p-revA"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-p-a2197-00-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
|
|
@ -36,6 +36,7 @@ CONFIG_FPGA_ZYNQMPPL=y
|
|||
CONFIG_MISC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ CONFIG_FPGA_ZYNQMPPL=y
|
|||
CONFIG_MISC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ CONFIG_MMC_HS200_SUPPORT=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ CONFIG_MISC=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ CONFIG_MISC=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@ CONFIG_MMC_UHS_SUPPORT=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -62,6 +62,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -60,6 +60,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ CONFIG_FPGA_ZYNQMPPL=y
|
|||
CONFIG_MISC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ CONFIG_MISC=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
@ -46,6 +47,10 @@ CONFIG_SPI_FLASH_STMICRO=y
|
|||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_PHY_XILINX_GMII2RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
|
|
|
|||
98
configs/xilinx_zynqmp_zcu216_revA_defconfig
Normal file
98
configs/xilinx_zynqmp_zcu216_revA_defconfig
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xff000000
|
||||
CONFIG_DEBUG_UART_CLOCK=100000000
|
||||
CONFIG_ZYNQMP_USB=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_RAM_SUPPORT=y
|
||||
CONFIG_SPL_RAM_DEVICE=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADP=y
|
||||
CONFIG_CMD_FPGA_LOAD_SECURE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA"
|
||||
CONFIG_ENV_IS_IN_FAT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_CLK_ZYNQMP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_FPGA_XILINX=y
|
||||
CONFIG_FPGA_ZYNQMPPL=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_CADENCE=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x0
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ZYNQ=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SF_DUAL_FLASH=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_ZYNQ_GEM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DEBUG_UART_ZYNQ=y
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_ZYNQ_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ZYNQMP_GQSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_XHCI_ZYNQMP=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GADGET=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -18,6 +18,7 @@ CONFIG_USE_PREBOOT=y
|
|||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
|||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_BOOTM is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_FDT is not set
|
||||
# CONFIG_CMD_GO is not set
|
||||
# CONFIG_CMD_RUN is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
|
|
@ -41,6 +42,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
|||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_SAVEENV is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
# CONFIG_CMD_CLK is not set
|
||||
# CONFIG_CMD_DM is not set
|
||||
|
|
@ -67,6 +69,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
|
|||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DEBUG_UART_ARM_DCC=y
|
||||
CONFIG_ZYNQ_QSPI=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
|
|||
|
|
@ -16,11 +16,11 @@ CONFIG_FIT_SIGNATURE=y
|
|||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ CONFIG_SPL_STACK_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ CONFIG_FIT_VERBOSE=y
|
|||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
|
|||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ CONFIG_SPL_STACK_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_DFU=y
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_SPL_STACK_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ CONFIG_SPL_STACK_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_DFU=y
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ CONFIG_SPL_FPGA_SUPPORT=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ CONFIG_SPL_STACK_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADFS=y
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
|
|||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADFS=y
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
|
|||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADFS=y
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
|
|||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADFS=y
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ CONFIG_SPL_STACK_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FPGA_LOADBP=y
|
||||
CONFIG_CMD_FPGA_LOADFS=y
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_SPL_STACK_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_SPL_STACK_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_SPL_STACK_R=y
|
|||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_THOR_DOWNLOAD=y
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <zynqmp_firmware.h>
|
||||
|
||||
#define MAX_PARENT 100
|
||||
#define MAX_NODES 6
|
||||
|
|
@ -362,7 +363,7 @@ static u32 versal_clock_get_div(u32 clk_id)
|
|||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
u32 div;
|
||||
|
||||
versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
|
||||
xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
|
||||
div = ret_payload[1];
|
||||
|
||||
return div;
|
||||
|
|
@ -372,7 +373,7 @@ static u32 versal_clock_set_div(u32 clk_id, u32 div)
|
|||
{
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
|
||||
versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
|
||||
xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
|
||||
|
||||
return div;
|
||||
}
|
||||
|
|
@ -382,7 +383,7 @@ static u64 versal_clock_ref(u32 clk_id)
|
|||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
int ref;
|
||||
|
||||
versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
|
||||
xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
|
||||
ref = ret_payload[0];
|
||||
if (!(ref & 1))
|
||||
return ref_clk;
|
||||
|
|
@ -401,7 +402,7 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
|
|||
u32 parent_rate, parent_id;
|
||||
u32 id = clk_id & 0xFFF;
|
||||
|
||||
versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
|
||||
xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
|
||||
res = ret_payload[1];
|
||||
if (!res) {
|
||||
printf("0%x PLL not enabled\n", clk_id);
|
||||
|
|
@ -411,9 +412,9 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
|
|||
parent_id = clock[clock[id].parent[0].id].clk_id;
|
||||
parent_rate = versal_clock_ref(parent_id);
|
||||
|
||||
versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
|
||||
xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
|
||||
fbdiv = ret_payload[1];
|
||||
versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
|
||||
xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
|
||||
frac = ret_payload[1];
|
||||
|
||||
freq = (fbdiv * parent_rate) >> (1 << frac);
|
||||
|
|
@ -440,7 +441,7 @@ static u32 versal_clock_get_parentid(u32 clk_id)
|
|||
u32 id = clk_id & 0xFFF;
|
||||
|
||||
if (versal_clock_mux(clk_id)) {
|
||||
versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
|
||||
xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
|
||||
ret_payload);
|
||||
parent_id = ret_payload[1];
|
||||
}
|
||||
|
|
|
|||
|
|
@ -702,7 +702,6 @@ static struct clk_ops zynqmp_clk_ops = {
|
|||
|
||||
static const struct udevice_id zynqmp_clk_ids[] = {
|
||||
{ .compatible = "xlnx,zynqmp-clk" },
|
||||
{ .compatible = "xlnx,zynqmp-clkc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -13,10 +13,23 @@
|
|||
#include <asm/io.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#endif
|
||||
|
||||
int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
|
||||
struct key_prop *node, uint8_t *out)
|
||||
{
|
||||
const struct mod_exp_ops *ops = device_get_ops(dev);
|
||||
struct mod_exp_ops *ops = (struct mod_exp_ops *)device_get_ops(dev);
|
||||
|
||||
#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
|
||||
static bool done;
|
||||
|
||||
if (!done) {
|
||||
done = true;
|
||||
ops->mod_exp += gd->reloc_off;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (!ops->mod_exp)
|
||||
return -ENOSYS;
|
||||
|
|
|
|||
|
|
@ -7,10 +7,10 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <zynqmp_firmware.h>
|
||||
|
||||
#if defined(CONFIG_ZYNQMP_IPI)
|
||||
#include <mailbox.h>
|
||||
#include <zynqmp_firmware.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
#define PMUFW_PAYLOAD_ARG_CNT 8
|
||||
|
|
@ -54,7 +54,7 @@ static int send_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
|
|||
if (IS_ENABLED(CONFIG_SPL_BUILD))
|
||||
return ipi_req(req, req_len, res, res_maxlen);
|
||||
|
||||
return invoke_smc(req[0] + PM_SIP_SVC, 0, 0, 0, 0, res);
|
||||
return xilinx_pm_request(req[0], 0, 0, 0, 0, res);
|
||||
}
|
||||
|
||||
unsigned int zynqmp_firmware_version(void)
|
||||
|
|
@ -110,19 +110,19 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
|
|||
|
||||
static int zynqmp_power_probe(struct udevice *dev)
|
||||
{
|
||||
int ret = 0;
|
||||
int ret;
|
||||
|
||||
debug("%s, (dev=%p)\n", __func__, dev);
|
||||
|
||||
ret = mbox_get_by_name(dev, "tx", &zynqmp_power.tx_chan);
|
||||
if (ret) {
|
||||
debug("%s, cannot tx mailbox\n", __func__);
|
||||
debug("%s: Cannot find tx mailbox\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mbox_get_by_name(dev, "rx", &zynqmp_power.rx_chan);
|
||||
if (ret) {
|
||||
debug("%s, cannot rx mailbox\n", __func__);
|
||||
debug("%s: Cannot find rx mailbox\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -147,6 +147,37 @@ U_BOOT_DRIVER(zynqmp_power) = {
|
|||
};
|
||||
#endif
|
||||
|
||||
int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
|
||||
u32 arg3, u32 *ret_payload)
|
||||
{
|
||||
/*
|
||||
* Added SIP service call Function Identifier
|
||||
* Make sure to stay in x0 register
|
||||
*/
|
||||
struct pt_regs regs;
|
||||
|
||||
if (current_el() == 3) {
|
||||
printf("%s: Can't call SMC from EL3 context\n", __func__);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
regs.regs[0] = PM_SIP_SVC | api_id;
|
||||
regs.regs[1] = ((u64)arg1 << 32) | arg0;
|
||||
regs.regs[2] = ((u64)arg3 << 32) | arg2;
|
||||
|
||||
smc_call(®s);
|
||||
|
||||
if (ret_payload) {
|
||||
ret_payload[0] = (u32)regs.regs[0];
|
||||
ret_payload[1] = upper_32_bits(regs.regs[0]);
|
||||
ret_payload[2] = (u32)regs.regs[1];
|
||||
ret_payload[3] = upper_32_bits(regs.regs[1]);
|
||||
ret_payload[4] = (u32)regs.regs[2];
|
||||
}
|
||||
|
||||
return regs.regs[0];
|
||||
}
|
||||
|
||||
static const struct udevice_id zynqmp_firmware_ids[] = {
|
||||
{ .compatible = "xlnx,zynqmp-firmware" },
|
||||
{ .compatible = "xlnx,versal-firmware"},
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include <asm/arch/sys_proto.h>
|
||||
#include <memalign.h>
|
||||
#include <versalpl.h>
|
||||
#include <zynqmp_firmware.h>
|
||||
|
||||
static ulong versal_align_dma_buffer(ulong *buf, u32 len)
|
||||
{
|
||||
|
|
@ -38,7 +39,7 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
|
|||
buf_lo = lower_32_bits(bin_buf);
|
||||
buf_hi = upper_32_bits(bin_buf);
|
||||
|
||||
ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
|
||||
ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
|
||||
buf_hi, 0, ret_payload);
|
||||
if (ret)
|
||||
puts("PL FPGA LOAD fail\n");
|
||||
|
|
|
|||
|
|
@ -227,11 +227,12 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
|
|||
buf_hi = upper_32_bits(bin_buf);
|
||||
|
||||
if (xilfpga_old)
|
||||
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
|
||||
(u32)(uintptr_t)bsizeptr, bstype, ret_payload);
|
||||
ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
|
||||
buf_hi, (u32)(uintptr_t)bsizeptr,
|
||||
bstype, ret_payload);
|
||||
else
|
||||
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
|
||||
(u32)bsize, 0, ret_payload);
|
||||
ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
|
||||
buf_hi, (u32)bsize, 0, ret_payload);
|
||||
|
||||
if (ret)
|
||||
puts("PL FPGA LOAD fail\n");
|
||||
|
|
@ -272,7 +273,8 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
|
|||
buf_lo = lower_32_bits((ulong)buf);
|
||||
buf_hi = upper_32_bits((ulong)buf);
|
||||
|
||||
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
|
||||
ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo,
|
||||
buf_hi,
|
||||
(u32)(uintptr_t)fpga_sec_info->userkey_addr,
|
||||
flag, ret_payload);
|
||||
if (ret)
|
||||
|
|
@ -289,8 +291,8 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
|
|||
int ret;
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
|
||||
ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
|
||||
0, ret_payload);
|
||||
ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
|
||||
0, ret_payload);
|
||||
if (!ret)
|
||||
printf("PCAP status\t0x%x\n", ret_payload[1]);
|
||||
|
||||
|
|
|
|||
|
|
@ -301,7 +301,7 @@ config MVEBU_GPIO
|
|||
|
||||
config ZYNQ_GPIO
|
||||
bool "Zynq GPIO driver"
|
||||
depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP)
|
||||
depends on DM_GPIO && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL)
|
||||
default y
|
||||
help
|
||||
Supports GPIO access on Zynq SoC.
|
||||
|
|
|
|||
|
|
@ -93,6 +93,9 @@
|
|||
/* GPIO upper 16 bit mask */
|
||||
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
|
||||
|
||||
#define PMC_GPIO_NR_GPIOS 116
|
||||
#define PMC_GPIO_MAX_BANK 5
|
||||
|
||||
struct zynq_gpio_platdata {
|
||||
phys_addr_t base;
|
||||
const struct zynq_platform_data *p_data;
|
||||
|
|
@ -114,6 +117,33 @@ struct zynq_platform_data {
|
|||
u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
|
||||
};
|
||||
|
||||
#define VERSAL_GPIO_NR_GPIOS 58
|
||||
#define VERSAL_GPIO_MAX_BANK 4
|
||||
|
||||
static const struct zynq_platform_data versal_gpio_def = {
|
||||
.label = "versal_gpio",
|
||||
.ngpio = VERSAL_GPIO_NR_GPIOS,
|
||||
.max_bank = VERSAL_GPIO_MAX_BANK,
|
||||
.bank_min[0] = 0,
|
||||
.bank_max[0] = 25,
|
||||
.bank_min[3] = 26,
|
||||
.bank_max[3] = 57,
|
||||
};
|
||||
|
||||
static const struct zynq_platform_data pmc_gpio_def = {
|
||||
.label = "pmc_gpio",
|
||||
.ngpio = PMC_GPIO_NR_GPIOS,
|
||||
.max_bank = PMC_GPIO_MAX_BANK,
|
||||
.bank_min[0] = 0,
|
||||
.bank_max[0] = 25,
|
||||
.bank_min[1] = 26,
|
||||
.bank_max[1] = 51,
|
||||
.bank_min[3] = 52,
|
||||
.bank_max[3] = 83,
|
||||
.bank_min[4] = 84,
|
||||
.bank_max[4] = 115,
|
||||
};
|
||||
|
||||
static const struct zynq_platform_data zynqmp_gpio_def = {
|
||||
.label = "zynqmp_gpio",
|
||||
.ngpio = ZYNQMP_GPIO_NR_GPIOS,
|
||||
|
|
@ -329,6 +359,10 @@ static const struct udevice_id zynq_gpio_ids[] = {
|
|||
.data = (ulong)&zynq_gpio_def},
|
||||
{ .compatible = "xlnx,zynqmp-gpio-1.0",
|
||||
.data = (ulong)&zynqmp_gpio_def},
|
||||
{ .compatible = "xlnx,versal-gpio-1.0",
|
||||
.data = (ulong)&versal_gpio_def},
|
||||
{ .compatible = "xlnx,pmc-gpio-1.0",
|
||||
.data = (ulong)&pmc_gpio_def },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -6,8 +6,6 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <clk.h>
|
||||
|
|
|
|||
|
|
@ -227,8 +227,6 @@
|
|||
/* Boot FreeBSD/vxWorks from an ELF image */
|
||||
#define CONFIG_SYS_MMC_MAX_DEVICE 1
|
||||
|
||||
#undef CONFIG_BOOTM_NETBSD
|
||||
|
||||
/* MMC support */
|
||||
#ifdef CONFIG_MMC_SDHCI_ZYNQ
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
||||
|
|
|
|||
126
include/dt-bindings/clock/xlnx-zynqmp-clk.h
Normal file
126
include/dt-bindings/clock/xlnx-zynqmp-clk.h
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Xilinx Zynq MPSoC Firmware layer
|
||||
*
|
||||
* Copyright (C) 2014-2018 Xilinx, Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
|
||||
#define _DT_BINDINGS_CLK_ZYNQMP_H
|
||||
|
||||
#define IOPLL 0
|
||||
#define RPLL 1
|
||||
#define APLL 2
|
||||
#define DPLL 3
|
||||
#define VPLL 4
|
||||
#define IOPLL_TO_FPD 5
|
||||
#define RPLL_TO_FPD 6
|
||||
#define APLL_TO_LPD 7
|
||||
#define DPLL_TO_LPD 8
|
||||
#define VPLL_TO_LPD 9
|
||||
#define ACPU 10
|
||||
#define ACPU_HALF 11
|
||||
#define DBF_FPD 12
|
||||
#define DBF_LPD 13
|
||||
#define DBG_TRACE 14
|
||||
#define DBG_TSTMP 15
|
||||
#define DP_VIDEO_REF 16
|
||||
#define DP_AUDIO_REF 17
|
||||
#define DP_STC_REF 18
|
||||
#define GDMA_REF 19
|
||||
#define DPDMA_REF 20
|
||||
#define DDR_REF 21
|
||||
#define SATA_REF 22
|
||||
#define PCIE_REF 23
|
||||
#define GPU_REF 24
|
||||
#define GPU_PP0_REF 25
|
||||
#define GPU_PP1_REF 26
|
||||
#define TOPSW_MAIN 27
|
||||
#define TOPSW_LSBUS 28
|
||||
#define GTGREF0_REF 29
|
||||
#define LPD_SWITCH 30
|
||||
#define LPD_LSBUS 31
|
||||
#define USB0_BUS_REF 32
|
||||
#define USB1_BUS_REF 33
|
||||
#define USB3_DUAL_REF 34
|
||||
#define USB0 35
|
||||
#define USB1 36
|
||||
#define CPU_R5 37
|
||||
#define CPU_R5_CORE 38
|
||||
#define CSU_SPB 39
|
||||
#define CSU_PLL 40
|
||||
#define PCAP 41
|
||||
#define IOU_SWITCH 42
|
||||
#define GEM_TSU_REF 43
|
||||
#define GEM_TSU 44
|
||||
#define GEM0_TX 45
|
||||
#define GEM1_TX 46
|
||||
#define GEM2_TX 47
|
||||
#define GEM3_TX 48
|
||||
#define GEM0_RX 49
|
||||
#define GEM1_RX 50
|
||||
#define GEM2_RX 51
|
||||
#define GEM3_RX 52
|
||||
#define QSPI_REF 53
|
||||
#define SDIO0_REF 54
|
||||
#define SDIO1_REF 55
|
||||
#define UART0_REF 56
|
||||
#define UART1_REF 57
|
||||
#define SPI0_REF 58
|
||||
#define SPI1_REF 59
|
||||
#define NAND_REF 60
|
||||
#define I2C0_REF 61
|
||||
#define I2C1_REF 62
|
||||
#define CAN0_REF 63
|
||||
#define CAN1_REF 64
|
||||
#define CAN0 65
|
||||
#define CAN1 66
|
||||
#define DLL_REF 67
|
||||
#define ADMA_REF 68
|
||||
#define TIMESTAMP_REF 69
|
||||
#define AMS_REF 70
|
||||
#define PL0_REF 71
|
||||
#define PL1_REF 72
|
||||
#define PL2_REF 73
|
||||
#define PL3_REF 74
|
||||
#define WDT 75
|
||||
#define IOPLL_INT 76
|
||||
#define IOPLL_PRE_SRC 77
|
||||
#define IOPLL_HALF 78
|
||||
#define IOPLL_INT_MUX 79
|
||||
#define IOPLL_POST_SRC 80
|
||||
#define RPLL_INT 81
|
||||
#define RPLL_PRE_SRC 82
|
||||
#define RPLL_HALF 83
|
||||
#define RPLL_INT_MUX 84
|
||||
#define RPLL_POST_SRC 85
|
||||
#define APLL_INT 86
|
||||
#define APLL_PRE_SRC 87
|
||||
#define APLL_HALF 88
|
||||
#define APLL_INT_MUX 89
|
||||
#define APLL_POST_SRC 90
|
||||
#define DPLL_INT 91
|
||||
#define DPLL_PRE_SRC 92
|
||||
#define DPLL_HALF 93
|
||||
#define DPLL_INT_MUX 94
|
||||
#define DPLL_POST_SRC 95
|
||||
#define VPLL_INT 96
|
||||
#define VPLL_PRE_SRC 97
|
||||
#define VPLL_HALF 98
|
||||
#define VPLL_INT_MUX 99
|
||||
#define VPLL_POST_SRC 100
|
||||
#define CAN0_MIO 101
|
||||
#define CAN1_MIO 102
|
||||
#define ACPU_FULL 103
|
||||
#define GEM0_REF 104
|
||||
#define GEM1_REF 105
|
||||
#define GEM2_REF 106
|
||||
#define GEM3_REF 107
|
||||
#define GEM0_REF_UNG 108
|
||||
#define GEM1_REF_UNG 109
|
||||
#define GEM2_REF_UNG 110
|
||||
#define GEM3_REF_UNG 111
|
||||
#define LPD_WDT 112
|
||||
|
||||
#endif
|
||||
39
include/dt-bindings/power/xlnx-zynqmp-power.h
Normal file
39
include/dt-bindings/power/xlnx-zynqmp-power.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Xilinx, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
|
||||
#define _DT_BINDINGS_ZYNQMP_POWER_H
|
||||
|
||||
#define PD_USB_0 22
|
||||
#define PD_USB_1 23
|
||||
#define PD_TTC_0 24
|
||||
#define PD_TTC_1 25
|
||||
#define PD_TTC_2 26
|
||||
#define PD_TTC_3 27
|
||||
#define PD_SATA 28
|
||||
#define PD_ETH_0 29
|
||||
#define PD_ETH_1 30
|
||||
#define PD_ETH_2 31
|
||||
#define PD_ETH_3 32
|
||||
#define PD_UART_0 33
|
||||
#define PD_UART_1 34
|
||||
#define PD_SPI_0 35
|
||||
#define PD_SPI_1 36
|
||||
#define PD_I2C_0 37
|
||||
#define PD_I2C_1 38
|
||||
#define PD_SD_0 39
|
||||
#define PD_SD_1 40
|
||||
#define PD_DP 41
|
||||
#define PD_GDMA 42
|
||||
#define PD_ADMA 43
|
||||
#define PD_NAND 44
|
||||
#define PD_QSPI 45
|
||||
#define PD_GPIO 46
|
||||
#define PD_CAN_0 47
|
||||
#define PD_CAN_1 48
|
||||
#define PD_GPU 58
|
||||
#define PD_PCIE 59
|
||||
|
||||
#endif
|
||||
130
include/dt-bindings/reset/xlnx-zynqmp-resets.h
Normal file
130
include/dt-bindings/reset/xlnx-zynqmp-resets.h
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Xilinx, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
|
||||
#define _DT_BINDINGS_ZYNQMP_RESETS_H
|
||||
|
||||
#define ZYNQMP_RESET_PCIE_CFG 0
|
||||
#define ZYNQMP_RESET_PCIE_BRIDGE 1
|
||||
#define ZYNQMP_RESET_PCIE_CTRL 2
|
||||
#define ZYNQMP_RESET_DP 3
|
||||
#define ZYNQMP_RESET_SWDT_CRF 4
|
||||
#define ZYNQMP_RESET_AFI_FM5 5
|
||||
#define ZYNQMP_RESET_AFI_FM4 6
|
||||
#define ZYNQMP_RESET_AFI_FM3 7
|
||||
#define ZYNQMP_RESET_AFI_FM2 8
|
||||
#define ZYNQMP_RESET_AFI_FM1 9
|
||||
#define ZYNQMP_RESET_AFI_FM0 10
|
||||
#define ZYNQMP_RESET_GDMA 11
|
||||
#define ZYNQMP_RESET_GPU_PP1 12
|
||||
#define ZYNQMP_RESET_GPU_PP0 13
|
||||
#define ZYNQMP_RESET_GPU 14
|
||||
#define ZYNQMP_RESET_GT 15
|
||||
#define ZYNQMP_RESET_SATA 16
|
||||
#define ZYNQMP_RESET_ACPU3_PWRON 17
|
||||
#define ZYNQMP_RESET_ACPU2_PWRON 18
|
||||
#define ZYNQMP_RESET_ACPU1_PWRON 19
|
||||
#define ZYNQMP_RESET_ACPU0_PWRON 20
|
||||
#define ZYNQMP_RESET_APU_L2 21
|
||||
#define ZYNQMP_RESET_ACPU3 22
|
||||
#define ZYNQMP_RESET_ACPU2 23
|
||||
#define ZYNQMP_RESET_ACPU1 24
|
||||
#define ZYNQMP_RESET_ACPU0 25
|
||||
#define ZYNQMP_RESET_DDR 26
|
||||
#define ZYNQMP_RESET_APM_FPD 27
|
||||
#define ZYNQMP_RESET_SOFT 28
|
||||
#define ZYNQMP_RESET_GEM0 29
|
||||
#define ZYNQMP_RESET_GEM1 30
|
||||
#define ZYNQMP_RESET_GEM2 31
|
||||
#define ZYNQMP_RESET_GEM3 32
|
||||
#define ZYNQMP_RESET_QSPI 33
|
||||
#define ZYNQMP_RESET_UART0 34
|
||||
#define ZYNQMP_RESET_UART1 35
|
||||
#define ZYNQMP_RESET_SPI0 36
|
||||
#define ZYNQMP_RESET_SPI1 37
|
||||
#define ZYNQMP_RESET_SDIO0 38
|
||||
#define ZYNQMP_RESET_SDIO1 39
|
||||
#define ZYNQMP_RESET_CAN0 40
|
||||
#define ZYNQMP_RESET_CAN1 41
|
||||
#define ZYNQMP_RESET_I2C0 42
|
||||
#define ZYNQMP_RESET_I2C1 43
|
||||
#define ZYNQMP_RESET_TTC0 44
|
||||
#define ZYNQMP_RESET_TTC1 45
|
||||
#define ZYNQMP_RESET_TTC2 46
|
||||
#define ZYNQMP_RESET_TTC3 47
|
||||
#define ZYNQMP_RESET_SWDT_CRL 48
|
||||
#define ZYNQMP_RESET_NAND 49
|
||||
#define ZYNQMP_RESET_ADMA 50
|
||||
#define ZYNQMP_RESET_GPIO 51
|
||||
#define ZYNQMP_RESET_IOU_CC 52
|
||||
#define ZYNQMP_RESET_TIMESTAMP 53
|
||||
#define ZYNQMP_RESET_RPU_R50 54
|
||||
#define ZYNQMP_RESET_RPU_R51 55
|
||||
#define ZYNQMP_RESET_RPU_AMBA 56
|
||||
#define ZYNQMP_RESET_OCM 57
|
||||
#define ZYNQMP_RESET_RPU_PGE 58
|
||||
#define ZYNQMP_RESET_USB0_CORERESET 59
|
||||
#define ZYNQMP_RESET_USB1_CORERESET 60
|
||||
#define ZYNQMP_RESET_USB0_HIBERRESET 61
|
||||
#define ZYNQMP_RESET_USB1_HIBERRESET 62
|
||||
#define ZYNQMP_RESET_USB0_APB 63
|
||||
#define ZYNQMP_RESET_USB1_APB 64
|
||||
#define ZYNQMP_RESET_IPI 65
|
||||
#define ZYNQMP_RESET_APM_LPD 66
|
||||
#define ZYNQMP_RESET_RTC 67
|
||||
#define ZYNQMP_RESET_SYSMON 68
|
||||
#define ZYNQMP_RESET_AFI_FM6 69
|
||||
#define ZYNQMP_RESET_LPD_SWDT 70
|
||||
#define ZYNQMP_RESET_FPD 71
|
||||
#define ZYNQMP_RESET_RPU_DBG1 72
|
||||
#define ZYNQMP_RESET_RPU_DBG0 73
|
||||
#define ZYNQMP_RESET_DBG_LPD 74
|
||||
#define ZYNQMP_RESET_DBG_FPD 75
|
||||
#define ZYNQMP_RESET_APLL 76
|
||||
#define ZYNQMP_RESET_DPLL 77
|
||||
#define ZYNQMP_RESET_VPLL 78
|
||||
#define ZYNQMP_RESET_IOPLL 79
|
||||
#define ZYNQMP_RESET_RPLL 80
|
||||
#define ZYNQMP_RESET_GPO3_PL_0 81
|
||||
#define ZYNQMP_RESET_GPO3_PL_1 82
|
||||
#define ZYNQMP_RESET_GPO3_PL_2 83
|
||||
#define ZYNQMP_RESET_GPO3_PL_3 84
|
||||
#define ZYNQMP_RESET_GPO3_PL_4 85
|
||||
#define ZYNQMP_RESET_GPO3_PL_5 86
|
||||
#define ZYNQMP_RESET_GPO3_PL_6 87
|
||||
#define ZYNQMP_RESET_GPO3_PL_7 88
|
||||
#define ZYNQMP_RESET_GPO3_PL_8 89
|
||||
#define ZYNQMP_RESET_GPO3_PL_9 90
|
||||
#define ZYNQMP_RESET_GPO3_PL_10 91
|
||||
#define ZYNQMP_RESET_GPO3_PL_11 92
|
||||
#define ZYNQMP_RESET_GPO3_PL_12 93
|
||||
#define ZYNQMP_RESET_GPO3_PL_13 94
|
||||
#define ZYNQMP_RESET_GPO3_PL_14 95
|
||||
#define ZYNQMP_RESET_GPO3_PL_15 96
|
||||
#define ZYNQMP_RESET_GPO3_PL_16 97
|
||||
#define ZYNQMP_RESET_GPO3_PL_17 98
|
||||
#define ZYNQMP_RESET_GPO3_PL_18 99
|
||||
#define ZYNQMP_RESET_GPO3_PL_19 100
|
||||
#define ZYNQMP_RESET_GPO3_PL_20 101
|
||||
#define ZYNQMP_RESET_GPO3_PL_21 102
|
||||
#define ZYNQMP_RESET_GPO3_PL_22 103
|
||||
#define ZYNQMP_RESET_GPO3_PL_23 104
|
||||
#define ZYNQMP_RESET_GPO3_PL_24 105
|
||||
#define ZYNQMP_RESET_GPO3_PL_25 106
|
||||
#define ZYNQMP_RESET_GPO3_PL_26 107
|
||||
#define ZYNQMP_RESET_GPO3_PL_27 108
|
||||
#define ZYNQMP_RESET_GPO3_PL_28 109
|
||||
#define ZYNQMP_RESET_GPO3_PL_29 110
|
||||
#define ZYNQMP_RESET_GPO3_PL_30 111
|
||||
#define ZYNQMP_RESET_GPO3_PL_31 112
|
||||
#define ZYNQMP_RESET_RPU_LS 113
|
||||
#define ZYNQMP_RESET_PS_ONLY 114
|
||||
#define ZYNQMP_RESET_PL 115
|
||||
#define ZYNQMP_RESET_PS_PL0 116
|
||||
#define ZYNQMP_RESET_PS_PL1 117
|
||||
#define ZYNQMP_RESET_PS_PL2 118
|
||||
#define ZYNQMP_RESET_PS_PL3 119
|
||||
|
||||
#endif
|
||||
|
|
@ -11,12 +11,58 @@
|
|||
enum pm_api_id {
|
||||
PM_GET_API_VERSION = 1,
|
||||
PM_SET_CONFIGURATION,
|
||||
PM_SECURE_IMAGE = 45,
|
||||
PM_GET_NODE_STATUS,
|
||||
PM_GET_OPERATING_CHARACTERISTIC,
|
||||
PM_REGISTER_NOTIFIER,
|
||||
PM_REQUEST_SUSPEND,
|
||||
PM_SELF_SUSPEND,
|
||||
PM_FORCE_POWERDOWN,
|
||||
PM_ABORT_SUSPEND,
|
||||
PM_REQUEST_WAKEUP,
|
||||
PM_SET_WAKEUP_SOURCE,
|
||||
PM_SYSTEM_SHUTDOWN,
|
||||
PM_REQUEST_NODE,
|
||||
PM_RELEASE_NODE,
|
||||
PM_SET_REQUIREMENT,
|
||||
PM_SET_MAX_LATENCY,
|
||||
PM_RESET_ASSERT,
|
||||
PM_RESET_GET_STATUS,
|
||||
PM_MMIO_WRITE,
|
||||
PM_MMIO_READ,
|
||||
PM_PM_INIT_FINALIZE,
|
||||
PM_FPGA_LOAD,
|
||||
PM_FPGA_GET_STATUS,
|
||||
PM_GET_CHIPID,
|
||||
PM_SECURE_SHA = 26,
|
||||
PM_SECURE_RSA,
|
||||
PM_PINCTRL_REQUEST,
|
||||
PM_PINCTRL_RELEASE,
|
||||
PM_PINCTRL_GET_FUNCTION,
|
||||
PM_PINCTRL_SET_FUNCTION,
|
||||
PM_PINCTRL_CONFIG_PARAM_GET,
|
||||
PM_PINCTRL_CONFIG_PARAM_SET,
|
||||
PM_IOCTL,
|
||||
PM_QUERY_DATA,
|
||||
PM_CLOCK_ENABLE,
|
||||
PM_CLOCK_DISABLE,
|
||||
PM_CLOCK_GETSTATE,
|
||||
PM_CLOCK_SETDIVIDER,
|
||||
PM_CLOCK_GETDIVIDER,
|
||||
PM_CLOCK_SETRATE,
|
||||
PM_CLOCK_GETRATE,
|
||||
PM_CLOCK_SETPARENT,
|
||||
PM_CLOCK_GETPARENT,
|
||||
PM_SECURE_IMAGE,
|
||||
PM_FPGA_READ = 46,
|
||||
PM_SECURE_AES,
|
||||
PM_CLOCK_PLL_GETPARAM = 49,
|
||||
PM_REGISTER_ACCESS = 52,
|
||||
PM_EFUSE_ACCESS,
|
||||
PM_FEATURE_CHECK = 63,
|
||||
PM_API_MAX,
|
||||
};
|
||||
|
||||
#define PM_SIP_SVC 0xc2000000
|
||||
#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD \
|
||||
(PM_SIP_SVC + PM_SECURE_IMAGE)
|
||||
|
||||
#define ZYNQMP_PM_VERSION_MAJOR 1
|
||||
#define ZYNQMP_PM_VERSION_MINOR 0
|
||||
|
|
@ -33,5 +79,7 @@ enum pm_api_id {
|
|||
|
||||
unsigned int zynqmp_firmware_version(void);
|
||||
void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
|
||||
int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
|
||||
u32 arg3, u32 *ret_payload);
|
||||
|
||||
#endif /* _ZYNQMP_FIRMWARE_H_ */
|
||||
|
|
|
|||
|
|
@ -64,7 +64,6 @@ psu_..._protection
|
|||
psu_init_xppu_aper_ram
|
||||
mask_delay(u32
|
||||
mask_read(u32
|
||||
dpll_prog
|
||||
mask_poll(u32
|
||||
mask_pollonvalue(u32
|
||||
psu_ps_pl_reset_config_data
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue