mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
commit
e3bf81b1e8
26 changed files with 389 additions and 60 deletions
|
@ -49,23 +49,23 @@ int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
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#ifdef CONFIG_SYS_DPAA_FMAN
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struct liodn_id_table fman1_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(1, 0, 6),
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SET_FMAN_RX_1G_LIODN(1, 1, 7),
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SET_FMAN_RX_1G_LIODN(1, 2, 8),
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SET_FMAN_RX_1G_LIODN(1, 3, 9),
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SET_FMAN_RX_1G_LIODN(1, 4, 10),
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SET_FMAN_RX_10G_LIODN(1, 0, 11),
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SET_FMAN_RX_1G_LIODN(1, 0, 11),
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SET_FMAN_RX_1G_LIODN(1, 1, 12),
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SET_FMAN_RX_1G_LIODN(1, 2, 13),
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SET_FMAN_RX_1G_LIODN(1, 3, 14),
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SET_FMAN_RX_1G_LIODN(1, 4, 15),
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SET_FMAN_RX_10G_LIODN(1, 0, 16),
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};
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int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
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#if (CONFIG_SYS_NUM_FMAN == 2)
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struct liodn_id_table fman2_liodn_tbl[] = {
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SET_FMAN_RX_1G_LIODN(2, 0, 12),
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SET_FMAN_RX_1G_LIODN(2, 1, 13),
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SET_FMAN_RX_1G_LIODN(2, 2, 14),
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SET_FMAN_RX_1G_LIODN(2, 3, 15),
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SET_FMAN_RX_1G_LIODN(2, 4, 16),
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SET_FMAN_RX_10G_LIODN(2, 0, 17),
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SET_FMAN_RX_1G_LIODN(2, 0, 17),
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SET_FMAN_RX_1G_LIODN(2, 1, 18),
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SET_FMAN_RX_1G_LIODN(2, 2, 19),
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SET_FMAN_RX_1G_LIODN(2, 3, 20),
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SET_FMAN_RX_1G_LIODN(2, 4, 21),
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SET_FMAN_RX_10G_LIODN(2, 0, 22),
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};
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int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
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#endif
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@ -14,9 +14,46 @@
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
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#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
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static void inhibit_portals(void __iomem *addr, int max_portals,
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int arch_max_portals, int portal_cinh_size)
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{
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uint32_t val;
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int i;
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/* arch_max_portals is the maximum based on memory size. This includes
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* the reserved memory in the SoC. max_portals the number of physical
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* portals in the SoC */
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if (max_portals > arch_max_portals) {
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printf("ERROR: portal config error\n");
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max_portals = arch_max_portals;
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}
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for (i = 0; i < max_portals; i++) {
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out_be32(addr, -1);
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val = in_be32(addr);
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if (!val) {
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printf("ERROR: Stopped after %d portals\n", i);
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goto done;
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}
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addr += portal_cinh_size;
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}
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#ifdef DEBUG
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printf("Cleared %d portals\n", i);
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#endif
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done:
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return;
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}
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void setup_portals(void)
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{
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ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
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void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
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CONFIG_SYS_BMAN_SWP_ISDR_REG;
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void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
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CONFIG_SYS_QMAN_SWP_ISDR_REG;
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#ifdef CONFIG_FSL_CORENET
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int i;
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@ -38,6 +75,12 @@ void setup_portals(void)
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out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
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#endif
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out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
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/* Change default state of BMan ISDR portals to all 1s */
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inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
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CONFIG_SYS_BMAN_SP_CINH_SIZE);
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inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
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CONFIG_SYS_QMAN_SP_CINH_SIZE);
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}
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/* Update portal containter to match LAW setup of portal in phy map */
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|
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@ -299,12 +299,16 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
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{
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unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
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u64 memsize = (u64)memsize_in_meg << 20;
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u64 size;
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memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
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memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
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size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
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size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);
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if (memsize)
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print_size(memsize, " left unmapped\n");
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if (size || memsize > CONFIG_MAX_MEM_MAPPED) {
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print_size(memsize > CONFIG_MAX_MEM_MAPPED ?
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memsize - CONFIG_MAX_MEM_MAPPED + size : size,
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" left unmapped\n");
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}
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return memsize_in_meg;
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}
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|
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@ -11,6 +11,7 @@
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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#include <asm/mpc85xx_gpio.h>
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#include "ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -109,6 +110,19 @@ found:
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
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}
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#if defined(CONFIG_DEEP_SLEEP)
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void board_mem_sleep_setup(void)
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{
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void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
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/* does not provide HW signals for power management */
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clrbits_8(cpld_base + 0x17, 0x40);
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/* Disable MCKE isolation */
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gpio_set_value(2, 0);
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udelay(1);
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}
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#endif
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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@ -124,5 +138,10 @@ phys_size_t initdram(int board_type)
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#else
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dram_size = fsl_ddr_sdram_size();
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#endif
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#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
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fsl_dp_resume();
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#endif
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return dram_size;
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}
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|
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@ -11,7 +11,7 @@
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <spi_flash.h>
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#include <asm/mpc85xx_gpio.h>
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#include "../common/sleep.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -64,8 +64,8 @@ void board_init_f(ulong bootflag)
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#ifdef CONFIG_DEEP_SLEEP
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/* disable the console if boot from deep sleep */
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if (in_be32(&gur->scrtsr[0]) & (1 << 3))
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gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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/* compiler optimization barrier needed for GCC >= 3.4 */
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__asm__ __volatile__("" : : : "memory");
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@ -132,16 +132,3 @@ void board_init_r(gd_t *gd, ulong dest_addr)
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nand_boot();
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#endif
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}
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#ifdef CONFIG_DEEP_SLEEP
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void board_mem_sleep_setup(void)
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{
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void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
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/* does not provide HW signals for power management */
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clrbits_8(cpld_base + 0x17, 0x40);
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/* Disable MCKE isolation */
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gpio_set_value(2, 0);
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udelay(1);
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}
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#endif
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@ -17,8 +17,7 @@
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include <asm/mpc85xx_gpio.h>
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#include "../common/sleep.h"
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#include "t104xrdb.h"
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#include "cpld.h"
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@ -44,6 +43,16 @@ int checkboard(void)
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return 0;
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}
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int board_early_init_f(void)
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{
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_SYS_FLASH_BASE
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@ -113,14 +122,3 @@ int ft_board_setup(void *blob, bd_t *bd)
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return 0;
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}
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#ifdef CONFIG_DEEP_SLEEP
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void board_mem_sleep_setup(void)
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{
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/* does not provide HW signals for power management */
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CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
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/* Disable MCKE isolation */
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gpio_set_value(2, 0);
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udelay(1);
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}
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#endif
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|
|
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@ -246,7 +246,7 @@ int run_descriptor_jr(uint32_t *desc)
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struct result op;
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int ret = 0;
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memset(&op, sizeof(op), 0);
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memset(&op, 0, sizeof(op));
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ret = jr_enqueue(desc, desc_done, &op);
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if (ret) {
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|
|
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@ -324,6 +324,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
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#elif defined(CONFIG_SYS_FSL_DDR3)
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unsigned int data_rate = get_ddr_freq(0);
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int txp;
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unsigned int ip_rev;
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int odt_overlap;
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/*
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* (tXARD and tXARDS). Empirical?
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@ -336,7 +337,25 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
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*/
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txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
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tmrd_mclk = 4;
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ip_rev = fsl_ddr_get_version();
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if (ip_rev >= 0x40700) {
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/*
|
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* MRS_CYC = max(tMRD, tMOD)
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* tMRD = 4nCK (8nCK for RDIMM)
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* tMOD = max(12nCK, 15ns)
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*/
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tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000));
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} else {
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/*
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* MRS_CYC = tMRD
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* tMRD = 4nCK (8nCK for RDIMM)
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*/
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if (popts->registered_dimm_en)
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tmrd_mclk = 8;
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else
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tmrd_mclk = 4;
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}
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|
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/* set the turnaround time */
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|
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/*
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|
|
|
@ -247,17 +247,17 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
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}
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|
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#ifdef CONFIG_SYS_FMAN_V3
|
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#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
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/*
|
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* Physically FM1_DTSEC9 and FM1_10GEC1 use the same dual-role MAC, when
|
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* FM1_10GEC1 is enabled and FM1_DTSEC9 is disabled, ensure that the
|
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* dual-role MAC is not disabled, ditto for other dual-role MACs.
|
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* On T2/T4 SoCs, physically FM1_DTSEC9 and FM1_10GEC1 use the same
|
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* dual-role MAC, when FM1_10GEC1 is enabled and FM1_DTSEC9
|
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* is disabled, ensure that the dual-role MAC is not disabled,
|
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* ditto for other dual-role MACs.
|
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*/
|
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if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
|
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((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
|
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((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
|
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((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
|
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((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
|
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((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
|
||||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
|
||||
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
|
||||
((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
|
||||
|
@ -268,6 +268,17 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
|
|||
((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) ||
|
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((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) ||
|
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((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10)))
|
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#endif
|
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#else
|
||||
/* FM1_DTSECx and FM1_10GECx use the same dual-role MAC */
|
||||
if (((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
|
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((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
|
||||
((info->port == FM1_DTSEC3) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
|
||||
((info->port == FM1_DTSEC4) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
|
||||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
|
||||
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC2))) ||
|
||||
((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC3))) ||
|
||||
((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4)))
|
||||
#endif
|
||||
)
|
||||
return;
|
||||
|
|
|
@ -13,6 +13,9 @@
|
|||
#include "asm/io.h"
|
||||
#include "linux/immap_qe.h"
|
||||
#include "qe.h"
|
||||
#ifdef CONFIG_LS102XA
|
||||
#include <asm/arch/immap_ls102xa.h>
|
||||
#endif
|
||||
|
||||
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
|
||||
|
||||
|
@ -335,7 +338,11 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
|
|||
size_t length;
|
||||
const struct qe_header *hdr;
|
||||
#ifdef CONFIG_DEEP_SLEEP
|
||||
#ifdef CONFIG_LS102XA
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
#else
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
#endif
|
||||
#endif
|
||||
if (!firmware) {
|
||||
printf("Invalid address\n");
|
||||
|
@ -470,7 +477,11 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
|
|||
size_t length;
|
||||
const struct qe_header *hdr;
|
||||
#ifdef CONFIG_DEEP_SLEEP
|
||||
#ifdef CONFIG_LS102XA
|
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
|
||||
#else
|
||||
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
#endif
|
||||
#endif
|
||||
if (!firmware) {
|
||||
printf("Invalid address\n");
|
||||
|
|
|
@ -641,6 +641,14 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
|
@ -649,6 +657,14 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
|
||||
|
|
|
@ -11,6 +11,9 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#ifdef CONFIG_BSC9131RDB
|
||||
#define CONFIG_BSC9131
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
|
|
|
@ -11,6 +11,9 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#ifdef CONFIG_BSC9132QDS
|
||||
#define CONFIG_BSC9132
|
||||
#endif
|
||||
|
|
|
@ -347,9 +347,25 @@ extern unsigned long get_clock_freq(void);
|
|||
#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
/* For FM */
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
|
|
|
@ -13,6 +13,8 @@
|
|||
|
||||
#define CONFIG_P2041RDB
|
||||
#define CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#define CONFIG_PPC_P2041
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
|
@ -489,6 +491,14 @@ unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
|
@ -497,6 +507,14 @@ unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
|
@ -720,7 +720,7 @@ unsigned long get_board_ddr_clk(void);
|
|||
/* Qman/Bman */
|
||||
#ifndef CONFIG_NOBQFMAN
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
|
@ -728,7 +728,15 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
|
@ -736,6 +744,14 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
|
||||
|
|
|
@ -677,7 +677,7 @@ unsigned long get_board_ddr_clk(void);
|
|||
/* Qman/Bman */
|
||||
#ifndef CONFIG_NOBQFMAN
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
|
@ -685,7 +685,15 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
|
@ -693,6 +701,14 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
|
||||
|
|
|
@ -605,14 +605,30 @@ unsigned long get_board_ddr_clk(void);
|
|||
/* Qman/Bman */
|
||||
#ifndef CONFIG_NOBQFMAN
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
|
@ -104,7 +104,10 @@
|
|||
|
||||
/* support deep sleep */
|
||||
#define CONFIG_DEEP_SLEEP
|
||||
#if defined(CONFIG_DEEP_SLEEP)
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_SILENT_CONSOLE
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff40000
|
||||
|
@ -636,14 +639,30 @@
|
|||
/* Qman/Bman */
|
||||
#ifndef CONFIG_NOBQFMAN
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
|
@ -634,10 +634,26 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 18
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
|
@ -567,10 +567,26 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 18
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
|
@ -85,10 +85,26 @@
|
|||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 50
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
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||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
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||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
|
@ -417,10 +417,26 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 50
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
|
@ -12,6 +12,8 @@
|
|||
|
||||
#define CONFIG_T4240RDB
|
||||
#define CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_PCIE4
|
||||
|
@ -577,10 +579,26 @@ unsigned long get_board_ddr_clk(void);
|
|||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 50
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
|
@ -495,6 +495,14 @@
|
|||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
|
@ -503,6 +511,14 @@
|
|||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
|
@ -339,10 +339,26 @@ int get_scl(void);
|
|||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
|
Loading…
Add table
Reference in a new issue