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Merge with git://www.denx.de/git/u-boot.git

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This commit is contained in:
Stefan Roese 2007-06-25 20:20:30 +02:00
commit e4feb7638c
45 changed files with 888 additions and 204 deletions
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39
CHANGELOG
View file

@ -1,3 +1,42 @@
commit 2dc64451b4c08ffd619372abfdc2506a2e2363b9
Author: Igor Lisitsin <igor@emcraft.com>
Date: Wed Apr 18 14:55:19 2007 +0400
Adapt log buffer code to support Linux 2.6
A new environment variable, "logversion", selects the log buffer
behaviour. If it is not set or set to a value other than 2, then the
old, Linux 2.4.4, behaviour is selected.
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
commit a11e06965ec91270c51853407ff1261d3c740386
Author: Igor Lisitsin <igor@emcraft.com>
Date: Wed Mar 28 19:06:19 2007 +0400
Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440.
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
commit 02032e8f14751a1a751b09240a4f1cf9f8a2077f
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Fri Jun 22 14:58:04 2007 +0200
[ppc] Fix build breakage for all non-4xx PowerPC variants.
- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
- minor 4xx cleanup
commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Jun 20 18:14:24 2007 +0200
Coding style cleanup. Refresh CHANGELOG.
commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024
Author: Stefan Roese <sr@denx.de>
Date: Tue Jun 19 17:22:44 2007 +0200

14
board/amcc/acadia/acadia.c
View file

@ -31,13 +31,13 @@ static void acadia_gpio_init(void)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
/*
* Ultra (405EZ) was nice enough to add another GPIO controller

10
board/amcc/sequoia/sequoia.c
View file

@ -573,3 +573,13 @@ int is_pci_host(struct pci_controller *hose)
return (1);
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */

2
board/bf537-stamp/ether_bf537.c
View file

@ -48,7 +48,7 @@
#define TXBUF_BASE_ADDR 0xFF800000
#define TX_BUF_CNT 1
#define TOUT_LOOP 1000000
#define TOUT_LOOP 1000000
ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];

6
board/bf537-stamp/flash-defines.h
View file

@ -44,9 +44,9 @@
#define ERASE_SECT 6
#define READ 7
#define GET_SECTNUM 8
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_MAN_ST 2
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_MAN_ST 2
#define RESET_VAL 0xF0
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];

2
board/bf537-stamp/stm_m25p64.c
View file

@ -9,7 +9,7 @@
/* Application definitions */
#define NUM_SECTORS 128 /* number of sectors */
#define NUM_SECTORS 128 /* number of sectors */
#define SECTOR_SIZE 0x10000
#define NOP_NUM 1000

12
board/bf537-stamp/u-boot.lds.S
View file

@ -33,7 +33,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
__DYNAMIC = 0; */
MEMORY
{
ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
}
@ -47,11 +47,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
@ -68,7 +68,7 @@ SECTIONS
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector before the environment sector. If it throws */
/* the sector before the environment sector. If it throws */
/* an error during compilation remove an object here to get */
/* it linked after the configuration sector. */

2
board/smdk2400/lowlevel_init.S
View file

@ -117,7 +117,7 @@
#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
#define Trp 0x0 /* 2 clk */
#define Trc 0x3 /* 7 clk */
#define Tchr 0x2 /* 3 clk */
#define Tchr 0x2 /* 3 clk */
#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */

120
common/cmd_log.c
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2002
* (C) Copyright 2002-2007
* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
*
* Code used from linux/kernel/printk.c
@ -60,45 +60,40 @@ static char buf[1024];
/* This combination will not print messages with the default loglevel */
static unsigned console_loglevel = 3;
static unsigned default_message_loglevel = 4;
static unsigned char *log_buf = NULL;
static unsigned long *ext_log_size;
static unsigned long *ext_log_start;
static unsigned long *ext_logged_chars;
#define log_size (*ext_log_size)
#define log_start (*ext_log_start)
#define logged_chars (*ext_logged_chars)
static unsigned log_version = 1;
static logbuff_t *log;
/* Forced by code, eh! */
#define LOGBUFF_MAGIC 0xc0de4ced
/* The mapping used here has to be the same as in setup_ext_logbuff ()
in linux/kernel/printk */
void logbuff_init_ptrs (void)
{
unsigned long *ext_tag;
unsigned long post_word;
unsigned long tag, post_word;
char *s;
log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN);
ext_tag = (unsigned long *)(log_buf)-4;
ext_log_start = (unsigned long *)(log_buf)-3;
ext_log_size = (unsigned long *)(log_buf)-2;
ext_logged_chars = (unsigned long *)(log_buf)-1;
log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1;
/* Set up log version */
if ((s = getenv ("logversion")) != NULL)
log_version = (int)simple_strtoul (s, NULL, 10);
if (log_version == 2)
tag = log->v2.tag;
else
tag = log->v1.tag;
post_word = post_word_load();
#ifdef CONFIG_POST
/* The post routines have setup the word so we can simply test it */
if (post_word_load () & POST_COLDBOOT) {
logged_chars = log_size = log_start = 0;
*ext_tag = LOGBUFF_MAGIC;
}
if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) {
logbuff_reset ();
}
#else
/* No post routines, so we do our own checking */
if (post_word != LOGBUFF_MAGIC) {
logged_chars = log_size = log_start = 0;
if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) {
logbuff_reset ();
post_word_store (LOGBUFF_MAGIC);
*ext_tag = LOGBUFF_MAGIC;
}
}
#endif
if (log_version == 2 && (long)log->v2.start > (long)log->v2.con)
log->v2.start = log->v2.con;
/* Initialize default loglevel if present */
if ((s = getenv ("loglevel")) != NULL)
console_loglevel = (int)simple_strtoul (s, NULL, 10);
@ -106,6 +101,15 @@ void logbuff_init_ptrs (void)
gd->post_log_word |= LOGBUFF_INITIALIZED;
}
void logbuff_reset (void)
{
memset (log, 0, sizeof (logbuff_t));
if (log_version == 2)
log->v2.tag = LOGBUFF_MAGIC;
else
log->v1.tag = LOGBUFF_MAGIC;
}
int drv_logbuff_init (void)
{
device_t logdev;
@ -162,7 +166,7 @@ void logbuff_log(char *msg)
int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *s;
unsigned long i;
unsigned long i, start, size;
if (strcmp(argv[1],"append") == 0) {
/* Log concatenation of all arguments separated by spaces */
@ -177,21 +181,34 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
case 2:
if (strcmp(argv[1],"show") == 0) {
for (i=0; i < (log_size&LOGBUFF_MASK); i++) {
s = (char *)log_buf+((log_start+i)&LOGBUFF_MASK);
if (log_version == 2) {
start = log->v2.start;
size = log->v2.end - log->v2.start;
}
else {
start = log->v1.start;
size = log->v1.size;
}
for (i=0; i < (size&LOGBUFF_MASK); i++) {
s = (char *)log->buf+((start+i)&LOGBUFF_MASK);
putc (*s);
}
return 0;
} else if (strcmp(argv[1],"reset") == 0) {
log_start = 0;
log_size = 0;
logged_chars = 0;
logbuff_reset ();
return 0;
} else if (strcmp(argv[1],"info") == 0) {
printf ("Logbuffer at %08lx\n", (unsigned long)log_buf);
printf ("log_start = %08lx\n", log_start);
printf ("log_size = %08lx\n", log_size);
printf ("logged_chars = %08lx\n", logged_chars);
printf ("Logbuffer at %08lx\n", (unsigned long)log->buf);
if (log_version == 2) {
printf ("log_start = %08lx\n", log->v2.start);
printf ("log_end = %08lx\n", log->v2.end);
printf ("logged_chars = %08lx\n", log->v2.chars);
}
else {
printf ("log_start = %08lx\n", log->v1.start);
printf ("log_size = %08lx\n", log->v1.size);
printf ("logged_chars = %08lx\n", log->v1.chars);
}
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
@ -202,7 +219,7 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
}
#if defined(CONFIG_LOGBUFFER)
U_BOOT_CMD(
log, 255, 1, do_log,
"log - manipulate logbuffer\n",
@ -211,7 +228,7 @@ U_BOOT_CMD(
"log show - show contents\n"
"log append <msg> - append <msg> to the logbuffer\n"
);
#endif /* CONFIG_LOGBUFFER */
static int logbuff_printk(const char *line)
{
int i;
@ -241,13 +258,22 @@ static int logbuff_printk(const char *line)
}
line_feed = 0;
for (; p < buf_end; p++) {
log_buf[(log_start+log_size) & LOGBUFF_MASK] = *p;
if (log_size < LOGBUFF_LEN)
log_size++;
else
log_start++;
logged_chars++;
if (log_version == 2) {
log->buf[log->v2.end & LOGBUFF_MASK] = *p;
log->v2.end++;
if (log->v2.end - log->v2.start > LOGBUFF_LEN)
log->v2.start++;
log->v2.chars++;
}
else {
log->buf[(log->v1.start + log->v1.size) &
LOGBUFF_MASK] = *p;
if (log->v1.size < LOGBUFF_LEN)
log->v1.size++;
else
log->v1.start++;
log->v1.chars++;
}
if (*p == '\n') {
line_feed = 1;
break;

2
common/main.c
View file

@ -962,7 +962,7 @@ int readline (const char *const prompt)
n = 0;
continue;
case 0x17: /* ^W - erase word */
case 0x17: /* ^W - erase word */
p=delete_char(console_buffer, p, &col, &n, plen);
while ((n > 0) && (*p != ' ')) {
p=delete_char(console_buffer, p, &col, &n, plen);

2
cpu/mpc5xx/start.S
View file

@ -155,7 +155,7 @@ in_flash:
/* Initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r2, CFG_INIT_SP_ADDR@h
ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
/* Note: R0 is still 0 here */

4
cpu/mpc8260/start.S
View file

@ -676,13 +676,13 @@ init_debug:
bdnz 1b
/* Load the Instruction Address Breakpoint Register (IABR). */
/* */
/* */
/* The address to load is stored in the first word of dual port */
/* ram and should be preserved while the power is on, so you */
/* can plug addresses into that location then reset the cpu and */
/* this code will load that address into the IABR after the */
/* reset. */
/* */
/* */
/* When the program counter matches the contents of the IABR, */
/* an exception is generated (before the instruction at that */
/* location completes). The vector for this exception is 0x1300 */

4
cpu/ppc4xx/44x_spd_ddr.c
View file

@ -1340,14 +1340,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
*/
cr |= SDRAM_BXCR_SDBE;
for (i = 0; i < num_banks; i++) {
for (i = 0; i < num_banks; i++) {
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
(4 << 20) * bank_size_id;
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
dimm_num, i, ctrl_bank_num[dimm_num]+i,
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
}
}
}
}

4
cpu/ppc4xx/44x_spd_ddr2.c
View file

@ -58,8 +58,8 @@
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
#define MAXDIMMS 2
#define MAXRANKS 4
#define MAXDIMMS 2
#define MAXRANKS 4
#define MAXBXCF 4
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */

4
cpu/ppc4xx/cpu_init.c
View file

@ -153,7 +153,7 @@ cpu_init_f (void)
*/
asm volatile(" bl 0f" ::: "lr");
asm volatile("0: mflr 3" ::: "r3");
asm volatile(" addi 4, 0, 14" ::: "r4");
asm volatile(" addi 4, 0, 14" ::: "r4");
asm volatile(" mtctr 4" ::: "ctr");
asm volatile("1: icbt 0, 3");
asm volatile(" addi 3, 3, 32" ::: "r3");
@ -211,6 +211,8 @@ cpu_init_f (void)
val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
val |= 0xb0000000; /* generate system reset after 1.34 seconds */
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */
#endif

46
include/asm-ppc/processor.h
View file

@ -35,18 +35,18 @@
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IS (1<<5) /* Book E Instruction space */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DS (1<<4) /* Book E Data space */
#define MSR_PE (1<<3) /* Protection Enable */
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
#define MSR_LE (1<<0) /* Little Endian */
#ifdef CONFIG_APUS_FAST_EXCEPT
#define MSR_ MSR_ME|MSR_IP|MSR_RI
@ -123,9 +123,9 @@
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
#define DBCR_RST(x) (((x) & 0x3) << 28)
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_SYSTEM 3
#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
@ -266,7 +266,7 @@
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
@ -495,17 +495,17 @@
#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
#define DBSR SPRN_DBSR /* Debug Status Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
#define EAR SPRN_EAR /* External Address Register */
#define EAR SPRN_EAR /* External Address Register */
#define ESR SPRN_ESR /* Exception Syndrome Register */
#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
@ -522,13 +522,13 @@
#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_MPC86xx)
@ -540,7 +540,7 @@
#define SVR SPRN_SVR /* System-On-Chip Version Register */
#define PVR SPRN_PVR /* Processor Version */
#define RPA SPRN_RPA /* Required Physical Address Register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
#define SPR1 SPRN_SPRG1
#define SPR2 SPRN_SPRG2
@ -611,7 +611,7 @@
#define IVOR35 SPRN_IVOR35
#define MCSRR0 SPRN_MCSRR0
#define MCSRR1 SPRN_MCSRR1
#define L1CSR0 SPRN_L1CSR0
#define L1CSR0 SPRN_L1CSR0
#define L1CSR1 SPRN_L1CSR1
#define MCSR SPRN_MCSR
#define MMUCSR0 SPRN_MMUCSR0
@ -620,7 +620,7 @@
#define PID1 SPRN_PID1
#define PID2 SPRN_PID2
#define MAS0 SPRN_MAS0
#define MAS1 SPRN_MAS1
#define MAS1 SPRN_MAS1
#define MAS2 SPRN_MAS2
#define MAS3 SPRN_MAS3
#define MAS4 SPRN_MAS4
@ -632,7 +632,7 @@
#define DCRN_BEAR 0x090 /* Bus Error Address Register */
#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DMES 0x40000000 /* DMA Error Status */
#define BESR_RWS 0x20000000 /* Read/Write Status */
#define BESR_ETMASK 0x1C000000 /* Error Type */
@ -689,8 +689,8 @@
#define IOCR_E3LP 0x01000000
#define IOCR_E4TE 0x00800000
#define IOCR_E4LP 0x00400000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDO 0x00008000
#define IOCR_2XC 0x00004000
#define IOCR_ATC 0x00002000
@ -815,7 +815,7 @@
#define PVR_823 PVR_821
#define PVR_850 PVR_821
#define PVR_860 PVR_821
#define PVR_7400 0x000C0000
#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
/*

4
include/configs/TQM5200.h
View file

@ -44,7 +44,7 @@
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
@ -238,7 +238,7 @@
"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
#else
#define CUSTOM_ENV_SETTINGS \
#define CUSTOM_ENV_SETTINGS \
"bootfile=cam5200/uImage\0" \
"u-boot=cam5200/u-boot.bin\0" \
"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"

4
include/configs/alpr.h
View file

@ -95,7 +95,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@ -257,7 +257,7 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */

14
include/configs/bamboo.h
View file

@ -74,9 +74,9 @@
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@ -115,8 +115,8 @@
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
@ -126,11 +126,11 @@
#define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned char
#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */

2
include/configs/ebony.h
View file

@ -122,7 +122,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */

4
include/configs/lwmon5.h
View file

@ -117,7 +117,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@ -359,7 +359,7 @@
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \

2
include/configs/ocotea.h
View file

@ -137,7 +137,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */

2
include/configs/p3p440.h
View file

@ -285,7 +285,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */

2
include/configs/pcs440ep.h
View file

@ -104,7 +104,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */

17
include/configs/sequoia.h
View file

@ -59,6 +59,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
@ -81,7 +82,7 @@
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
@ -126,7 +127,7 @@
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@ -328,6 +329,18 @@
CFG_CMD_SDRAM | \
CMD_USB)
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_UART | \
CFG_POST_I2C | \
CFG_POST_SPR)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CONFIG_LOGBUFFER
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_SUPPORT_VFAT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */

4
include/configs/taishan.h
View file

@ -218,8 +218,8 @@
#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x1
#define CONFIG_PHY3_ADDR 0x3
#define CONFIG_ET1011C_PHY 1

2
include/configs/yosemite.h
View file

@ -123,7 +123,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */

26
include/logbuff.h
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2002
* (C) Copyright 2002-2007
* Detlev Zundel, dzu@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -25,6 +25,7 @@
#ifdef CONFIG_LOGBUFFER
#define LOGBUFF_MAGIC 0xc0de4ced /* Forced by code, eh! */
#define LOGBUFF_LEN (16384) /* Must be 16k right now */
#define LOGBUFF_MASK (LOGBUFF_LEN-1)
#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
@ -32,6 +33,29 @@
#define LOGBUFF_INITIALIZED (1<<31)
/* The mapping used here has to be the same as in setup_ext_logbuff ()
in linux/kernel/printk */
typedef struct {
union {
struct {
unsigned long tag;
unsigned long start;
unsigned long con;
unsigned long end;
unsigned long chars;
} v2;
struct {
unsigned long dummy;
unsigned long tag;
unsigned long start;
unsigned long size;
unsigned long chars;
} v1;
};
unsigned char buf[0];
} logbuff_t;
int drv_logbuff_init (void);
void logbuff_init_ptrs (void);
void logbuff_log(char *msg);

42
include/mpc5xx.h
View file

@ -76,10 +76,10 @@
#define SIUMCR_DBPC01 0x00080000 /* - " - */
#define SIUMCR_DBPC10 0x00100000 /* - " - */
#define SIUMCR_DBPC11 0x00180000 /* - " - */
#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
@ -90,7 +90,7 @@
#define SIUMCR_MLRC01 0x00000400 /* - " - */
#define SIUMCR_MLRC10 0x00000800 /* - " - */
#define SIUMCR_MLRC11 0x00000c00 /* - " - */
#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control Register
@ -123,13 +123,13 @@
* SCCR - System Clock and reset Control Register
*/
#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
#define SCCR_EBDF11 0x00060000 /* reserved */
#define SCCR_TBS 0x02000000 /* Time Base Source */
#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
@ -138,11 +138,11 @@
/*-----------------------------------------------------------------------
* MC - Memory Controller
*/
#define BR_V 0x00000001 /* Bank valid */
#define BR_BI 0x00000002 /* Burst inhibit */
#define BR_PS_8 0x00000400 /* 8 bit port size */
#define BR_PS_16 0x00000800 /* 16 bit port size */
#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_V 0x00000001 /* Bank valid */
#define BR_BI 0x00000002 /* Burst inhibit */
#define BR_PS_8 0x00000400 /* 8 bit port size */
#define BR_PS_16 0x00000800 /* 16 bit port size */
#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_LBDIR 0x00000008 /* Late burst data in progess */
#define BR_SETA 0x00000004 /* External Data Acknowledge */
#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
@ -159,8 +159,8 @@
/*-----------------------------------------------------------------------
* UMCR - UIMB Module Configuration Register
*/
#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
#define UMCR_HSPEED 0x10000000 /* Half speed */
#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
#define UMCR_HSPEED 0x10000000 /* Half speed */
/*-----------------------------------------------------------------------
* ICTRL - I-Bus Support Control Register
@ -174,16 +174,16 @@
* SCI - Serial communication interface
*/
#define SCI_TDRE 0x0100 /* Transmit data register empty */
#define SCI_TE 0x0008 /* Transmitter enabled */
#define SCI_TDRE 0x0100 /* Transmit data register empty */
#define SCI_TE 0x0008 /* Transmitter enabled */
#define SCI_RE 0x0004 /* Receiver enabled */
#define SCI_RDRF 0x0040 /* Receive data register full */
#define SCI_PE 0x0400 /* Parity enable */
#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
#define SCI_SCXDR_MK 0x00ff /* Data register mask */
#define SCI_RDRF 0x0040 /* Receive data register full */
#define SCI_PE 0x0400 /* Parity enable */
#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
#define SCI_SCXDR_MK 0x00ff /* Data register mask */
#define SCI_M_11 0x0200 /* Frame size is 11 bit */
#define SCI_M_10 0x0000 /* Frame size is 10 bit */
#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
#define SCI_PORT_2 ((int)2)
#endif /* __MPC5XX_H__ */

6
include/mpc824x.h
View file

@ -88,7 +88,7 @@
#define PREP_PCI_MEMORY_BUS 0x80000000
#define PREP_PCI_MEMORY_SIZE 0x80000000
#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */
#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */
#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */
#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */
@ -98,8 +98,8 @@
#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */
#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */
#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */
#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */
#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */
#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */

16
include/mpc8260.h
View file

@ -664,7 +664,7 @@
#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */
/*-----------------------------------------------------------------------
* LSDMR - Local Bus SDRAM Mode Register 10-24
* LSDMR - Local Bus SDRAM Mode Register 10-24
*/
/*
@ -707,23 +707,23 @@
/*-----------------------------------------------------------------------
* TMR1-TMR4 - Timer Mode Registers 17-6
*/
#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/
#define TMRx_OM 0x0020 /* Output Mode */
#define TMRx_OM 0x0020 /* Output Mode */
#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/
#define TMRx_FRR 0x0008 /* Free Run/Restart */
#define TMRx_FRR 0x0008 /* Free Run/Restart */
#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
#define TMRx_GE 0x0001 /* Gate Enable */
#define TMRx_GE 0x0001 /* Gate Enable */
#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/
#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/
#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/
#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
/*-----------------------------------------------------------------------

10
include/mpc83xx.h
View file

@ -439,9 +439,9 @@
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_MPC831X)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
#define HRCWH_RL_EXT_LEGACY 0x00000000
@ -1218,7 +1218,7 @@
#define FCR_CMD1 0x00FF0000
#define FCR_CMD1_SHIFT 16
#define FCR_CMD2 0x0000FF00
#define FCR_CMD2_SHIFT 8
#define FCR_CMD2_SHIFT 8
#define FCR_CMD3 0x000000FF
#define FCR_CMD3_SHIFT 0
@ -1242,8 +1242,8 @@
/* LTESR - Transfer Error Status Register
*/
#define LTESR_BM 0x80000000
#define LTESR_FCT 0x40000000
#define LTESR_PAR 0x20000000
#define LTESR_FCT 0x40000000
#define LTESR_PAR 0x20000000
#define LTESR_WP 0x04000000
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000

12
include/mpc8xx.h
View file

@ -208,12 +208,12 @@
#define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */
#define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
#define SCCR_DFNL001 0x00000100 /* Division by 4 */
#define SCCR_DFNL010 0x00000200 /* Division by 8 */
#define SCCR_DFNL011 0x00000300 /* Division by 16 */
#define SCCR_DFNL100 0x00000400 /* Division by 32 */
#define SCCR_DFNL101 0x00000500 /* Division by 64 */
#define SCCR_DFNL110 0x00000600 /* Division by 128 */
#define SCCR_DFNL001 0x00000100 /* Division by 4 */
#define SCCR_DFNL010 0x00000200 /* Division by 8 */
#define SCCR_DFNL011 0x00000300 /* Division by 16 */
#define SCCR_DFNL100 0x00000400 /* Division by 32 */
#define SCCR_DFNL101 0x00000500 /* Division by 64 */
#define SCCR_DFNL110 0x00000600 /* Division by 128 */
#define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */
#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */

1
include/post.h
View file

@ -91,6 +91,7 @@ extern int post_hotkeys_pressed(void);
#define CFG_POST_SYSMON 0x00000800
#define CFG_POST_DSP 0x00001000
#define CFG_POST_CODEC 0x00002000
#define CFG_POST_FPU 0x00004000
#endif /* CONFIG_POST */

14
include/ppc405.h
View file

@ -143,12 +143,12 @@
#define UIC_USBH1 0x00040000 /* USB Host 1 */
#define UIC_USBH2 0x00020000 /* USB Host 2 */
#define UIC_USBDEV 0x00010000 /* USB Device */
#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
#define UIC_ENET1 0x00008000 /* dummy define */
#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
#define UIC_ENET1 0x00008000 /* dummy define */
#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
@ -886,7 +886,7 @@
#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
#define ecr (0xaa) /* edge conditioner register (405gpr) */
@ -1119,13 +1119,13 @@
| UART Register Offsets
'----------------------------------------------------------------------------*/
#define DATA_REG 0x00
#define DL_LSB 0x00
#define DL_MSB 0x01
#define DL_LSB 0x00
#define DL_MSB 0x01
#define INT_ENABLE 0x01
#define FIFO_CONTROL 0x02
#define LINE_CONTROL 0x03
#define MODEM_CONTROL 0x04
#define LINE_STATUS 0x05
#define LINE_STATUS 0x05
#define MODEM_STATUS 0x06
#define SCRATCH 0x07

58
include/ppc440.h
View file

@ -112,7 +112,7 @@
#define icdbtrh 0x39f /* instruction cache debug tag register high */
#define mmucr 0x3b2 /* mmu control register */
#define ccr0 0x3b3 /* core configuration register 0 */
#define ccr1 0x378 /* core configuration for 440x5 only */
#define ccr1 0x378 /* core configuration for 440x5 only */
#define icdbdr 0x3d3 /* instruction cache debug data register */
#define dbdr 0x3f3 /* debug data register */
@ -136,7 +136,7 @@
#define clk_opbd 0x00c0
#define clk_perd 0x00e0
#define clk_mald 0x0100
#define clk_spcid 0x0120
#define clk_spcid 0x0120
#define clk_icfg 0x0140
/* 440gx sdr register definations */
@ -282,6 +282,32 @@
#define sdr_sdstp3 0x4003
#endif /* CONFIG_440GX */
#ifdef CONFIG_440
/*----------------------------------------------------------------------------+
| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
+----------------------------------------------------------------------------*/
#define CCR0_PRE 0x40000000
#define CCR0_CRPE 0x08000000
#define CCR0_DSTG 0x00200000
#define CCR0_DAPUIB 0x00100000
#define CCR0_DTB 0x00008000
#define CCR0_GICBT 0x00004000
#define CCR0_GDCBT 0x00002000
#define CCR0_FLSTA 0x00000100
#define CCR0_ICSLC_MASK 0x0000000C
#define CCR0_ICSLT_MASK 0x00000003
#define CCR1_TCS_MASK 0x00000080
#define CCR1_TCS_INTCLK 0x00000000
#define CCR1_TCS_EXTCLK 0x00000080
#define MMUCR_SWOA 0x01000000
#define MMUCR_U1TE 0x00400000
#define MMUCR_U2SWOAE 0x00200000
#define MMUCR_DULXE 0x00800000
#define MMUCR_IULXE 0x00400000
#define MMUCR_STS 0x00100000
#define MMUCR_STID_MASK 0x000000FF
#endif /* CONFIG_440 */
#ifdef CONFIG_440SPE
#undef sdr_sdstp2
#define sdr_sdstp2 0x0022
@ -307,30 +333,6 @@
#define sdr_sdstp6 0x4005
#define sdr_sdstp7 0x4007
/*----------------------------------------------------------------------------+
| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
+----------------------------------------------------------------------------*/
#define CCR0_PRE 0x40000000
#define CCR0_CRPE 0x08000000
#define CCR0_DSTG 0x00200000
#define CCR0_DAPUIB 0x00100000
#define CCR0_DTB 0x00008000
#define CCR0_GICBT 0x00004000
#define CCR0_GDCBT 0x00002000
#define CCR0_FLSTA 0x00000100
#define CCR0_ICSLC_MASK 0x0000000C
#define CCR0_ICSLT_MASK 0x00000003
#define CCR1_TCS_MASK 0x00000080
#define CCR1_TCS_INTCLK 0x00000000
#define CCR1_TCS_EXTCLK 0x00000080
#define MMUCR_SEOA 0x01000000
#define MMUCR_U1TE 0x00400000
#define MMUCR_U2SWOAE 0x00200000
#define MMUCR_DULXE 0x00800000
#define MMUCR_IULXE 0x00400000
#define MMUCR_STS 0x00100000
#define MMUCR_STID_MASK 0x000000FF
#define SDR0_CFGADDR 0x00E
#define SDR0_CFGDATA 0x00F
@ -684,8 +686,8 @@
#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
#define SDRAM_CODT_IO_HIZ 0x00000000
#define SDRAM_CODT_IO_NMODE 0x00000001
#define SDRAM_CODT_IO_HIZ 0x00000000
#define SDRAM_CODT_IO_NMODE 0x00000001
/*-----------------------------------------------------------------------------+
| SDRAM Mode Register

28
post/cpu/ppc4xx/Makefile Normal file
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@ -0,0 +1,28 @@
#
# (C) Copyright 2002-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
LIB = libpostppc4xx.a
COBJS = fpu.o spr.o uart.o watchdog.o
include $(TOPDIR)/post/rules.mk

55
post/cpu/ppc4xx/fpu.c Normal file
View file

@ -0,0 +1,55 @@
/*
* Copyright (C) 2007 Wolfgang Denk <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#ifdef CONFIG_POST
#if defined(CONFIG_440EP) || \
defined(CONFIG_440EPX)
#include <ppc4xx.h>
#include <asm/processor.h>
int fpu_status(void)
{
if (mfspr(ccr0) & CCR0_DAPUIB)
return 0; /* Disabled */
else
return 1; /* Enabled */
}
void fpu_disable(void)
{
mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB);
mtmsr(mfmsr() & ~MSR_FP);
}
void fpu_enable(void)
{
mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB);
mtmsr(mfmsr() | MSR_FP);
}
#endif
#endif

176
post/cpu/ppc4xx/spr.c Normal file
View file

@ -0,0 +1,176 @@
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* SPR test
*
* The test checks the contents of Special Purpose Registers (SPR) listed
* in the spr_test_list array below.
* Each SPR value is read using mfspr instruction, some bits are masked
* according to the table and the resulting value is compared to the
* corresponding table value.
*/
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_SPR
static struct
{
int number;
char * name;
unsigned long mask;
unsigned long value;
} spr_test_list [] = {
/* Standard Special-Purpose Registers */
{0x001, "XER", 0x00000000, 0x00000000},
{0x008, "LR", 0x00000000, 0x00000000},
{0x009, "CTR", 0x00000000, 0x00000000},
{0x016, "DEC", 0x00000000, 0x00000000},
{0x01a, "SRR0", 0x00000000, 0x00000000},
{0x01b, "SRR1", 0x00000000, 0x00000000},
{0x110, "SPRG0", 0x00000000, 0x00000000},
{0x111, "SPRG1", 0x00000000, 0x00000000},
{0x112, "SPRG2", 0x00000000, 0x00000000},
{0x113, "SPRG3", 0x00000000, 0x00000000},
{0x11f, "PVR", 0x00000000, 0x00000000},
/* Additional Special-Purpose Registers */
{0x30, "PID", 0x00000000, 0x00000000},
{0x3a, "CSRR0", 0x00000000, 0x00000000},
{0x3b, "CSRR1", 0x00000000, 0x00000000},
{0x3d, "DEAR", 0x00000000, 0x00000000},
{0x3e, "ESR", 0x00000000, 0x00000000},
{0x3f, "IVPR", 0xffff0000, 0x00000000},
{0x100, "USPRG0", 0x00000000, 0x00000000},
{0x104, "SPRG4", 0x00000000, 0x00000000},
{0x105, "SPRG5", 0x00000000, 0x00000000},
{0x106, "SPRG6", 0x00000000, 0x00000000},
{0x107, "SPRG7", 0x00000000, 0x00000000},
{0x10c, "TBL", 0x00000000, 0x00000000},
{0x10d, "TBU", 0x00000000, 0x00000000},
{0x11e, "PIR", 0x0000000f, 0x00000000},
{0x130, "DBSR", 0x00000000, 0x00000000},
{0x134, "DBCR0", 0x00000000, 0x00000000},
{0x135, "DBCR1", 0x00000000, 0x00000000},
{0x136, "DBCR2", 0x00000000, 0x00000000},
{0x138, "IAC1", 0x00000000, 0x00000000},
{0x139, "IAC2", 0x00000000, 0x00000000},
{0x13a, "IAC3", 0x00000000, 0x00000000},
{0x13b, "IAC4", 0x00000000, 0x00000000},
{0x13c, "DAC1", 0x00000000, 0x00000000},
{0x13d, "DAC2", 0x00000000, 0x00000000},
{0x13e, "DVC1", 0x00000000, 0x00000000},
{0x13f, "DVC2", 0x00000000, 0x00000000},
{0x150, "TSR", 0x00000000, 0x00000000},
{0x154, "TCR", 0x00000000, 0x00000000},
{0x190, "IVOR0", 0x00000000, 0x00000000},
{0x191, "IVOR1", 0x00000000, 0x00000000},
{0x192, "IVOR2", 0x00000000, 0x00000000},
{0x193, "IVOR3", 0x00000000, 0x00000000},
{0x194, "IVOR4", 0x00000000, 0x00000000},
{0x195, "IVOR5", 0x00000000, 0x00000000},
{0x196, "IVOR6", 0x00000000, 0x00000000},
{0x197, "IVOR7", 0x00000000, 0x00000000},
{0x198, "IVOR8", 0x00000000, 0x00000000},
{0x199, "IVOR9", 0x00000000, 0x00000000},
{0x19a, "IVOR10", 0x00000000, 0x00000000},
{0x19b, "IVOR11", 0x00000000, 0x00000000},
{0x19c, "IVOR12", 0x00000000, 0x00000000},
{0x19d, "IVOR13", 0x00000000, 0x00000000},
{0x19e, "IVOR14", 0x00000000, 0x00000000},
{0x19f, "IVOR15", 0x00000000, 0x00000000},
{0x23a, "MCSRR0", 0x00000000, 0x00000000},
{0x23b, "MCSRR1", 0x00000000, 0x00000000},
{0x23c, "MCSR", 0x00000000, 0x00000000},
{0x370, "INV0", 0x00000000, 0x00000000},
{0x371, "INV1", 0x00000000, 0x00000000},
{0x372, "INV2", 0x00000000, 0x00000000},
{0x373, "INV3", 0x00000000, 0x00000000},
{0x374, "ITV0", 0x00000000, 0x00000000},
{0x375, "ITV1", 0x00000000, 0x00000000},
{0x376, "ITV2", 0x00000000, 0x00000000},
{0x377, "ITV3", 0x00000000, 0x00000000},
{0x378, "CCR1", 0x00000000, 0x00000000},
{0x390, "DNV0", 0x00000000, 0x00000000},
{0x391, "DNV1", 0x00000000, 0x00000000},
{0x392, "DNV2", 0x00000000, 0x00000000},
{0x393, "DNV3", 0x00000000, 0x00000000},
{0x394, "DTV0", 0x00000000, 0x00000000},
{0x395, "DTV1", 0x00000000, 0x00000000},
{0x396, "DTV2", 0x00000000, 0x00000000},
{0x397, "DTV3", 0x00000000, 0x00000000},
{0x398, "DVLIM", 0x00000000, 0x00000000},
{0x399, "IVLIM", 0x00000000, 0x00000000},
{0x39b, "RSTCFG", 0x00000000, 0x00000000},
{0x39c, "DCDBTRL", 0x00000000, 0x00000000},
{0x39d, "DCDBTRH", 0x00000000, 0x00000000},
{0x39e, "ICDBTRL", 0x00000000, 0x00000000},
{0x39f, "ICDBTRH", 0x00000000, 0x00000000},
{0x3b2, "MMUCR", 0x00000000, 0x00000000},
{0x3b3, "CCR0", 0x00000000, 0x00000000},
{0x3d3, "ICDBDR", 0x00000000, 0x00000000},
{0x3f3, "DBDR", 0x00000000, 0x00000000},
};
static int spr_test_list_size =
sizeof (spr_test_list) / sizeof (spr_test_list[0]);
int spr_post_test (int flags)
{
int ret = 0;
int i;
unsigned long code[] = {
0x7c6002a6, /* mfspr r3,SPR */
0x4e800020 /* blr */
};
unsigned long (*get_spr) (void) = (void *) code;
for (i = 0; i < spr_test_list_size; i++) {
int num = spr_test_list[i].number;
/* mfspr r3,num */
code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6);
asm volatile ("isync");
if ((get_spr () & spr_test_list[i].mask) !=
(spr_test_list[i].value & spr_test_list[i].mask)) {
post_log ("The value of %s special register "
"is incorrect: 0x%08X\n",
spr_test_list[i].name, get_spr ());
ret = -1;
}
}
return ret;
}
#endif /* CONFIG_POST & CFG_POST_SPR */
#endif /* CONFIG_POST */

214
post/cpu/ppc4xx/uart.c Normal file
View file

@ -0,0 +1,214 @@
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* UART test
*
* The controllers are configured to loopback mode and several
* characters are transmitted.
*/
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_UART
#include <asm/processor.h>
#include <serial.h>
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#define UART2_SDR sdr_uart2
#define UART3_SDR sdr_uart3
#define MFREG(a, d) mfsdr(a, d)
#define MTREG(a, d) mtsdr(a, d)
#define UART_RBR 0x00
#define UART_THR 0x00
#define UART_IER 0x01
#define UART_IIR 0x02
#define UART_FCR 0x02
#define UART_LCR 0x03
#define UART_MCR 0x04
#define UART_LSR 0x05
#define UART_MSR 0x06
#define UART_SCR 0x07
#define UART_DLL 0x00
#define UART_DLM 0x01
/*
Line Status Register.
*/
#define asyncLSRDataReady1 0x01
#define asyncLSROverrunError1 0x02
#define asyncLSRParityError1 0x04
#define asyncLSRFramingError1 0x08
#define asyncLSRBreakInterrupt1 0x10
#define asyncLSRTxHoldEmpty1 0x20
#define asyncLSRTxShiftEmpty1 0x40
#define asyncLSRRxFifoError1 0x80
DECLARE_GLOBAL_DATA_PTR;
static int uart_post_init (unsigned long dev_base)
{
unsigned long reg;
unsigned long udiv;
unsigned short bdiv;
volatile char val;
#ifdef CFG_EXT_SERIAL_CLOCK
unsigned long tmp;
#endif
int i;
for (i = 0; i < 3500; i++) {
if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
break;
udelay (100);
}
MFREG(UART0_SDR, reg);
reg &= ~CR0_MASK;
#ifdef CFG_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
/* For 440, the cpu clock is on divider chain A, UART on divider
* chain B ... so cpu clock is irrelevant. Get the "optimized"
* values that are subject to the 1/2 opb clock constraint
*/
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
/*
* Configure input clock to baudrate generator for all
* available serial ports here
*/
MTREG(UART0_SDR, reg);
#if defined(UART1_SDR)
MTREG(UART1_SDR, reg);
#endif
#if defined(UART2_SDR)
MTREG(UART2_SDR, reg);
#endif
#if defined(UART3_SDR)
MTREG(UART3_SDR, reg);
#endif
out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
val = in8(dev_base + UART_LSR); /* clear line status */
val = in8(dev_base + UART_RBR); /* read receive buffer */
out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
return 0;
}
static void uart_post_putc (unsigned long dev_base, char c)
{
int i;
out8 (dev_base + UART_THR, c); /* put character out */
/* Wait for transfer completion */
for (i = 0; i < 3500; i++) {
if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
break;
udelay (100);
}
}
static int uart_post_getc (unsigned long dev_base)
{
int i;
/* Wait for character available */
for (i = 0; i < 3500; i++) {
if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
break;
udelay (100);
}
return 0xff & in8 (dev_base + UART_RBR);
}
static int test_ctlr (unsigned long dev_base, int index)
{
int res = -1;
char test_str[] = "*** UART Test String ***\r\n";
int i;
uart_post_init (dev_base);
for (i = 0; i < sizeof (test_str) - 1; i++) {
uart_post_putc (dev_base, test_str[i]);
if (uart_post_getc (dev_base) != test_str[i])
goto done;
}
res = 0;
done:
if (res)
post_log ("uart%d test failed\n", index);
return res;
}
int uart_post_test (int flags)
{
int i, res = 0;
static unsigned long base[] = {
UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
};
for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
if (test_ctlr (base[i], i))
res = -1;
}
serial_reinit_all ();
return res;
}
#endif /* CONFIG_POST & CFG_POST_UART */
#endif /* CONFIG_POST */

68
post/cpu/ppc4xx/watchdog.c Normal file
View file

@ -0,0 +1,68 @@
/*
* (C) Copyright 2007
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* Watchdog test
*
* The test verifies the watchdog timer operation.
* On the first iteration, the test routine disables interrupts and
* makes a 10-second delay. If the system does not reboot during this delay,
* the watchdog timer is not operational and the test fails. If the system
* reboots, on the second iteration the test routine reports a success.
*/
#ifdef CONFIG_POST
#include <post.h>
#include <watchdog.h>
#if CONFIG_POST & CFG_POST_WATCHDOG
int watchdog_post_test (int flags)
{
if (flags & POST_REBOOT) {
/* Test passed */
return 0;
} else {
/* 10-second delay */
int ints = disable_interrupts ();
ulong base = post_time_ms (0);
while (post_time_ms (base) < 10000)
;
if (ints)
enable_interrupts ();
/*
* If we have reached this point, the watchdog timer
* does not work
*/
return -1;
}
}
#endif /* CONFIG_POST & CFG_POST_WATCHDOG */
#endif /* CONFIG_POST */

12
post/lib_ppc/asm.S
View file

@ -34,6 +34,7 @@
/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
.global cpu_post_exec_02
cpu_post_exec_02:
isync
mflr r0
stwu r0, -4(r1)
@ -56,6 +57,7 @@ cpu_post_exec_02:
/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
.global cpu_post_exec_04
cpu_post_exec_04:
isync
mflr r0
stwu r0, -4(r1)
@ -80,6 +82,7 @@ cpu_post_exec_04:
/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
.global cpu_post_exec_12
cpu_post_exec_12:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@ -100,6 +103,7 @@ cpu_post_exec_12:
/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
.global cpu_post_exec_11
cpu_post_exec_11:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@ -119,6 +123,7 @@ cpu_post_exec_11:
/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
.global cpu_post_exec_21
cpu_post_exec_21:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@ -148,6 +153,7 @@ cpu_post_exec_21:
ulong op2); */
.global cpu_post_exec_22
cpu_post_exec_22:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@ -177,6 +183,7 @@ cpu_post_exec_22:
/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
.global cpu_post_exec_12w
cpu_post_exec_12w:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@ -198,6 +205,7 @@ cpu_post_exec_12w:
/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
.global cpu_post_exec_11w
cpu_post_exec_11w:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@ -218,6 +226,7 @@ cpu_post_exec_11w:
/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
.global cpu_post_exec_22w
cpu_post_exec_22w:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@ -241,6 +250,7 @@ cpu_post_exec_22w:
/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
.global cpu_post_exec_21w
cpu_post_exec_21w:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@ -263,6 +273,7 @@ cpu_post_exec_21w:
/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
.global cpu_post_exec_21x
cpu_post_exec_21x:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)
@ -286,6 +297,7 @@ cpu_post_exec_21x:
ulong cr); */
.global cpu_post_exec_31
cpu_post_exec_31:
isync
mflr r0
stwu r0, -4(r1)
stwu r4, -4(r1)

8
post/lib_ppc/b.c
View file

@ -49,7 +49,7 @@ extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
ulong cr);
static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
int pjump, int dec, int link, ulong pctr, ulong cr)
int pjump, int decr, int link, ulong pctr, ulong cr)
{
int ret = 0;
ulong lr = 0;
@ -77,7 +77,7 @@ static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi,
ret = pjump == jump ? 0 : -1;
if (ret == 0)
{
if (dec)
if (decr)
ret = pctr == ctr + 1 ? 0 : -1;
else
ret = pctr == ctr ? 0 : -1;
@ -163,7 +163,7 @@ int cpu_post_test_b (void)
{
for (ctr = 1; ctr <= 2 && ret == 0; ctr++)
{
int dec = cd < 2;
int decr = cd < 2;
int cr = cond ? 0x80000000 : 0x00000000;
int jumpc = cc >= 2 ||
(cc == 0 && !cond) ||
@ -174,7 +174,7 @@ int cpu_post_test_b (void)
int jump = jumpc && jumpd;
ret = cpu_post_test_bc (link ? OP_BCL : OP_BC,
(cc << 3) + (cd << 1), 0, jump, dec, link,
(cc << 3) + (cd << 1), 0, jump, decr, link,
ctr, cr);
if (ret != 0)

2
post/post.c
View file

@ -428,7 +428,7 @@ void post_reloc (void)
unsigned long post_time_ms (unsigned long base)
{
#ifdef CONFIG_PPC
return (unsigned long)get_ticks () / (get_tbclk () / CFG_HZ) - base;
return (unsigned long)(get_ticks () / (get_tbclk () / CFG_HZ)) - base;
#else
#warning "Not implemented yet"
return 0; /* Not implemented yet */

14
post/tests.c
View file

@ -37,6 +37,7 @@ extern int i2c_post_test (int flags);
extern int rtc_post_test (int flags);
extern int memory_post_test (int flags);
extern int cpu_post_test (int flags);
extern int fpu_post_test (int flags);
extern int uart_post_test (int flags);
extern int ether_post_test (int flags);
extern int spi_post_test (int flags);
@ -126,6 +127,19 @@ struct post_test post_list[] =
CFG_POST_CPU
},
#endif
#if CONFIG_POST & CFG_POST_FPU
{
"FPU test",
"fpu",
"This test verifies the arithmetic logic unit of"
" FPU.",
POST_RAM | POST_ALWAYS,
&fpu_post_test,
NULL,
NULL,
CFG_POST_FPU
},
#endif
#if CONFIG_POST & CFG_POST_UART
{
"UART test",