mirror of
https://github.com/Fishwaldo/u-boot.git
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starfive: Porting jh7100-beaglev-starlight.dts from linux
https://github.com/starfive-tech/linux
This commit is contained in:
Emil Renner Berthing
Tekkaman Ninja
parent
28f4f6d2ab
commit
e4ffe1da9c
5 changed files with 1308 additions and 0 deletions
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@ -10,6 +10,8 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
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ifeq ($(CONFIG_TARGET_STARFIVE_JH7100),y)
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dtb-$(CONFIG_JH_EVB_V1) += starfive_jh7100_evb.dtb
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dtb-$(CONFIG_JH_STARLIGHT) += starfive_jh7100_starlight.dtb
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dtb-$(CONFIG_JH_STARLIGHT) += jh7100-beaglev-starlight.dtb
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dtb-$(CONFIG_JH_STARLIGHT) += jh7100-beaglev-starlight-a1.dtb
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endif
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targets += $(dtb-y)
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16
arch/riscv/dts/jh7100-beaglev-starlight-a1.dts
Normal file
16
arch/riscv/dts/jh7100-beaglev-starlight-a1.dts
Normal file
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@ -0,0 +1,16 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2021 Emil Renner Berthing <kernel@esmil.dk> */
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/dts-v1/;
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#include "jh7100-beaglev-starlight.dts"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "BeagleV Starlight Beta A1";
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
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priority = <256>;
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};
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};
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465
arch/riscv/dts/jh7100-beaglev-starlight.dts
Normal file
465
arch/riscv/dts/jh7100-beaglev-starlight.dts
Normal file
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@ -0,0 +1,465 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
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/dts-v1/;
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#include "jh7100.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/starfive_fb.h>
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/ {
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model = "BeagleV Starlight Beta";
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compatible = "beagle,beaglev-starlight-jh7100", "starfive,jh7100";
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aliases {
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mshc0 = &sdio0;
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mshc1 = &sdio1;
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serial0 = &uart3;
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serial1 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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timebase-frequency = <6250000>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x2 0x0>;
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};
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leds {
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compatible = "gpio-leds";
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led-ack {
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gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_HEARTBEAT;
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linux,default-trigger = "heartbeat";
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label = "ack";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x28000000>;
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alignment = <0x0 0x1000>;
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alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
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linux,cma-default;
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};
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jpu_reserved: framebuffer@c9000000 {
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reg = <0x0 0xc9000000 0x0 0x4000000>;
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};
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nvdla_reserved: framebuffer@d0000000 {
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no-map;
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reg = <0x0 0xd0000000 0x0 0x28000000>;
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};
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vin_reserved: framebuffer@f9000000 {
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compatible = "shared-dma-pool";
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no-map;
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reg = <0x0 0xf9000000 0x0 0x1000000>;
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};
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sffb_reserved: framebuffer@fb000000 {
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compatible = "shared-dma-pool";
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no-map;
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reg = <0x0 0xfb000000 0x0 0x2000000>;
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};
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};
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wifi_pwrseq: wifi-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <500>;
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i2c-scl-falling-time-ns = <500>;
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scl-gpio = <&gpio 62 0>;
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sda-gpio = <&gpio 61 0>;
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status = "okay";
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imx219@10 {
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compatible = "imx219";
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reg = <0x10>;
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reset-gpio = <&gpio 58 GPIO_ACTIVE_HIGH>;
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};
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pmic@5e {
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compatible = "ti,tps65086";
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reg = <0x5e>;
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gpio-controller;
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#gpio-cells = <2>;
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regulators {
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};
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};
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tda998x@70 {
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compatible = "nxp,tda998x";
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reg = <0x70>;
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <100>;
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i2c-scl-falling-time-ns = <100>;
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scl-gpio = <&gpio 47 0>;
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sda-gpio = <&gpio 48 0>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <500>;
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i2c-scl-falling-time-ns = <500>;
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scl-gpio = <&gpio 60 0>;
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sda-gpio = <&gpio 59 0>;
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status = "okay";
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seeed_plane_i2c@45 {
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compatible = "seeed_panel";
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reg = <0x45>;
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};
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};
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&osc_sys {
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clock-frequency = <25000000>;
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};
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&osc_aud {
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clock-frequency = <27000000>;
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};
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&qspi {
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nor_flash: nor-flash@0 {
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compatible = "spi-flash";
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reg = <0>;
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spi-max-frequency = <31250000>;
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page-size = <256>;
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block-size = <16>;
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cdns,read-delay = <4>;
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cdns,tshsl-ns = <1>;
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cdns,tsd2d-ns = <1>;
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cdns,tchsh-ns = <1>;
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cdns,tslch-ns = <1>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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nand_flash: nand-flash@1 {
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compatible = "spi-flash-nand";
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reg = <1>;
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spi-max-frequency = <31250000>;
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page-size = <2048>;
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block-size = <17>;
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cdns,read-delay = <4>;
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cdns,tshsl-ns = <1>;
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cdns,tsd2d-ns = <1>;
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cdns,tchsh-ns = <1>;
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cdns,tslch-ns = <1>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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&sdio0 {
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broken-cd;
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bus-width = <4>;
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cap-sd-highspeed;
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max-frequency = <10000000>;
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status = "okay";
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};
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&sdio1 {
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#address-cells = <1>;
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#size-cells = <0>;
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bus-width = <4>;
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cap-sd-highspeed;
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cap-sdio-irq;
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cap-power-off-card;
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max-frequency = <10000000>;
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mmc-pwrseq = <&wifi_pwrseq>;
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non-removable;
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status = "okay";
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wifi@1 {
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compatible = "brcm,bcm4329-fmac";
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reg = <1>;
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};
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};
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&sfivefb {
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status = "okay";
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/*
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pp1 {
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pp-id = <1>;
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fifo-out;
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src-format = <COLOR_YUV420_NV21>;
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src-width = <800>;
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src-height = <480>;
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dst-format = <COLOR_RGB888_ARGB>;
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dst-width = <800>;
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dst-height = <480>;
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};
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*/
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tda_998x_1080p {
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compatible = "starfive,display-dev";
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panel_name = "tda_998x_1080p";
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panel_lcd_id = <22>; /* 1080p */
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interface_info = "rgb_interface";
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refresh_en = <1>;
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bits-per-pixel = <16>;
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physical-width = <62>;
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physical-height = <114>;
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panel-width = <1920>;
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panel-height = <1080>;
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pixel-clock = <78000000>;
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/*dyn_fps;*/ /*dynamic frame rate support*/
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/*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/
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/*gamma-command-monolithic;*/
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/*ce-command-monolithic;*/
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/*resume-with-gamma;*/
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/*resume-with-ce;*/
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/*mipi info*/
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mipi-byte-clock = <78000>;
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mipi-escape-clock = <13000>;
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lane-no = <4>;
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display_mode = "video_mode"; /*video_mode, command_mode*/
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/*
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auto_stop_clklane_en;
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im_pin_val;*/
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color_bits = <COLOR_CODE_24BIT>;
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/*is_18bit_loosely;*/
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/*video mode info*/
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h-pulse-width = <44>;
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h-back-porch = <148>;
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h-front-porch = <88>;
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v-pulse-width = <5>;
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v-back-porch = <36>;
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v-front-porch = <4>;
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status = "okay";
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sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/
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lp_cmd_en;
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/*lp_hfp_en;*/
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/*lp_hbp_en;*/
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/*lp_vact_en;*/
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lp_vfp_en;
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lp_vbp_en;
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lp_vsa_en;
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traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/
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/*phy info*/
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data_tprepare = /bits/ 8 <0>;
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data_hs_zero = /bits/ 8 <0>;
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data_hs_exit = /bits/ 8 <0>;
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data_hs_trail = /bits/ 8 <0>;
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/*te info*/
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te_source = "external_pin"; /*external_pin, dsi_te_trigger*/
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te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/
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te_enable = <0>;
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cm_te_effect_sync_enable = <0>; /*used in command mode*/
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te_count_per_sec = <64>; /*used in esd*/
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/*ext info*/
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/*
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crc_rx_en;
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ecc_rx_en;
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eotp_rx_en;
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*/
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eotp_tx_en;
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dev_read_time = <0x7fff>;
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/*type cmd return_count return_code*/
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/*id_read_cmd_info = [];*/
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/*pre_id_cmd = [];*/
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/*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/
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/*pre_esd_cmd = [];*/
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/*panel-on-command = [];*/
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/*panel-off-command = [];*/
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/*reset-sequence = <1 5>, <0 10>, <1 30>;*/
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/*
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panel-gamma-warm-command = [
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];
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panel-gamma-nature-command = [
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];
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panel-gamma-cool-command = [
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];
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panel-ce-std-command = [
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];
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panel-ce-vivid-command = [
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];
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*/
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};
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seeed_5_inch {
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compatible = "starfive,display-dev";
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panel_name = "seeed_5_inch";
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panel_lcd_id = <22>; /* 480p */
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interface_info = "mipi_interface";
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refresh_en = <1>;
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bits-per-pixel = <24>;
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physical-width = <62>;
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physical-height = <114>;
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panel-width = <800>;
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panel-height = <480>;
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pixel-clock = <27500000>;
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/*dyn_fps;*/ /*dynamic frame rate support*/
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fps = <50>;
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/*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/
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/*gamma-command-monolithic;*/
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/*ce-command-monolithic;*/
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/*resume-with-gamma;*/
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/*resume-with-ce;*/
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/*mipi info*/
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mipi-byte-clock = <78000>;
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mipi-escape-clock = <13000>;
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lane-no = <1>;
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display_mode = "video_mode"; /*video_mode, command_mode*/
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/*
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auto_stop_clklane_en;
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im_pin_val;
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*/
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color_bits = <COLOR_CODE_24BIT>;
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/*is_18bit_loosely;*/
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/*video mode info*/
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h-pulse-width = <10>;
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h-back-porch = <20>;
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h-front-porch = <50>;
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v-pulse-width = <5>;
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v-back-porch = <5>;
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v-front-porch = <135>;
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/*seeed panel mode info*/
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dphy_bps = <700000000>;
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dsi_burst_mode = <0>;
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dsi_sync_pulse = <1>;
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// bytes
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dsi_hsa = <30>;
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dsi_hbp = <211>;
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dsi_hfp = <159>;
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// lines
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dsi_vsa = <5>;
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dsi_vbp = <5>;
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dsi_vfp = <134>;
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status = "okay";
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sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/
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lp_cmd_en;
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/*lp_hfp_en;*/
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/*lp_hbp_en;*/
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||||
/*lp_vact_en;*/
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lp_vfp_en;
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lp_vbp_en;
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lp_vsa_en;
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traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/
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/*phy info*/
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data_tprepare = /bits/ 8 <0>;
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data_hs_zero = /bits/ 8 <0>;
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data_hs_exit = /bits/ 8 <0>;
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data_hs_trail = /bits/ 8 <0>;
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||||
/*te info*/
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te_source = "external_pin"; /*external_pin, dsi_te_trigger*/
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te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/
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te_enable = <0>;
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cm_te_effect_sync_enable = <0>; /*used in command mode*/
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te_count_per_sec = <64>; /*used in esd*/
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/*ext info*/
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||||
/*
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crc_rx_en;
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ecc_rx_en;
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eotp_rx_en;
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*/
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eotp_tx_en;
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dev_read_time = <0x7fff>;
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/*type cmd return_count return_code*/
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/*id_read_cmd_info = [];*/
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/*pre_id_cmd = [];*/
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/*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/
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/*pre_esd_cmd = [];*/
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/*panel-on-command = [];*/
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/*panel-off-command = [];*/
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/*reset-sequence = <1 5>, <0 10>, <1 30>;*/
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/*
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panel-gamma-warm-command = [
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];
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||||
panel-gamma-nature-command = [
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||||
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];
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panel-gamma-cool-command = [
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||||
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];
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||||
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panel-ce-std-command = [
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];
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panel-ce-vivid-command = [
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];
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*/
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||||
};
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||||
};
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||||
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||||
&spi2 {
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||||
status = "okay";
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||||
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||||
spi_dev0: spi@0 {
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||||
compatible = "rohm,dh2228fv";
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||||
spi-max-frequency = <10000000>;
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||||
reg = <0>;
|
||||
};
|
||||
};
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||||
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||||
&uart0 {
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||||
status = "okay";
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||||
};
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||||
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&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
622
arch/riscv/dts/jh7100.dtsi
Normal file
622
arch/riscv/dts/jh7100.dtsi
Normal file
|
|
@ -0,0 +1,622 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/clock/starfive-jh7100.h>
|
||||
#include <dt-bindings/starfive_fb.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "starfive,jh7100";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "sifive,u74-mc", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <32>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <32>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <&ccache>;
|
||||
reg = <0>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
starfive,itim = <&itim0>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
cpu0_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "sifive,u74-mc", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <32768>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <32>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <32768>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <32>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <&ccache>;
|
||||
reg = <1>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
starfive,itim = <&itim1>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
cpu1_intc: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
osc_sys: osc_sys {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc_aud: osc_aud {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&plic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ccache: cache-controller@2010000 {
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
cache-sets = <2048>;
|
||||
cache-size = <2097152>;
|
||||
cache-unified;
|
||||
compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
|
||||
interrupts = <128 131 129 130>;
|
||||
/*next-level-cache = <&L40 &L36>;*/
|
||||
reg = <0x0 0x2010000 0x0 0x1000>,
|
||||
<0x0 0x8000000 0x0 0x2000000>;
|
||||
reg-names = "control", "sideband";
|
||||
};
|
||||
|
||||
dtim: dtim@1000000 {
|
||||
compatible = "starfive,dtim0";
|
||||
reg = <0x0 0x1000000 0x0 0x2000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
|
||||
itim0: itim@1808000 {
|
||||
compatible = "starfive,itim0";
|
||||
reg = <0x0 0x1808000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
|
||||
itim1: itim@1820000 {
|
||||
compatible = "starfive,itim0";
|
||||
reg = <0x0 0x1820000 0x0 0x8000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
|
||||
clint: clint@2000000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,clint0";
|
||||
interrupts-extended = <&cpu0_intc 3>,
|
||||
<&cpu0_intc 7>,
|
||||
<&cpu1_intc 3>,
|
||||
<&cpu1_intc 7>;
|
||||
reg = <0x0 0x2000000 0x0 0x10000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
plic: interrupt-controller@c000000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,plic0";
|
||||
interrupt-controller;
|
||||
interrupts-extended = <&cpu0_intc 11>,
|
||||
<&cpu0_intc 9>,
|
||||
<&cpu1_intc 11>,
|
||||
<&cpu1_intc 9>;
|
||||
reg = <0x0 0xc000000 0x0 0x4000000>;
|
||||
reg-names = "control";
|
||||
riscv,max-priority = <7>;
|
||||
riscv,ndev = <127>;
|
||||
};
|
||||
|
||||
clkgen: clock-controller@11800000 {
|
||||
compatible = "starfive,jh7100-clkgen";
|
||||
reg = <0x0 0x11800000 0x0 0x10000>;
|
||||
clocks = <&osc_sys>, <&osc_aud>;
|
||||
clock-names = "osc_sys", "osc_aud";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@11870000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
interrupts = <92>;
|
||||
reg = <0x0 0x11870000 0x0 0x10000>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clkgen JH7100_CLK_UART0_CORE>,
|
||||
<&clkgen JH7100_CLK_UART0_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
current-clock = <74250000>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11880000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
interrupts = <93>;
|
||||
reg = <0x0 0x11880000 0x0 0x10000>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clkgen JH7100_CLK_UART1_CORE>,
|
||||
<&clkgen JH7100_CLK_UART1_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
current-clock = <74250000>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@12430000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
interrupts = <72>;
|
||||
reg = <0x0 0x12430000 0x0 0x10000>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clkgen JH7100_CLK_UART2_CORE>,
|
||||
<&clkgen JH7100_CLK_UART2_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
current-clock = <100000000>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@12440000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
interrupts = <73>;
|
||||
reg = <0x0 0x12440000 0x0 0x10000>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clkgen JH7100_CLK_UART3_CORE>,
|
||||
<&clkgen JH7100_CLK_UART3_APB>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
current-clock = <100000000>;
|
||||
current-speed = <115200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma2p: dma-controller@100b0000 {
|
||||
compatible = "snps,axi-dma-1.01a";
|
||||
reg = <0x0 0x100b0000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
|
||||
<&clkgen JH7100_CLK_SGDMA2P_AHB>;
|
||||
clock-names = "core-clk", "cfgr-clk";
|
||||
interrupts = <2>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <4>;
|
||||
snps,dma-masters = <1>;
|
||||
snps,data-width = <4>;
|
||||
snps,block-size = <4096 4096 4096 4096>;
|
||||
snps,priority = <0 1 2 3>;
|
||||
snps,axi-max-burst-len = <128>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
dma1p: dma-controller@10500000 {
|
||||
compatible = "snps,axi-dma-1.01a";
|
||||
reg = <0x0 0x10500000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
|
||||
<&clkgen JH7100_CLK_SGDMA1P_BUS>;
|
||||
clock-names = "core-clk", "cfgr-clk";
|
||||
interrupts = <1>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
snps,dma-masters = <1>;
|
||||
snps,data-width = <3>;
|
||||
snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
|
||||
snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||||
snps,axi-max-burst-len = <64>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3: usb@104c0000 {
|
||||
compatible = "cdns,usb3";
|
||||
reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
|
||||
<0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
|
||||
<0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
|
||||
reg-names = "otg", "xhci", "dev";
|
||||
interrupts = <44>, <52>, <43>;
|
||||
interrupt-names = "host", "peripheral", "otg";
|
||||
phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
|
||||
maximum-speed = "super-speed";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio: gpio@11910000 {
|
||||
compatible = "starfive,jh7100-gpio";
|
||||
reg = <0x0 0x11910000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_GPIO_APB>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <32>;
|
||||
};
|
||||
|
||||
i2c0: i2c@118b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x118b0000 0x0 0x10000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
|
||||
<&clkgen JH7100_CLK_I2C0_APB>;
|
||||
clock-names = "ref", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@118c0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x118c0000 0x0 0x10000>;
|
||||
interrupts = <97>;
|
||||
clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
|
||||
<&clkgen JH7100_CLK_I2C1_APB>;
|
||||
clock-names = "ref", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@12450000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x12450000 0x0 0x10000>;
|
||||
interrupts = <74>;
|
||||
clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
|
||||
<&clkgen JH7100_CLK_I2C2_APB>;
|
||||
clock-names = "ref", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@12460000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0x0 0x12460000 0x0 0x10000>;
|
||||
interrupts = <75>;
|
||||
clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
|
||||
<&clkgen JH7100_CLK_I2C3_APB>;
|
||||
clock-names = "ref", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trng: trng@118d0000 {
|
||||
compatible = "starfive,vic-rng";
|
||||
reg = <0x0 0x118d0000 0x0 0x10000>;
|
||||
interrupts = <98>;
|
||||
clocks = <&clkgen JH7100_CLK_TRNG_APB>;
|
||||
};
|
||||
|
||||
crypto: crypto@100d0000 {
|
||||
compatible = "starfive,vic-sec";
|
||||
reg = <0x0 0x100d0000 0x0 0x20000>,
|
||||
<0x0 0x11800234 0x0 0xc>;
|
||||
reg-names = "secmem", "secclk";
|
||||
interrupts = <31>;
|
||||
clocks = <&clkgen JH7100_CLK_SEC_AHB>;
|
||||
};
|
||||
|
||||
/* gmac device configuration */
|
||||
stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,wr_osr_lmt = <0xf>;
|
||||
snps,rd_osr_lmt = <0xf>;
|
||||
snps,blen = <256 128 64 32 0 0 0>;
|
||||
};
|
||||
|
||||
gmac: ethernet@10020000 {
|
||||
compatible = "snps,dwmac";
|
||||
reg = <0x0 0x10020000 0x0 0x10000>;
|
||||
interrupts = <6 7>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
max-frame-size = <9000>;
|
||||
phy-mode = "rgmii-txid";
|
||||
snps,multicast-filter-bins = <256>;
|
||||
snps,perfect-filter-entries = <128>;
|
||||
rx-fifo-depth = <32768>;
|
||||
tx-fifo-depth = <16384>;
|
||||
clocks = <&clkgen JH7100_CLK_GMAC_AHB>,
|
||||
<&clkgen JH7100_CLK_GMAC_AHB>,
|
||||
<&clkgen JH7100_CLK_GMAC_PTP_REF>;
|
||||
clock-names = "stmmaceth", "pclk", "ptp_ref";
|
||||
snps,fixed-burst;
|
||||
snps,no-pbl-x8 = <1>;
|
||||
/*snps,force_sf_dma_mode;*/
|
||||
snps,force_thresh_dma_mode;
|
||||
snps,axi-config = <&stmmac_axi_setup>;
|
||||
};
|
||||
|
||||
nvdla@11940000 {
|
||||
compatible = "nvidia,nvdla_os_initial";
|
||||
interrupts = <22>;
|
||||
memory-region = <&nvdla_reserved>;
|
||||
reg = <0x0 0x11940000 0x0 0x40000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
jpu: coadj12@11900000 {
|
||||
compatible = "cm,codaj12-jpu-1";
|
||||
reg = <0x0 0x11900000 0x0 0x300>;
|
||||
memory-region = <&jpu_reserved>;
|
||||
interrupts = <24>;
|
||||
clocks = <&clkgen JH7100_CLK_JPEG_APB>;
|
||||
clock-names = "jpege";
|
||||
reg-names = "control";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vpu_dec: vpu_dec@118f0000 {
|
||||
compatible = "c&m,cm511-vpu";
|
||||
reg = <0 0x118f0000 0 0x10000>;
|
||||
//memory-region = <&vpu_reserved>;
|
||||
interrupts = <23>;
|
||||
clocks = <&clkgen JH7100_CLK_VP6_CORE>;
|
||||
clock-names = "vcodec";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vpu_enc: vpu_enc@118e0000 {
|
||||
compatible = "cm,cm521-vpu";
|
||||
reg = <0x0 0x118e0000 0x0 0x4000>;
|
||||
interrupts = <26>;
|
||||
clocks = <&clkgen JH7100_CLK_VP6_CORE>;
|
||||
clock-names = "vcodec";
|
||||
reg-names = "control";
|
||||
};
|
||||
|
||||
ptc: pwm@12490000 {
|
||||
compatible = "starfive,pwm0";
|
||||
reg = <0x0 0x12490000 0x0 0x10000>;
|
||||
reg-names = "control";
|
||||
sifive,approx-period = <100000000>;
|
||||
clocks = <&clkgen JH7100_CLK_PWM_APB>;
|
||||
#pwm-cells = <3>;
|
||||
sifive,npwm = <8>;
|
||||
|
||||
};
|
||||
|
||||
qspi: spi@11860000 {
|
||||
compatible = "cdns,qspi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x11860000 0x0 0x10000>,
|
||||
<0x0 0x20000000 0x0 0x20000000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
|
||||
cdns,fifo-depth = <256>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,trigger-address = <0x0>;
|
||||
status = "disabled";
|
||||
spi-max-frequency = <250000000>;
|
||||
};
|
||||
|
||||
spi0: spi@11890000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <94>;
|
||||
reg = <0x0 0x11890000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
|
||||
<&clkgen JH7100_CLK_SPI0_APB>;
|
||||
clock-names = "ssi_clk", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@118a0000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <95>;
|
||||
reg = <0x0 0x118a0000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
|
||||
<&clkgen JH7100_CLK_SPI1_APB>;
|
||||
clock-names = "ssi_clk", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@12410000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <70>;
|
||||
reg = <0x0 0x12410000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
|
||||
<&clkgen JH7100_CLK_SPI2_APB>;
|
||||
clock-names = "ssi_clk", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@12420000 {
|
||||
compatible = "snps,dw-apb-ssi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <71>;
|
||||
reg = <0x0 0x12420000 0x0 0x10000>;
|
||||
clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
|
||||
<&clkgen JH7100_CLK_SPI3_APB>;
|
||||
clock-names = "ssi_clk", "pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xrp@f0000000 {
|
||||
compatible = "cdns,xrp";
|
||||
reg = <0x0 0xf0000000 0x0 0x01ffffff>,
|
||||
<0x10 0x72000000 0x0 0x00001000>,
|
||||
<0x10 0x72001000 0x0 0x00fff000>,
|
||||
<0x0 0x124b0000 0x0 0x00010000>;
|
||||
clocks = <&clkgen JH7100_CLK_VP6_CORE>;
|
||||
firmware-name = "vp6_elf";
|
||||
dsp-irq = <19 20>;
|
||||
dsp-irq-src = <0x20 0x21>;
|
||||
intc-irq-mode = <1>;
|
||||
intc-irq = <0 1>;
|
||||
interrupts = <27 28>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x40000000 0x0 0x40000000 0x01000000>,
|
||||
<0xb0000000 0x10 0x70000000 0x3000000>;
|
||||
dsp@0 {
|
||||
};
|
||||
};
|
||||
|
||||
sdio0: mmc@10000000 {
|
||||
compatible = "snps,dw-mshc";
|
||||
reg = <0x0 0x10000000 0x0 0x10000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
|
||||
<&clkgen JH7100_CLK_SDIO0_CCLKINT>;
|
||||
clock-names = "biu", "ciu";
|
||||
clock-frequency = <100000000>;
|
||||
data-addr = <0>;
|
||||
fifo-depth = <32>;
|
||||
fifo-watermark-aligned;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: mmc@10010000 {
|
||||
compatible = "snps,dw-mshc";
|
||||
reg = <0x0 0x10010000 0x0 0x10000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
|
||||
<&clkgen JH7100_CLK_SDIO1_CCLKINT>;
|
||||
clock-names = "biu", "ciu";
|
||||
clock-frequency = <100000000>;
|
||||
data-addr = <0>;
|
||||
fifo-depth = <32>;
|
||||
fifo-watermark-aligned;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sfivefb: sfivefb@12000000 {
|
||||
compatible = "starfive,vpp-lcdc";
|
||||
interrupts = <101>, <103>;
|
||||
interrupt-names = "lcdc_irq", "vpp1_irq";
|
||||
reg = <0x0 0x12000000 0x0 0x10000>,
|
||||
<0x0 0x12100000 0x0 0x10000>,
|
||||
<0x0 0x12040000 0x0 0x10000>,
|
||||
<0x0 0x12080000 0x0 0x10000>,
|
||||
<0x0 0x120c0000 0x0 0x10000>,
|
||||
<0x0 0x12240000 0x0 0x10000>,
|
||||
<0x0 0x12250000 0x0 0x10000>,
|
||||
<0x0 0x12260000 0x0 0x10000>;
|
||||
reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
|
||||
memory-region = <&sffb_reserved>;
|
||||
#if 0 // FIXME uart clocks can't be right for lcdc
|
||||
clocks = <&clkgen JH7100_CLK_UART>,
|
||||
<&clkgen JH7100_CLK_APB2>;
|
||||
#endif
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin_sysctl: vin_sysctl@19800000 {
|
||||
compatible = "starfive,stf-vin";
|
||||
reg = <0x0 0x19800000 0x0 0x10000>,
|
||||
<0x0 0x19810000 0x0 0x10000>,
|
||||
<0x0 0x19820000 0x0 0x10000>,
|
||||
<0x0 0x19830000 0x0 0x10000>,
|
||||
<0x0 0x19840000 0x0 0x10000>,
|
||||
<0x0 0x19870000 0x0 0x30000>,
|
||||
<0x0 0x198a0000 0x0 0x30000>,
|
||||
<0x0 0x11800000 0x0 0x10000>,
|
||||
<0x0 0x11840000 0x0 0x10000>,
|
||||
<0x0 0x11858000 0x0 0x10000>;
|
||||
reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
|
||||
"isp0", "isp1", "tclk", "trst", "iopad";
|
||||
interrupts = <119 109>;
|
||||
memory-region = <&vin_reserved>;
|
||||
/*defaule config for imx219 vin&isp*/
|
||||
format = <SRC_CSI2RX_VIN_ISP>;
|
||||
frame-width = <800>;
|
||||
frame-height =<480>;
|
||||
isp0_enable;
|
||||
csi-lane = <2>;
|
||||
csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
|
||||
csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
|
||||
csi-clane-swap = /bits/ 8 <0>;
|
||||
csi-clane-pn-swap = /bits/ 8 <0>;
|
||||
csi-mipiID = <0>;
|
||||
csi-width = <1920>;
|
||||
csi-height = <1080>;
|
||||
csi-dt = <0x2b>;
|
||||
};
|
||||
|
||||
sfctemp: tmon@124a0000 {
|
||||
compatible = "starfive,jh7100-temp";
|
||||
reg = <0x0 0x124a0000 0x0 0x10000>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
interrupts = <122>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <15000>;
|
||||
|
||||
thermal-sensors = <&sfctemp>;
|
||||
|
||||
cooling-maps {
|
||||
};
|
||||
|
||||
trips {
|
||||
cpu_alert0: cpu_alert0 {
|
||||
/* milliCelsius */
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit: cpu_crit {
|
||||
/* milliCelsius */
|
||||
temperature = <90000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
otp: otp@11810000 {
|
||||
compatible = "starfive,fu740-otp";
|
||||
reg = <0x0 0x11810000 0x0 0x10000>;
|
||||
fuse-count = <0x200>;
|
||||
clocks = <&clkgen JH7100_CLK_OTP_APB>;
|
||||
};
|
||||
};
|
||||
};
|
||||
203
include/dt-bindings/clock/starfive-jh7100.h
Normal file
203
include/dt-bindings/clock/starfive-jh7100.h
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR X11 */
|
||||
/*
|
||||
* Copyright (C) 2021 Ahmad Fatoum, Pengutronix
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
|
||||
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
|
||||
|
||||
#define JH7100_CLK_OSC_SYS 0
|
||||
#define JH7100_CLK_OSC_AUD 1
|
||||
#define JH7100_CLK_PLL0_OUT 2
|
||||
#define JH7100_CLK_PLL1_OUT 3
|
||||
#define JH7100_CLK_PLL2_OUT 4
|
||||
#define JH7100_CLK_CPUNDBUS_ROOT 5
|
||||
#define JH7100_CLK_DLA_ROOT 6
|
||||
#define JH7100_CLK_DSP_ROOT 7
|
||||
#define JH7100_CLK_GMACUSB_ROOT 8
|
||||
#define JH7100_CLK_PERH0_ROOT 9
|
||||
#define JH7100_CLK_PERH1_ROOT 10
|
||||
#define JH7100_CLK_VIN_ROOT 11
|
||||
#define JH7100_CLK_VOUT_ROOT 12
|
||||
#define JH7100_CLK_AUDIO_ROOT 13
|
||||
#define JH7100_CLK_CDECHIFI4_ROOT 14
|
||||
#define JH7100_CLK_CDEC_ROOT 15
|
||||
#define JH7100_CLK_VOUTBUS_ROOT 16
|
||||
#define JH7100_CLK_CPUNBUS_ROOT_DIV 17
|
||||
#define JH7100_CLK_DSP_ROOT_DIV 18
|
||||
#define JH7100_CLK_PERH0_SRC 19
|
||||
#define JH7100_CLK_PERH1_SRC 20
|
||||
#define JH7100_CLK_PLL0_TESTOUT 21
|
||||
#define JH7100_CLK_PLL1_TESTOUT 22
|
||||
#define JH7100_CLK_PLL2_TESTOUT 23
|
||||
#define JH7100_CLK_PLL2_REF 24
|
||||
#define JH7100_CLK_CPU_CORE 25
|
||||
#define JH7100_CLK_CPU_AXI 26
|
||||
#define JH7100_CLK_AHB_BUS 27
|
||||
#define JH7100_CLK_APB1_BUS 28
|
||||
#define JH7100_CLK_APB2_BUS 29
|
||||
#define JH7100_CLK_DOM3AHB_BUS 30
|
||||
#define JH7100_CLK_DOM7AHB_BUS 31
|
||||
#define JH7100_CLK_U74_CORE0 32
|
||||
#define JH7100_CLK_U74_CORE1 33
|
||||
#define JH7100_CLK_U74_AXI 34
|
||||
#define JH7100_CLK_U74RTC_TOGGLE 35
|
||||
#define JH7100_CLK_SGDMA2P_AXI 36
|
||||
#define JH7100_CLK_DMA2PNOC_AXI 37
|
||||
#define JH7100_CLK_SGDMA2P_AHB 38
|
||||
#define JH7100_CLK_DLA_BUS 39
|
||||
#define JH7100_CLK_DLA_AXI 40
|
||||
#define JH7100_CLK_DLANOC_AXI 41
|
||||
#define JH7100_CLK_DLA_APB 42
|
||||
#define JH7100_CLK_VP6_CORE 43
|
||||
#define JH7100_CLK_VP6BUS_SRC 44
|
||||
#define JH7100_CLK_VP6_AXI 45
|
||||
#define JH7100_CLK_VCDECBUS_SRC 46
|
||||
#define JH7100_CLK_VDEC_BUS 47
|
||||
#define JH7100_CLK_VDEC_AXI 48
|
||||
#define JH7100_CLK_VDECBRG_MAIN 49
|
||||
#define JH7100_CLK_VDEC_BCLK 50
|
||||
#define JH7100_CLK_VDEC_CCLK 51
|
||||
#define JH7100_CLK_VDEC_APB 52
|
||||
#define JH7100_CLK_JPEG_AXI 53
|
||||
#define JH7100_CLK_JPEG_CCLK 54
|
||||
#define JH7100_CLK_JPEG_APB 55
|
||||
#define JH7100_CLK_GC300_2X 56
|
||||
#define JH7100_CLK_GC300_AHB 57
|
||||
#define JH7100_CLK_JPCGC300_AXIBUS 58
|
||||
#define JH7100_CLK_GC300_AXI 59
|
||||
#define JH7100_CLK_JPCGC300_MAIN 60
|
||||
#define JH7100_CLK_VENC_BUS 61
|
||||
#define JH7100_CLK_VENC_AXI 62
|
||||
#define JH7100_CLK_VENCBRG_MAIN 63
|
||||
#define JH7100_CLK_VENC_BCLK 64
|
||||
#define JH7100_CLK_VENC_CCLK 65
|
||||
#define JH7100_CLK_VENC_APB 66
|
||||
#define JH7100_CLK_DDRPLL_DIV2 67
|
||||
#define JH7100_CLK_DDRPLL_DIV4 68
|
||||
#define JH7100_CLK_DDRPLL_DIV8 69
|
||||
#define JH7100_CLK_DDROSC_DIV2 70
|
||||
#define JH7100_CLK_DDRC0 71
|
||||
#define JH7100_CLK_DDRC1 72
|
||||
#define JH7100_CLK_DDRPHY_APB 73
|
||||
#define JH7100_CLK_NOC_ROB 74
|
||||
#define JH7100_CLK_NOC_COG 75
|
||||
#define JH7100_CLK_NNE_AHB 76
|
||||
#define JH7100_CLK_NNEBUS_SRC1 77
|
||||
#define JH7100_CLK_NNE_BUS 78
|
||||
#define JH7100_CLK_NNE_AXI 79
|
||||
#define JH7100_CLK_NNENOC_AXI 80
|
||||
#define JH7100_CLK_DLASLV_AXI 81
|
||||
#define JH7100_CLK_DSPX2C_AXI 82
|
||||
#define JH7100_CLK_HIFI4_SRC 83
|
||||
#define JH7100_CLK_HIFI4_COREFREE 84
|
||||
#define JH7100_CLK_HIFI4_CORE 85
|
||||
#define JH7100_CLK_HIFI4_BUS 86
|
||||
#define JH7100_CLK_HIFI4_AXI 87
|
||||
#define JH7100_CLK_HIFI4NOC_AXI 88
|
||||
#define JH7100_CLK_SGDMA1P_BUS 89
|
||||
#define JH7100_CLK_SGDMA1P_AXI 90
|
||||
#define JH7100_CLK_DMA1P_AXI 91
|
||||
#define JH7100_CLK_X2C_AXI 92
|
||||
#define JH7100_CLK_USB_BUS 93
|
||||
#define JH7100_CLK_USB_AXI 94
|
||||
#define JH7100_CLK_USBNOC_AXI 95
|
||||
#define JH7100_CLK_USBPHY_ROOTDIV 96
|
||||
#define JH7100_CLK_USBPHY_125M 97
|
||||
#define JH7100_CLK_USBPHY_PLLDIV25M 98
|
||||
#define JH7100_CLK_USBPHY_25M 99
|
||||
#define JH7100_CLK_AUDIO_DIV 100
|
||||
#define JH7100_CLK_AUDIO_SRC 101
|
||||
#define JH7100_CLK_AUDIO_12288 102
|
||||
#define JH7100_CLK_VIN_SRC 103
|
||||
#define JH7100_CLK_ISP0_BUS 104
|
||||
#define JH7100_CLK_ISP0_AXI 105
|
||||
#define JH7100_CLK_ISP0NOC_AXI 106
|
||||
#define JH7100_CLK_ISPSLV_AXI 107
|
||||
#define JH7100_CLK_ISP1_BUS 108
|
||||
#define JH7100_CLK_ISP1_AXI 109
|
||||
#define JH7100_CLK_ISP1NOC_AXI 110
|
||||
#define JH7100_CLK_VIN_BUS 111
|
||||
#define JH7100_CLK_VIN_AXI 112
|
||||
#define JH7100_CLK_VINNOC_AXI 113
|
||||
#define JH7100_CLK_VOUT_SRC 114
|
||||
#define JH7100_CLK_DISPBUS_SRC 115
|
||||
#define JH7100_CLK_DISP_BUS 116
|
||||
#define JH7100_CLK_DISP_AXI 117
|
||||
#define JH7100_CLK_DISPNOC_AXI 118
|
||||
#define JH7100_CLK_SDIO0_AHB 119
|
||||
#define JH7100_CLK_SDIO0_CCLKINT 120
|
||||
#define JH7100_CLK_SDIO0_CCLKINT_INV 121
|
||||
#define JH7100_CLK_SDIO1_AHB 122
|
||||
#define JH7100_CLK_SDIO1_CCLKINT 123
|
||||
#define JH7100_CLK_SDIO1_CCLKINT_INV 124
|
||||
#define JH7100_CLK_GMAC_AHB 125
|
||||
#define JH7100_CLK_GMAC_ROOT_DIV 126
|
||||
#define JH7100_CLK_GMAC_PTP_REF 127
|
||||
#define JH7100_CLK_GMAC_GTX 128
|
||||
#define JH7100_CLK_GMAC_RMII_TX 129
|
||||
#define JH7100_CLK_GMAC_RMII_RX 130
|
||||
#define JH7100_CLK_GMAC_TX 131
|
||||
#define JH7100_CLK_GMAC_TX_INV 132
|
||||
#define JH7100_CLK_GMAC_RX_PRE 133
|
||||
#define JH7100_CLK_GMAC_RX_INV 134
|
||||
#define JH7100_CLK_GMAC_RMII 135
|
||||
#define JH7100_CLK_GMAC_TOPHYREF 136
|
||||
#define JH7100_CLK_SPI2AHB_AHB 137
|
||||
#define JH7100_CLK_SPI2AHB_CORE 138
|
||||
#define JH7100_CLK_EZMASTER_AHB 139
|
||||
#define JH7100_CLK_E24_AHB 140
|
||||
#define JH7100_CLK_E24RTC_TOGGLE 141
|
||||
#define JH7100_CLK_QSPI_AHB 142
|
||||
#define JH7100_CLK_QSPI_APB 143
|
||||
#define JH7100_CLK_QSPI_REF 144
|
||||
#define JH7100_CLK_SEC_AHB 145
|
||||
#define JH7100_CLK_AES 146
|
||||
#define JH7100_CLK_SHA 147
|
||||
#define JH7100_CLK_PKA 148
|
||||
#define JH7100_CLK_TRNG_APB 149
|
||||
#define JH7100_CLK_OTP_APB 150
|
||||
#define JH7100_CLK_UART0_APB 151
|
||||
#define JH7100_CLK_UART0_CORE 152
|
||||
#define JH7100_CLK_UART1_APB 153
|
||||
#define JH7100_CLK_UART1_CORE 154
|
||||
#define JH7100_CLK_SPI0_APB 155
|
||||
#define JH7100_CLK_SPI0_CORE 156
|
||||
#define JH7100_CLK_SPI1_APB 157
|
||||
#define JH7100_CLK_SPI1_CORE 158
|
||||
#define JH7100_CLK_I2C0_APB 159
|
||||
#define JH7100_CLK_I2C0_CORE 160
|
||||
#define JH7100_CLK_I2C1_APB 161
|
||||
#define JH7100_CLK_I2C1_CORE 162
|
||||
#define JH7100_CLK_GPIO_APB 163
|
||||
#define JH7100_CLK_UART2_APB 164
|
||||
#define JH7100_CLK_UART2_CORE 165
|
||||
#define JH7100_CLK_UART3_APB 166
|
||||
#define JH7100_CLK_UART3_CORE 167
|
||||
#define JH7100_CLK_SPI2_APB 168
|
||||
#define JH7100_CLK_SPI2_CORE 169
|
||||
#define JH7100_CLK_SPI3_APB 170
|
||||
#define JH7100_CLK_SPI3_CORE 171
|
||||
#define JH7100_CLK_I2C2_APB 172
|
||||
#define JH7100_CLK_I2C2_CORE 173
|
||||
#define JH7100_CLK_I2C3_APB 174
|
||||
#define JH7100_CLK_I2C3_CORE 175
|
||||
#define JH7100_CLK_WDTIMER_APB 176
|
||||
#define JH7100_CLK_WDT_CORE 177
|
||||
#define JH7100_CLK_TIMER0_CORE 178
|
||||
#define JH7100_CLK_TIMER1_CORE 179
|
||||
#define JH7100_CLK_TIMER2_CORE 180
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#define JH7100_CLK_TIMER3_CORE 181
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#define JH7100_CLK_TIMER4_CORE 182
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#define JH7100_CLK_TIMER5_CORE 183
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#define JH7100_CLK_TIMER6_CORE 184
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#define JH7100_CLK_VP6INTC_APB 185
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#define JH7100_CLK_PWM_APB 186
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#define JH7100_CLK_MSI_APB 187
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#define JH7100_CLK_TEMP_APB 188
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#define JH7100_CLK_TEMP_SENSE 189
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#define JH7100_CLK_SYSERR_APB 190
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#define JH7100_CLK_END 191
|
||||
|
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */
|
||||
Loading…
Add table
Reference in a new issue