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https://github.com/Fishwaldo/u-boot.git
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Fixes for 2019.01
-----BEGIN PGP SIGNATURE----- iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAlw2/EgPHHNiYWJpY0Bk ZW54LmRlAAoJECjE2NMq1et32w4MAInrLv5lIvzwlcCxsX25cbWO8TSRemt4Stbl g01Cq/yaHkTs/VTpHHqtuAy+PHBx6pFSIJNp8zheNy/VGMHavb+RSVH3d+KM6uU3 qCfVQq3ZMm4NyvbnrJSW6Uu2qmmEJQssldWuRhIIEFK1nCrYKQp9eyo215miLbFE 9b1MWFO+XV0Qz+HZQsk2ApiuvmaXu3qpvZ0tRRi9xb2dGJYYTuEcfvbehy7Iejta +JKd3wtZaKj1JDdsDFQoJs55OAdJySTSYAeNVzlstQ+1fYArB3Ju4et2QInWbXuF x/NdFAzyAtl4xOf8yQ9kbALa3TlofhPu9fJm7bniC3hf+ZPPwdS3jlvEy+DeCJIU tX/es+WgUVciiCfRHXS1RgFuHGDDpO5qi2RjSLqq6yRhlBAvXYhET2YCU9RLoLHY D57V6lkFl7jWto8xS7GoicKvGPS5MwjARw917TSocJzhJz86PeJBhOW6tR+E2/Zh kCDDCrKlyuLRg+2/eFV5H91TalwjQQ== =vYKZ -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20190110' of git://git.denx.de/u-boot-imx Fixes for 2019.01
This commit is contained in:
commit
e5aa3f4d97
17 changed files with 51 additions and 34 deletions
|
@ -123,7 +123,7 @@ F: drivers/spi/bcmstb_spi.c
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ARM FREESCALE IMX
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M: Stefano Babic <sbabic@denx.de>
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M: Fabio Estevam <fabio.estevam@nxp.com>
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R: NXP Linux Team <linux-imx@nxp.com>
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R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
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S: Maintained
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T: git git://git.denx.de/u-boot-imx.git
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F: arch/arm/cpu/arm1136/mx*/
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3
Makefile
3
Makefile
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@ -1155,6 +1155,9 @@ U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
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else
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ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
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U_BOOT_ITS := u-boot.its
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ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
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U_BOOT_ITS_DEPS += u-boot-nodtb.bin
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endif
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ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
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U_BOOT_ITS_DEPS += u-boot
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endif
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@ -200,7 +200,8 @@
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#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24)
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#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
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#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
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#define DDRMC_CR82_INT_MASK 0x10000000
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#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8)
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#define DDRMC_CR82_INT_MASK (1 << 28)
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#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
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#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
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#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
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@ -239,7 +240,7 @@
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#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
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#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16)
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#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16)
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#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x8) << 8)
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#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x7) << 8)
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#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
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#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
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#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)
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@ -244,6 +244,8 @@ enum {
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VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
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VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
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VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
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VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
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VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 = IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
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};
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#endif /* __IOMUX_VF610_H__ */
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@ -61,6 +61,8 @@ void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
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VF610_PAD_DDR_WE__DDR_WE_B,
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VF610_PAD_DDR_ODT1__DDR_ODT_0,
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VF610_PAD_DDR_ODT0__DDR_ODT_1,
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VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
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VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
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VF610_PAD_DDR_RESETB,
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};
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@ -188,7 +190,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
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writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
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DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
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writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
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writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
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@ -231,6 +232,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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/* all inits done, start the DDR controller */
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writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
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while (!(readl(&ddrmr->cr[80]) && 0x100))
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while (!(readl(&ddrmr->cr[80]) & DDRMC_CR80_MC_INIT_COMPLETE))
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udelay(10);
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writel(DDRMC_CR80_MC_INIT_COMPLETE, &ddrmr->cr[81]);
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}
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|
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@ -573,7 +573,7 @@ int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
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if (size < 100)
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return -ENOSPC;
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snprintf(buf, size, "CPU: Freescale i.MX8%s Rev%s %s at %u MHz\n",
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snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz\n",
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plat->type, plat->rev, plat->name, plat->freq_mhz);
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return 0;
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@ -250,9 +250,9 @@ static u32 get_root_src_clk(enum clk_root_src root_src)
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case OSC_25M_CLK:
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return 25000000;
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case OSC_27M_CLK:
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return 25000000;
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return 27000000;
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case OSC_32K_CLK:
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return 32000;
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return 32768;
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case ARM_PLL_CLK:
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return decode_frac_pll(root_src);
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case SYSTEM_PLL1_800M_CLK:
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@ -42,14 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define USB_CDET_GPIO 102
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static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
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/* levelling */
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{ DDRMC_CR97_WRLVL_EN, 97 },
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{ DDRMC_CR98_WRLVL_DL_0(0), 98 },
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{ DDRMC_CR99_WRLVL_DL_1(0), 99 },
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{ DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
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{ DDRMC_CR105_RDLVL_DL_0(0), 105 },
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{ DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
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{ DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
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/* AXI */
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{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
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{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
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@ -88,7 +80,7 @@ static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
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DDRMC_CR154_PAD_ZQ_MODE(1) |
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DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
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DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
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{ DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
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{ DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
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{ DDRMC_CR158_TWR(6), 158 },
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{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
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DDRMC_CR161_TODTH_WR(2), 161 },
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@ -23,11 +23,14 @@ CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_FUSE=y
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_BMP=y
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@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_VERSION_VARIABLE=y
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CONFIG_SPL_BOARD_INIT=y
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CONFIG_SPL_NAND_SUPPORT=y
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CONFIG_SPL_WATCHDOG_SUPPORT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_ASKENV=y
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CONFIG_CMD_GREPENV=y
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@ -33,6 +34,7 @@ CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_BMP=y
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CONFIG_CMD_BOOTCOUNT=y
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CONFIG_CMD_DATE=y
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CONFIG_CMD_BTRFS=y
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CONFIG_CMD_EXT4=y
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@ -44,6 +46,11 @@ CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)"
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CONFIG_CMD_UBI=y
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CONFIG_ENV_IS_IN_NAND=y
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CONFIG_BOOTCOUNT_LIMIT=y
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CONFIG_BOOTCOUNT_BOOTLIMIT=3
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CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
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CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
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CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
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CONFIG_FSL_ESDHC=y
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CONFIG_NAND=y
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CONFIG_NAND_MXC=y
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@ -58,5 +65,6 @@ CONFIG_USB_ETHER_MCS7830=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_VIDEO=y
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# CONFIG_VIDEO_SW_CURSOR is not set
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CONFIG_IMX_WATCHDOG=y
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CONFIG_FAT_WRITE=y
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CONFIG_OF_LIBFDT=y
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@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000
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CONFIG_TARGET_TBS2910=y
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CONFIG_CMD_HDMIDETECT=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_FIT=y
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CONFIG_BOOTDELAY=3
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CONFIG_PRE_CONSOLE_BUFFER=y
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CONFIG_PRE_CON_BUF_ADDR=0x7c000000
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@ -18,6 +18,7 @@ struct imx8_clks {
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const char *name;
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};
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#if CONFIG_IS_ENABLED(CMD_CLK)
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static struct imx8_clks imx8_clk_names[] = {
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{ IMX8QXP_A35_DIV, "A35_DIV" },
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{ IMX8QXP_I2C0_CLK, "I2C0" },
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@ -39,6 +40,7 @@ static struct imx8_clks imx8_clk_names[] = {
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{ IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
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{ IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
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};
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#endif
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static ulong imx8_clk_get_rate(struct clk *clk)
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{
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@ -158,7 +158,7 @@ static int sc_ipc_write(struct mu_type *base, void *data)
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static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
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int tx_size, void *rx_msg, int rx_size)
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{
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struct imx8_scu *priv = dev_get_priv(dev);
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struct imx8_scu *plat = dev_get_platdata(dev);
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sc_err_t result;
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int ret;
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@ -166,11 +166,11 @@ static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
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if (rx_msg && tx_msg != rx_msg)
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printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
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ret = sc_ipc_write(priv->base, tx_msg);
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ret = sc_ipc_write(plat->base, tx_msg);
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if (ret)
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return ret;
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if (!no_resp) {
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ret = sc_ipc_read(priv->base, rx_msg);
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ret = sc_ipc_read(plat->base, rx_msg);
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if (ret)
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return ret;
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}
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@ -182,24 +182,24 @@ static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
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static int imx8_scu_probe(struct udevice *dev)
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{
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struct imx8_scu *priv = dev_get_priv(dev);
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struct imx8_scu *plat = dev_get_platdata(dev);
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fdt_addr_t addr;
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debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
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debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);
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addr = devfdt_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = (struct mu_type *)addr;
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plat->base = (struct mu_type *)addr;
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/* U-Boot not enable interrupts, so need to enable RX interrupts */
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mu_hal_init(priv->base);
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mu_hal_init(plat->base);
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gd->arch.scu_dev = dev;
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device_probe(priv->clk);
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device_probe(priv->pinclk);
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device_probe(plat->clk);
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device_probe(plat->pinclk);
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return 0;
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}
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@ -211,7 +211,7 @@ static int imx8_scu_remove(struct udevice *dev)
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static int imx8_scu_bind(struct udevice *dev)
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{
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struct imx8_scu *priv = dev_get_priv(dev);
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struct imx8_scu *plat = dev_get_platdata(dev);
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int ret;
|
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struct udevice *child;
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int node;
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@ -227,7 +227,7 @@ static int imx8_scu_bind(struct udevice *dev)
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if (ret)
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return ret;
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priv->clk = child;
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plat->clk = child;
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node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
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"fsl,imx8qxp-iomuxc");
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@ -238,7 +238,7 @@ static int imx8_scu_bind(struct udevice *dev)
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if (ret)
|
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return ret;
|
||||
|
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priv->pinclk = child;
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plat->pinclk = child;
|
||||
|
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return 0;
|
||||
}
|
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|
@ -261,6 +261,6 @@ U_BOOT_DRIVER(imx8_scu) = {
|
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.bind = imx8_scu_bind,
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.remove = imx8_scu_remove,
|
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.ops = &imx8_scu_ops,
|
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.priv_auto_alloc_size = sizeof(struct imx8_scu),
|
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.platdata_auto_alloc_size = sizeof(struct imx8_scu),
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
|
|
|
@ -169,7 +169,7 @@ int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
|
|||
printf("%s: ctrl:%d resource:%d: res:%d\n",
|
||||
__func__, ctrl, resource, RPC_R8(&msg));
|
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|
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if (!val)
|
||||
if (val)
|
||||
*val = RPC_U32(&msg, 0U);
|
||||
|
||||
return ret;
|
||||
|
@ -194,7 +194,7 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev)
|
|||
if (ret)
|
||||
printf("%s: res:%d\n", __func__, RPC_R8(&msg));
|
||||
|
||||
if (!boot_dev)
|
||||
if (boot_dev)
|
||||
*boot_dev = RPC_U16(&msg, 0U);
|
||||
}
|
||||
|
||||
|
|
|
@ -157,6 +157,9 @@
|
|||
/* IIM Fuses */
|
||||
#define CONFIG_FSL_IIM
|
||||
|
||||
/* Watchdog */
|
||||
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
|
||||
|
||||
/*
|
||||
* Boot Linux
|
||||
*/
|
||||
|
|
|
@ -122,6 +122,8 @@
|
|||
#define CONFIG_ENV_OFFSET (384 * 1024)
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
|
||||
"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
|
||||
|
|
|
@ -968,7 +968,7 @@ int imx8image_copy_image(int outfd, struct image_tool_params *mparams)
|
|||
fprintf(stdout, "CONTAINER SW VERSION:\t0x%04x\n", sw_version);
|
||||
|
||||
build_container(soc, sector_size, emmc_fastboot,
|
||||
img_sp, false, fuse_version, sw_version, outfd);
|
||||
img_sp, true, fuse_version, sw_version, outfd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
Loading…
Add table
Reference in a new issue