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https://github.com/Fishwaldo/u-boot.git
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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
This commit is contained in:
commit
e5e3d7d520
2 changed files with 19 additions and 11 deletions
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@ -96,6 +96,23 @@ int board_early_init_f(void)
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gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
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/*
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* Reset PHY's:
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* The PHY's need a 2nd reset pulse, since the MDIO address is latched
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* upon reset, and with the first reset upon powerup, the addresses are
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* not latched reliable, since the IRQ line is multiplexed with an
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* MDIO address. A 2nd reset at this time will make sure, that the
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* correct address is latched.
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*/
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gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
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gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
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udelay(1000);
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gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
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gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
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udelay(1000);
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gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
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gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
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return 0;
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}
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@ -230,15 +247,6 @@ int misc_init_r(void)
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/* Write lime controller memory parameters */
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out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
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/*
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* Reset PHY's
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*/
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gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
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gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
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udelay(100);
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gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
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gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
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/*
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* Init display controller
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*/
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@ -432,7 +432,7 @@
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
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@ -473,7 +473,7 @@
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{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
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