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spi: davinci_spi: Move header code to driver
Move the header code into driver for more readable and easy to access it. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Rex Chang <rchang@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
This commit is contained in:
Jagan Teki
parent
a7b6ef05bf
commit
e6d2fbf70a
2 changed files with 109 additions and 122 deletions
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@ -13,7 +13,115 @@
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include "davinci_spi.h"
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struct davinci_spi_regs {
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dv_reg gcr0; /* 0x00 */
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dv_reg gcr1; /* 0x04 */
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dv_reg int0; /* 0x08 */
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dv_reg lvl; /* 0x0c */
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dv_reg flg; /* 0x10 */
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dv_reg pc0; /* 0x14 */
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dv_reg pc1; /* 0x18 */
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dv_reg pc2; /* 0x1c */
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dv_reg pc3; /* 0x20 */
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dv_reg pc4; /* 0x24 */
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dv_reg pc5; /* 0x28 */
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dv_reg rsvd[3];
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dv_reg dat0; /* 0x38 */
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dv_reg dat1; /* 0x3c */
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dv_reg buf; /* 0x40 */
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dv_reg emu; /* 0x44 */
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dv_reg delay; /* 0x48 */
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dv_reg def; /* 0x4c */
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dv_reg fmt0; /* 0x50 */
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dv_reg fmt1; /* 0x54 */
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dv_reg fmt2; /* 0x58 */
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dv_reg fmt3; /* 0x5c */
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dv_reg intvec0; /* 0x60 */
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dv_reg intvec1; /* 0x64 */
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};
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#define BIT(x) (1 << (x))
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/* SPIGCR0 */
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#define SPIGCR0_SPIENA_MASK 0x1
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#define SPIGCR0_SPIRST_MASK 0x0
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/* SPIGCR0 */
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#define SPIGCR1_CLKMOD_MASK BIT(1)
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#define SPIGCR1_MASTER_MASK BIT(0)
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#define SPIGCR1_SPIENA_MASK BIT(24)
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/* SPIPC0 */
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#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
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#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
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#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
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#define SPIPC0_EN0FUN_MASK BIT(0)
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/* SPIFMT0 */
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#define SPIFMT_SHIFTDIR_SHIFT 20
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#define SPIFMT_POLARITY_SHIFT 17
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#define SPIFMT_PHASE_SHIFT 16
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#define SPIFMT_PRESCALE_SHIFT 8
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/* SPIDAT1 */
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#define SPIDAT1_CSHOLD_SHIFT 28
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#define SPIDAT1_CSNR_SHIFT 16
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/* SPIDELAY */
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#define SPI_C2TDELAY_SHIFT 24
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#define SPI_T2CDELAY_SHIFT 16
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/* SPIBUF */
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#define SPIBUF_RXEMPTY_MASK BIT(31)
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#define SPIBUF_TXFULL_MASK BIT(29)
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/* SPIDEF */
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#define SPIDEF_CSDEF0_MASK BIT(0)
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#define SPI0_BUS 0
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#define SPI0_BASE CONFIG_SYS_SPI_BASE
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/*
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* Define default SPI0_NUM_CS as 1 for existing platforms that uses this
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* driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
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* if more than one CS is supported and by defining CONFIG_SYS_SPI0.
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*/
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#ifndef CONFIG_SYS_SPI0
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#define SPI0_NUM_CS 1
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#else
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#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
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#endif
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/*
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* define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
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* CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
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*/
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#ifdef CONFIG_SYS_SPI1
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#define SPI1_BUS 1
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#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
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#define SPI1_BASE CONFIG_SYS_SPI1_BASE
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#endif
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/*
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* define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
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* CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
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*/
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#ifdef CONFIG_SYS_SPI2
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#define SPI2_BUS 2
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#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
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#define SPI2_BASE CONFIG_SYS_SPI2_BASE
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#endif
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struct davinci_spi_slave {
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struct spi_slave slave;
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struct davinci_spi_regs *regs;
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unsigned int freq;
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};
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static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct davinci_spi_slave, slave);
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}
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void spi_init()
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{
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@ -1,121 +0,0 @@
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/*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Register definitions for the DaVinci SPI Controller
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DAVINCI_SPI_H_
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#define _DAVINCI_SPI_H_
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struct davinci_spi_regs {
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dv_reg gcr0; /* 0x00 */
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dv_reg gcr1; /* 0x04 */
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dv_reg int0; /* 0x08 */
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dv_reg lvl; /* 0x0c */
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dv_reg flg; /* 0x10 */
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dv_reg pc0; /* 0x14 */
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dv_reg pc1; /* 0x18 */
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dv_reg pc2; /* 0x1c */
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dv_reg pc3; /* 0x20 */
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dv_reg pc4; /* 0x24 */
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dv_reg pc5; /* 0x28 */
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dv_reg rsvd[3];
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dv_reg dat0; /* 0x38 */
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dv_reg dat1; /* 0x3c */
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dv_reg buf; /* 0x40 */
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dv_reg emu; /* 0x44 */
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dv_reg delay; /* 0x48 */
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dv_reg def; /* 0x4c */
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dv_reg fmt0; /* 0x50 */
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dv_reg fmt1; /* 0x54 */
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dv_reg fmt2; /* 0x58 */
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dv_reg fmt3; /* 0x5c */
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dv_reg intvec0; /* 0x60 */
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dv_reg intvec1; /* 0x64 */
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};
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#define BIT(x) (1 << (x))
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/* SPIGCR0 */
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#define SPIGCR0_SPIENA_MASK 0x1
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#define SPIGCR0_SPIRST_MASK 0x0
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/* SPIGCR0 */
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#define SPIGCR1_CLKMOD_MASK BIT(1)
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#define SPIGCR1_MASTER_MASK BIT(0)
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#define SPIGCR1_SPIENA_MASK BIT(24)
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/* SPIPC0 */
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#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
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#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
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#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
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#define SPIPC0_EN0FUN_MASK BIT(0)
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/* SPIFMT0 */
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#define SPIFMT_SHIFTDIR_SHIFT 20
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#define SPIFMT_POLARITY_SHIFT 17
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#define SPIFMT_PHASE_SHIFT 16
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#define SPIFMT_PRESCALE_SHIFT 8
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/* SPIDAT1 */
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#define SPIDAT1_CSHOLD_SHIFT 28
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#define SPIDAT1_CSNR_SHIFT 16
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/* SPIDELAY */
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#define SPI_C2TDELAY_SHIFT 24
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#define SPI_T2CDELAY_SHIFT 16
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/* SPIBUF */
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#define SPIBUF_RXEMPTY_MASK BIT(31)
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#define SPIBUF_TXFULL_MASK BIT(29)
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/* SPIDEF */
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#define SPIDEF_CSDEF0_MASK BIT(0)
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#define SPI0_BUS 0
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#define SPI0_BASE CONFIG_SYS_SPI_BASE
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/*
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* Define default SPI0_NUM_CS as 1 for existing platforms that uses this
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* driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
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* if more than one CS is supported and by defining CONFIG_SYS_SPI0.
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*/
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#ifndef CONFIG_SYS_SPI0
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#define SPI0_NUM_CS 1
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#else
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#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
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#endif
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/*
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* define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
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* CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
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*/
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#ifdef CONFIG_SYS_SPI1
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#define SPI1_BUS 1
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#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
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#define SPI1_BASE CONFIG_SYS_SPI1_BASE
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#endif
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/*
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* define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
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* CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
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*/
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#ifdef CONFIG_SYS_SPI2
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#define SPI2_BUS 2
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#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
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#define SPI2_BASE CONFIG_SYS_SPI2_BASE
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#endif
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struct davinci_spi_slave {
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struct spi_slave slave;
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struct davinci_spi_regs *regs;
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unsigned int freq;
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};
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static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
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{
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return container_of(slave, struct davinci_spi_slave, slave);
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}
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#endif /* _DAVINCI_SPI_H_ */
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