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x86: Update microcode for secondary CPUs
Each CPU needs to have its microcode loaded. Add support for this so that all CPUs will have the same version. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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5 changed files with 12 additions and 2 deletions
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@ -27,6 +27,7 @@
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#include <asm/control_regs.h>
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#include <asm/cpu.h>
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#include <asm/lapic.h>
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#include <asm/microcode.h>
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#include <asm/mp.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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@ -237,5 +237,7 @@ mtrr_table_end:
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.align 4
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_dt_ucode_base_size:
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/* These next two fields are filled in by ifdtool */
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.globl ucode_base
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ucode_base: /* Declared in microcode.h */
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.long 0 /* microcode base */
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.long 0 /* microcode size */
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@ -248,8 +248,10 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
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if (!stack)
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return -ENOMEM;
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params->stack_top = (u32)(stack + size);
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params->microcode_ptr = 0;
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#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
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params->microcode_ptr = ucode_base;
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debug("Microcode at %x\n", params->microcode_ptr);
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#endif
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params->msr_table_ptr = (u32)msr_save;
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ret = save_bsp_msrs(msr_save, sizeof(msr_save));
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if (ret < 0)
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@ -9,6 +9,9 @@
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#ifndef __ASSEMBLY__
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/* This is a declaration for ucode_base in start.S */
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extern u32 ucode_base;
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/**
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* microcode_update_intel() - Apply microcode updates
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*
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@ -102,6 +102,8 @@ temp_ram_init_romstack:
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temp_ram_init_params:
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_dt_ucode_base_size:
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/* These next two fields are filled in by ifdtool */
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.globl ucode_base
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ucode_base: /* Declared in micrcode.h */
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.long 0 /* microcode base */
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.long 0 /* microcode size */
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.long CONFIG_SYS_MONITOR_BASE /* code region base */
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