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sh: Add support SH4 cache control

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Add support SH4 cache control and flash_cache function

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu 2008-03-12 12:15:29 +09:00
parent 28e5efde4d
commit e92c95180b
2 changed files with 37 additions and 1 deletions
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3
cpu/sh4/cpu.c
View file

@ -24,6 +24,7 @@
#include <common.h> #include <common.h>
#include <command.h> #include <command.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/cache.h>
int checkcpu(void) int checkcpu(void)
{ {
@ -51,7 +52,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
void flush_cache (unsigned long addr, unsigned long size) void flush_cache (unsigned long addr, unsigned long size)
{ {
dcache_invalid_range( addr , addr + size );
} }
void icache_enable (void) void icache_enable (void)

35
include/asm-sh/cache.h Normal file
View file

@ -0,0 +1,35 @@
#ifndef __ASM_SH_CACHE_H
#define __ASM_SH_CACHE_H
#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
#define L1_CACHE_BYTES 32
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
void dcache_wback_range(u32 start, u32 end)
{
u32 v;
start &= ~(L1_CACHE_BYTES-1);
for (v = start; v < end; v+=L1_CACHE_BYTES) {
asm volatile("ocbwb %0"
: /* no output */
: "m" (__m(v)));
}
}
void dcache_invalid_range(u32 start, u32 end)
{
u32 v;
start &= ~(L1_CACHE_BYTES-1);
for (v = start; v < end; v+=L1_CACHE_BYTES) {
asm volatile("ocbi %0"
: /* no output */
: "m" (__m(v)));
}
}
#endif /* CONFIG_SH4 || CONFIG_SH4A */
#endif /* __ASM_SH_CACHE_H */