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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2014-07-01 15:11:18 +02:00
commit e99f30e105
45 changed files with 255 additions and 258 deletions
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2
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
View file

@ -14,7 +14,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/ddr2_defs.h>
#include <asm/arch/emif_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/pll_defs.h>
void davinci_enable_uart0(void)

1
arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
View file

@ -11,6 +11,7 @@
#include <nand.h>
#include <ns16550.h>
#include <post.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/dm365_lowlevel.h>
#include <asm/arch/hardware.h>

1
arch/arm/cpu/armv7/am33xx/ddr.c
View file

@ -95,6 +95,7 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
&emif_reg[nr]->emif_rd_wr_exec_thresh);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);

1
arch/arm/cpu/armv7/keystone/Makefile
View file

@ -5,7 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += aemif.o
obj-y += init.o
obj-y += psc.o
obj-y += clock.o

6
arch/arm/cpu/armv7/omap-common/mem-common.c
View file

@ -121,7 +121,8 @@ void gpmc_init(void)
writel(0x00000008, &gpmc_cfg->sysconfig);
writel(0x00000000, &gpmc_cfg->irqstatus);
writel(0x00000000, &gpmc_cfg->irqenable);
writel(0x00000000, &gpmc_cfg->timeout_control);
/* disable timeout, set a safe reset value */
writel(0x00001ff0, &gpmc_cfg->timeout_control);
#ifdef CONFIG_NOR
writel(0x00000200, &gpmc_cfg->config);
#else
@ -133,5 +134,6 @@ void gpmc_init(void)
writel(0, &gpmc_cfg->cs[0].config7);
sdelay(1000);
/* enable chip-select specific configurations */
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
if (base != 0)
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
}

4
arch/arm/cpu/armv7/omap3/board.c
View file

@ -147,7 +147,7 @@ void secure_unlock_mem(void)
* configure secure registers and exit secure world
* general use.
*****************************************************************************/
void secureworld_exit()
void secureworld_exit(void)
{
unsigned long i;
@ -178,7 +178,7 @@ void secureworld_exit()
* Description: If chip is GP/EMU(special) type, unlock the SRAM for
* general use.
*****************************************************************************/
void try_unlock_memory()
void try_unlock_memory(void)
{
int mode;
int in_sdram = is_running_in_sdram();

72
arch/arm/include/asm/arch-davinci/emif_defs.h
View file

@ -1,72 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EMIF_DEFS_H_
#define _EMIF_DEFS_H_
#include <asm/arch/hardware.h>
struct davinci_emif_regs {
u_int32_t ercsr;
u_int32_t awccr;
u_int32_t sdbcr;
u_int32_t sdrcr;
u_int32_t ab1cr;
u_int32_t ab2cr;
u_int32_t ab3cr;
u_int32_t ab4cr;
u_int32_t sdtimr;
u_int32_t ddrsr;
u_int32_t ddrphycr;
u_int32_t ddrphysr;
u_int32_t totar;
u_int32_t totactr;
u_int32_t ddrphyid_rev;
u_int32_t sdsretr;
u_int32_t eirr;
u_int32_t eimr;
u_int32_t eimsr;
u_int32_t eimcr;
u_int32_t ioctrlr;
u_int32_t iostatr;
u_int8_t rsvd0[8];
u_int32_t nandfcr;
u_int32_t nandfsr;
u_int8_t rsvd1[8];
u_int32_t nandfecc[4];
u_int8_t rsvd2[60];
u_int32_t nand4biteccload;
u_int32_t nand4bitecc[4];
u_int32_t nanderradd1;
u_int32_t nanderradd2;
u_int32_t nanderrval1;
u_int32_t nanderrval2;
};
#define davinci_emif_regs \
((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2))
#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4)
#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2)))
#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
/* Chip Select setup */
#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
#define DAVINCI_ABCR_WSETUP(n) (n << 26)
#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
#define DAVINCI_ABCR_WHOLD(n) (n << 17)
#define DAVINCI_ABCR_RSETUP(n) (n << 13)
#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
#define DAVINCI_ABCR_RHOLD(n) (n << 4)
#define DAVINCI_ABCR_TA(n) (n << 2)
#define DAVINCI_ABCR_ASIZE_16BIT 1
#define DAVINCI_ABCR_ASIZE_8BIT 0
#endif

1
arch/arm/include/asm/arch-davinci/hardware.h
View file

@ -597,7 +597,6 @@ static inline enum davinci_clk_ids get_async3_src(void)
#if defined(CONFIG_SOC_DM365)
#include <asm/arch/aintc_defs.h>
#include <asm/arch/ddr2_defs.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pll_defs.h>
#include <asm/arch/psc_defs.h>

38
arch/arm/include/asm/arch-davinci/nand_defs.h
View file

@ -1,38 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Parts shamelesly stolen from Linux Kernel source tree.
*
* ------------------------------------------------------------
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _NAND_DEFS_H_
#define _NAND_DEFS_H_
#include <asm/arch/hardware.h>
#ifdef CONFIG_SOC_DM646X
#define MASK_CLE 0x80000
#define MASK_ALE 0x40000
#else
#define MASK_CLE 0x10
#define MASK_ALE 0x08
#endif
#ifdef CONFIG_SYS_NAND_MASK_CLE
#undef MASK_CLE
#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
#endif
#ifdef CONFIG_SYS_NAND_MASK_ALE
#undef MASK_ALE
#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
#endif
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30
#define NAND_STATUS 0x70
extern void davinci_nand_init(struct nand_chip *nand);
#endif

7
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
View file

@ -9,13 +9,6 @@
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE
#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000
#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000
#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000
#define K2HK_PLL_CNTRL_BASE 0x02310000
#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)

30
arch/arm/include/asm/arch-keystone/hardware.h
View file

@ -22,32 +22,6 @@
typedef volatile unsigned int dv_reg;
typedef volatile unsigned int *dv_reg_p;
#define ASYNC_EMIF_NUM_CS 4
#define ASYNC_EMIF_MODE_NOR 0
#define ASYNC_EMIF_MODE_NAND 1
#define ASYNC_EMIF_MODE_ONENAND 2
#define ASYNC_EMIF_PRESERVE -1
struct async_emif_config {
unsigned mode;
unsigned select_strobe;
unsigned extend_wait;
unsigned wr_setup;
unsigned wr_strobe;
unsigned wr_hold;
unsigned rd_setup;
unsigned rd_strobe;
unsigned rd_hold;
unsigned turn_around;
enum {
ASYNC_EMIF_8 = 0,
ASYNC_EMIF_16 = 1,
ASYNC_EMIF_32 = 2,
} width;
};
void init_async_emif(int num_cs, struct async_emif_config *config);
struct ddr3_phy_config {
unsigned int pllcr;
unsigned int pgcr1_mask;
@ -145,6 +119,10 @@ struct ddr3_emif_config {
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
/* AEMIF */
#define KS2_AEMIF_CNTRL_BASE 0x21000a00
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif

23
arch/arm/include/asm/arch-keystone/nand_defs.h
View file

@ -1,23 +0,0 @@
/*
* nand driver definitions to re-use davinci nand driver on Keystone2
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _NAND_DEFS_H_
#define _NAND_DEFS_H_
#include <asm/arch/hardware.h>
#include <linux/mtd/nand.h>
#define MASK_CLE 0x4000
#define MASK_ALE 0x2000
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30
#define NAND_STATUS 0x70
#endif

1
arch/arm/include/asm/arch-tnetv107x/emif_defs.h
View file

@ -1 +0,0 @@
#include <asm/arch-davinci/emif_defs.h>

2
arch/arm/include/asm/arch-tnetv107x/hardware.h
View file

@ -155,4 +155,6 @@ int wdt_kick(void);
#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500)
#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380)
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
#endif /* __ASM_ARCH_HARDWARE_H */

23
arch/arm/include/asm/arch-tnetv107x/nand_defs.h
View file

@ -1,23 +0,0 @@
/*
* TNETV107X: NAND definitions
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _NAND_DEFS_H_
#define _NAND_DEFS_H_
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
#define MASK_CLE 0x4000
#define MASK_ALE 0x2000
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30
#define NAND_STATUS 0x70
extern void davinci_nand_init(struct nand_chip *nand);
#endif

55
arch/arm/include/asm/arch-keystone/emif_defs.h → arch/arm/include/asm/ti-common/davinci_nand.h
View file

@ -1,23 +1,45 @@
/*
* emif definitions to re-use davinci emif driver on Keystone2
* NAND Flash Driver
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
* Copyright (C) 2006-2014 Texas Instruments.
*
* SPDX-License-Identifier: GPL-2.0+
* Based on Linux DaVinci NAND driver by TI.
*/
#ifndef _EMIF_DEFS_H_
#define _EMIF_DEFS_H_
#ifndef _DAVINCI_NAND_H_
#define _DAVINCI_NAND_H_
#include <linux/mtd/nand.h>
#include <asm/arch/hardware.h>
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30
#define NAND_STATUS 0x70
#define MASK_CLE 0x10
#define MASK_ALE 0x08
#ifdef CONFIG_SYS_NAND_MASK_CLE
#undef MASK_CLE
#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
#endif
#ifdef CONFIG_SYS_NAND_MASK_ALE
#undef MASK_ALE
#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
#endif
struct davinci_emif_regs {
uint32_t ercsr;
uint32_t awccr;
uint32_t sdbcr;
uint32_t sdrcr;
uint32_t abncr[4];
union {
uint32_t abncr[4];
uint32_t ab1cr;
uint32_t ab2cr;
uint32_t ab3cr;
uint32_t ab4cr;
};
uint32_t sdtimr;
uint32_t ddrsr;
uint32_t ddrphycr;
@ -56,18 +78,21 @@ struct davinci_emif_regs {
#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
/* Chip Select setup */
#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
#define DAVINCI_ABCR_WSETUP(n) ((n) << 26)
#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20)
#define DAVINCI_ABCR_WHOLD(n) ((n) << 17)
#define DAVINCI_ABCR_RSETUP(n) ((n) << 13)
#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7)
#define DAVINCI_ABCR_RHOLD(n) ((n) << 4)
#define DAVINCI_ABCR_TA(n) ((n) << 2)
#define DAVINCI_ABCR_WSETUP(n) (n << 26)
#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
#define DAVINCI_ABCR_WHOLD(n) (n << 17)
#define DAVINCI_ABCR_RSETUP(n) (n << 13)
#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
#define DAVINCI_ABCR_RHOLD(n) (n << 4)
#define DAVINCI_ABCR_TA(n) (n << 2)
#define DAVINCI_ABCR_ASIZE_16BIT 1
#define DAVINCI_ABCR_ASIZE_8BIT 0
void davinci_nand_init(struct nand_chip *nand);
#endif

39
arch/arm/include/asm/ti-common/ti-aemif.h Normal file
View file

@ -0,0 +1,39 @@
/*
* AEMIF definitions
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _AEMIF_H_
#define _AEMIF_H_
#define AEMIF_NUM_CS 4
#define AEMIF_MODE_NOR 0
#define AEMIF_MODE_NAND 1
#define AEMIF_MODE_ONENAND 2
#define AEMIF_PRESERVE -1
struct aemif_config {
unsigned mode;
unsigned select_strobe;
unsigned extend_wait;
unsigned wr_setup;
unsigned wr_strobe;
unsigned wr_hold;
unsigned rd_setup;
unsigned rd_strobe;
unsigned rd_hold;
unsigned turn_around;
enum {
AEMIF_WIDTH_8 = 0,
AEMIF_WIDTH_16 = 1,
AEMIF_WIDTH_32 = 2,
} width;
};
void aemif_init(int num_cs, struct aemif_config *config);
#endif

2
board/Barix/ipam390/ipam390.c
View file

@ -20,7 +20,7 @@
#include <spi.h>
#include <spi_flash.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>

2
board/ait/cam_enc_4xx/cam_enc_4xx.c
View file

@ -16,7 +16,7 @@
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/nand_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/davinci_misc.h>
#ifdef CONFIG_DAVINCI_MMC
#include <mmc.h>

3
board/davinci/da8xxevm/da830evm.c
View file

@ -25,12 +25,11 @@
#include <net.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/davinci_misc.h>
#ifdef CONFIG_DAVINCI_MMC

2
board/davinci/da8xxevm/da850evm.c
View file

@ -16,7 +16,7 @@
#include <spi.h>
#include <spi_flash.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>

3
board/davinci/dm355evm/dm355evm.c
View file

@ -8,8 +8,7 @@
#include <nand.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/nand_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>

2
board/davinci/dm355leopard/dm355leopard.c
View file

@ -9,7 +9,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <asm/arch/nand_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>

3
board/davinci/dm365evm/dm365evm.c
View file

@ -8,8 +8,7 @@
#include <nand.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/nand_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
#include <asm/arch/davinci_misc.h>

3
board/davinci/dm6467evm/dm6467evm.c
View file

@ -8,7 +8,8 @@
#include <netdev.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/davinci_nand.h>
DECLARE_GLOBAL_DATA_PTR;

2
board/davinci/ea20/ea20.c
View file

@ -19,7 +19,7 @@
#include <net.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emif_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>

2
board/davinci/sonata/sonata.c
View file

@ -14,7 +14,7 @@
#include <common.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>

2
board/enbw/enbw_cmc/enbw_cmc.c
View file

@ -29,7 +29,7 @@
#include <asm/io.h>
#include <asm/arch/da850_lowlevel.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/emif_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux_defs.h>

2
board/omicron/calimain/calimain.c
View file

@ -18,7 +18,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <asm/arch/emif_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/pinmux_defs.h>
#include <asm/arch/davinci_misc.h>

14
board/overo/overo.c
View file

@ -267,12 +267,14 @@ int misc_init_r(void)
expansion_config.revision,
expansion_config.fab_revision);
setenv("defaultdisplay", "dvi");
setenv("expansionname", "summit");
break;
case GUMSTIX_TOBI:
printf("Recognized Tobi expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
setenv("defaultdisplay", "dvi");
setenv("expansionname", "tobi");
break;
case GUMSTIX_TOBI_DUO:
printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
@ -293,12 +295,14 @@ int misc_init_r(void)
expansion_config.revision,
expansion_config.fab_revision);
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "palo43");
break;
case GUMSTIX_CHESTNUT43:
printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "chestnut43");
break;
case GUMSTIX_PINTO:
printf("Recognized Pinto expansion board (rev %d %s)\n",
@ -310,6 +314,7 @@ int misc_init_r(void)
expansion_config.revision,
expansion_config.fab_revision);
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "gallop43");
break;
case GUMSTIX_ALTO35:
printf("Recognized Alto35 expansion board (rev %d %s)\n",
@ -317,6 +322,7 @@ int misc_init_r(void)
expansion_config.fab_revision);
MUX_ALTO35();
setenv("defaultdisplay", "lcd35");
setenv("expansionname", "alto35");
break;
case GUMSTIX_STAGECOACH:
printf("Recognized Stagecoach expansion board (rev %d %s)\n",
@ -349,8 +355,11 @@ int misc_init_r(void)
break;
case GUMSTIX_NO_EEPROM:
puts("No EEPROM on expansion board\n");
setenv("expansionname", "tobi");
break;
default:
if (expansion_id == 0x0)
setenv("expansionname", "tobi");
printf("Unrecognized expansion board 0x%08x\n", expansion_id);
break;
}
@ -360,6 +369,11 @@ int misc_init_r(void)
dieid_num_r();
if (get_cpu_family() == CPU_OMAP34XX)
setenv("boardname", "overo");
else
setenv("boardname", "overo-storm");
return 0;
}

79
board/ti/am43xx/board.c
View file

@ -217,6 +217,28 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
.emif_rd_wr_exec_thresh = 0x00000405
};
static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
.sdram_config = 0x638413b2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x00000c30,
.sdram_tim1 = 0xeaaad4db,
.sdram_tim2 = 0x266b7fda,
.sdram_tim3 = 0x107f8678,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074be4,
.temp_alert_config = 0x0,
.emif_ddr_phy_ctlr_1 = 0x0e084008,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x89,
.emif_ddr_ext_phy_ctrl_3 = 0x90,
.emif_ddr_ext_phy_ctrl_4 = 0x8e,
.emif_ddr_ext_phy_ctrl_5 = 0x8d,
.emif_rd_wr_lvl_rmp_win = 0x0,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000000,
};
const u32 ext_phy_ctrl_const_base_ddr3[] = {
0x00400040,
0x00350035,
@ -240,6 +262,48 @@ const u32 ext_phy_ctrl_const_base_ddr3[] = {
0x08102040
};
static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
/* first 5 are taken care by emif_regs */
0x00700070,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00150015,
0x00150015,
0x00150015,
0x00150015,
0x00150015,
0x00800080,
0x00800080,
0x40000000,
0x08102040,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
if (board_is_eposevm()) {
@ -248,6 +312,9 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
} else if (board_is_gpevm()) {
*regs = ext_phy_ctrl_const_base_ddr3;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
} else if (board_is_sk()) {
*regs = ext_phy_ctrl_const_base_ddr3_sk;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
}
return;
@ -257,10 +324,10 @@ const struct dpll_params *get_dpll_ddr_params(void)
{
if (board_is_eposevm())
return &epos_evm_dpll_ddr;
else if (board_is_gpevm())
else if (board_is_gpevm() || board_is_sk())
return &gp_evm_dpll_ddr;
puts(" Board not supported\n");
printf(" Board '%s' not supported\n", am43xx_board_name);
return NULL;
}
@ -410,6 +477,9 @@ void sdram_init(void)
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz, 0);
} else if (board_is_sk()) {
config_ddr(400, &ioregs_ddr3, NULL, NULL,
&ddr3_sk_emif_regs_400Mhz, 0);
}
}
#endif
@ -524,6 +594,11 @@ int board_eth_init(bd_t *bis)
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[0].phy_addr = 16;
} else if (board_is_sk()) {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
cpsw_slaves[0].phy_addr = 4;
cpsw_slaves[1].phy_addr = 5;
} else {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;

5
board/ti/am43xx/board.h
View file

@ -47,6 +47,11 @@ static inline int board_is_gpevm(void)
return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
}
static inline int board_is_sk(void)
{
return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN);
}
void enable_uart0_pin_mux(void);
void enable_board_pin_mux(void);
void enable_i2c0_pin_mux(void);

3
board/ti/am43xx/mux.c
View file

@ -97,6 +97,9 @@ void enable_board_pin_mux(void)
if (board_is_gpevm()) {
configure_module_pin_mux(gpio5_7_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
} else if (board_is_sk()) {
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(qspi_pin_mux);
} else if (board_is_eposevm()) {
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(qspi_pin_mux);

10
board/ti/k2hk_evm/board.c
View file

@ -16,9 +16,9 @@
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/psc_defs.h>
#include <asm/ti-common/ti-aemif.h>
DECLARE_GLOBAL_DATA_PTR;
@ -40,9 +40,9 @@ unsigned int external_clk[ext_clk_count] = {
what is that */
};
static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
static struct aemif_config aemif_configs[] = {
{ /* CS0 */
.mode = ASYNC_EMIF_MODE_NAND,
.mode = AEMIF_MODE_NAND,
.wr_setup = 0xf,
.wr_strobe = 0x3f,
.wr_hold = 7,
@ -50,7 +50,7 @@ static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
.rd_strobe = 0x3f,
.rd_hold = 7,
.turn_around = 3,
.width = ASYNC_EMIF_8,
.width = AEMIF_WIDTH_8,
},
};
@ -67,7 +67,7 @@ int dram_init(void)
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
return 0;
}

2
board/ti/tnetv107xevm/sdb_board.c
View file

@ -11,7 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/arch/nand_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/mux.h>
DECLARE_GLOBAL_DATA_PTR;

1
drivers/Makefile
View file

@ -14,3 +14,4 @@ obj-y += twserial/
obj-y += video/
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
obj-y += memory/

1
drivers/memory/Makefile Normal file
View file

@ -0,0 +1 @@
obj-$(CONFIG_TI_AEMIF) += ti-aemif.o

37
arch/arm/cpu/armv7/keystone/aemif.c → drivers/memory/ti-aemif.c
View file

@ -8,9 +8,13 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/emif_defs.h>
#include <asm/ti-common/ti-aemif.h>
#define AEMIF_WAITCYCLE_CONFIG (CONFIG_AEMIF_CNTRL_BASE + 0x4)
#define AEMIF_NAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x60)
#define AEMIF_ONENAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x5c)
#define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \
+ (cs * 4))
#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
@ -31,22 +35,22 @@
} \
} while (0)
void configure_async_emif(int cs, struct async_emif_config *cfg)
static void aemif_configure(int cs, struct aemif_config *cfg)
{
unsigned long tmp;
if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
tmp = __raw_readl(&davinci_emif_regs->nandfcr);
if (cfg->mode == AEMIF_MODE_NAND) {
tmp = __raw_readl(AEMIF_NAND_CONTROL);
tmp |= (1 << cs);
__raw_writel(tmp, &davinci_emif_regs->nandfcr);
__raw_writel(tmp, AEMIF_NAND_CONTROL);
} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
tmp = __raw_readl(&davinci_emif_regs->one_nand_cr);
} else if (cfg->mode == AEMIF_MODE_ONENAND) {
tmp = __raw_readl(AEMIF_ONENAND_CONTROL);
tmp |= (1 << cs);
__raw_writel(tmp, &davinci_emif_regs->one_nand_cr);
__raw_writel(tmp, AEMIF_ONENAND_CONTROL);
}
tmp = __raw_readl(&davinci_emif_regs->abncr[cs]);
tmp = __raw_readl(AEMIF_CONFIG(cs));
set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
@ -59,13 +63,18 @@ void configure_async_emif(int cs, struct async_emif_config *cfg)
set_config_field(tmp, TURN_AROUND, cfg->turn_around);
set_config_field(tmp, WIDTH, cfg->width);
__raw_writel(tmp, &davinci_emif_regs->abncr[cs]);
__raw_writel(tmp, AEMIF_CONFIG(cs));
}
void init_async_emif(int num_cs, struct async_emif_config *config)
void aemif_init(int num_cs, struct aemif_config *config)
{
int cs;
if (num_cs > AEMIF_NUM_CS) {
num_cs = AEMIF_NUM_CS;
printf("AEMIF: csnum has to be <= 5");
}
for (cs = 0; cs < num_cs; cs++)
configure_async_emif(cs, config + cs);
aemif_configure(cs, config + cs);
}

3
drivers/mtd/nand/davinci_nand.c
View file

@ -32,8 +32,7 @@
#include <common.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/emif_defs.h>
#include <asm/ti-common/davinci_nand.h>
/* Definitions for 4-bit hardware ECC */
#define NAND_TIMEOUT 10240

2
drivers/spi/davinci_spi.c
View file

@ -41,7 +41,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
break;
#ifdef CONFIG_SYS_SPI1
case SPI1_BUS:
ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
break;
#endif
#ifdef CONFIG_SYS_SPI2

2
include/configs/am43xx_evm.h
View file

@ -226,6 +226,8 @@
"setenv fdtfile am43x-epos-evm.dtb; fi; " \
"if test $board_name = AM43__GP; then " \
"setenv fdtfile am437x-gp-evm.dtb; fi; " \
"if test $board_name = AM43__SK; then " \
"setenv fdtfile am437x-sk-evm.dtb; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree; fi; \0"

2
include/configs/davinci_dm6467evm.h
View file

@ -78,6 +78,8 @@ extern unsigned int davinci_arm_clk_get(void);
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_MASK_CLE 0x80000
#define CONFIG_SYS_NAND_MASK_ALE 0x40000
#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_IS_IN_NAND

6
include/configs/k2hk_evm.h
View file

@ -129,6 +129,10 @@
#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
#define CONFIG_SYS_SGMII_RATESCALE 2
/* AEMIF */
#define CONFIG_TI_AEMIF
#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
/* NAND Configuration */
#define CONFIG_NAND_DAVINCI
#define CONFIG_CMD_NAND_ECCLAYOUT
@ -136,6 +140,8 @@
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_MASK_CLE 0x4000
#define CONFIG_SYS_NAND_MASK_ALE 0x2000
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }

10
include/configs/omap3_overo.h
View file

@ -83,7 +83,6 @@
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"fdtfile=overo.dtb\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"usbtty=cdc_acm\0" \
@ -152,10 +151,11 @@
"run mmcboot;" \
"fi;" \
"if run loadzimage; then " \
"if test -n $fdtfile; then " \
"if run loadfdt; then " \
"run mmcbootfdt;" \
"fi;" \
"if test $fdtfile; then " \
"setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
"fi;" \
"if run loadfdt; then " \
"run mmcbootfdt;" \
"fi;" \
"fi;" \
"fi;" \

2
include/configs/ti_omap4_common.h
View file

@ -126,7 +126,7 @@
"if test $board_name = panda-es; then " \
"setenv fdtfile omap4-panda-es.dtb; fi;" \
"if test $board_name = duovero; then " \
"setenv fdtfile omap4-duovero.dtb; fi;" \
"setenv fdtfile omap4-duovero-parlor.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \