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First set of u-boot-atmel fixes for 2019.07 cycle
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJc+lyDAAoJEB6zHgIOrC/I2MQH/A20fKVWQcnvmwwuJ8w/QNZ5 syNqpRLgw8jIMuLgmnUOQmjhKEsdcNWlESQt+eppTH2yMTSwNlQVT8SVE2s1podP QKBSHw4V5UXlYZwZBhrrmL3twVOf6oecoE4gzpnh1ydMHiC1zcHAJuutlNw8y+ye IVrojVPu5miN91TJuvkcGdafNdFVO4mBMhGhCFA4VN38OI6Dk/fQg4QBrxj/3XWb +EOznxL1YZYGf8hhYqe68vMVVVT5sSq1SbId6JGHRkAYDcn/qKOuOkzW7FP7tbi/ PidcTmfqOFH1EYnincxQ1cXyhaSs/VOxRHIWgzlRIJJHHp0o7Y+FUGAilSGKHso= =tnXy -----END PGP SIGNATURE----- Merge tag 'u-boot-atmel-fixes-2019.07-a' of git://git.denx.de/u-boot-atmel First set of u-boot-atmel fixes for 2019.07 cycle
This commit is contained in:
commit
eb53a18c9e
8 changed files with 65 additions and 1 deletions
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@ -44,7 +44,15 @@ static void switch_to_main_crystal_osc(void)
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#endif
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#endif
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tmp = readl(&pmc->mor);
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tmp = readl(&pmc->mor);
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/*
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* some boards have an external oscillator with driving.
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* in this case we need to disable the internal SoC driving (bypass mode)
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*/
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#if defined(CONFIG_SPL_AT91_MCK_BYPASS)
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tmp |= AT91_PMC_MOR_OSCBYPASS;
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#else
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tmp &= ~AT91_PMC_MOR_OSCBYPASS;
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tmp &= ~AT91_PMC_MOR_OSCBYPASS;
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#endif
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tmp &= ~AT91_PMC_MOR_KEY(0xff);
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tmp &= ~AT91_PMC_MOR_KEY(0xff);
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tmp |= AT91_PMC_MOR_KEY(0x37);
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tmp |= AT91_PMC_MOR_KEY(0x37);
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writel(tmp, &pmc->mor);
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writel(tmp, &pmc->mor);
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@ -73,6 +73,36 @@ int misc_init_r(void)
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/* SPL */
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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/* must set PB25 low to enable the CAN transceivers */
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static void board_can_stdby_dis(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0);
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}
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static void board_leds_init(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */
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atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */
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}
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/* deassert reset lines for external periph in case of warm reboot */
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static void board_reset_additional_periph(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */
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}
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static void board_start_additional_periph(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */
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atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */
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}
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#ifdef CONFIG_SD_BOOT
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#ifdef CONFIG_SD_BOOT
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void spl_mmc_init(void)
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void spl_mmc_init(void)
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{
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{
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@ -93,12 +123,20 @@ void spl_board_init(void)
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#ifdef CONFIG_SD_BOOT
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#ifdef CONFIG_SD_BOOT
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spl_mmc_init();
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spl_mmc_init();
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#endif
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#endif
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board_reset_additional_periph();
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board_can_stdby_dis();
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board_leds_init();
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}
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}
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void spl_display_print(void)
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void spl_display_print(void)
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{
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{
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}
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}
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void spl_board_prepare_for_boot(void)
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{
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board_start_additional_periph();
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}
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static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
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static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
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{
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{
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ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
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ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
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@ -1187,5 +1187,17 @@ config TPL_YMODEM_SUPPORT
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endif # TPL
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endif # TPL
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config SPL_AT91_MCK_BYPASS
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bool "Use external clock signal as a source of main clock for AT91 platforms"
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depends on ARCH_AT91
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default n
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help
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Use external 8 to 24 Mhz clock signal as source of main clock instead
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of an external crystal oscillator.
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This option disables the internal driving on the XOUT pin.
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The external source has to provide a stable clock on the XIN pin.
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If this option is disabled, the SoC expects a crystal oscillator
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that needs driving on both XIN and XOUT lines.
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endif # SPL
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endif # SPL
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endmenu
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endmenu
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@ -36,6 +36,7 @@ CONFIG_CMD_DM=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_NAND=y
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CONFIG_CMD_NAND=y
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CONFIG_CMD_WDT=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_PING=y
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@ -23,12 +23,12 @@ CONFIG_SD_BOOT=y
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CONFIG_BOOTDELAY=3
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_USE_BOOTARGS=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_SPL_TEXT_BASE=0x200000
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CONFIG_SPL_SEPARATE_BSS=y
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CONFIG_SPL_SEPARATE_BSS=y
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CONFIG_SPL_DISPLAY_PRINT=y
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CONFIG_SPL_DISPLAY_PRINT=y
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# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
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# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
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CONFIG_SPL_RAM_SUPPORT=y
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CONFIG_SPL_RAM_SUPPORT=y
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CONFIG_SPL_RAM_DEVICE=y
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CONFIG_SPL_RAM_DEVICE=y
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CONFIG_SPL_AT91_MCK_BYPASS=y
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CONFIG_HUSH_PARSER=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_IMI is not set
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@ -75,3 +75,4 @@ CONFIG_TIMER=y
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CONFIG_SPL_TIMER=y
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CONFIG_SPL_TIMER=y
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CONFIG_ATMEL_PIT_TIMER=y
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CONFIG_ATMEL_PIT_TIMER=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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# CONFIG_EFI_LOADER_HII is not set
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@ -51,6 +51,7 @@ CONFIG_MMC_SDHCI_ATMEL=y
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CONFIG_NAND=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_NAND_ATMEL=y
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CONFIG_ATMEL_NAND_HW_PMECC=y
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CONFIG_ATMEL_NAND_HW_PMECC=y
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CONFIG_PMECC_CAP=4
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CONFIG_DM_ETH=y
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CONFIG_DM_ETH=y
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CONFIG_MACB=y
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CONFIG_MACB=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL=y
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@ -50,6 +50,7 @@ CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ATMEL=y
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CONFIG_MMC_SDHCI_ATMEL=y
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CONFIG_NAND_ATMEL=y
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CONFIG_NAND_ATMEL=y
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CONFIG_ATMEL_NAND_HW_PMECC=y
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CONFIG_ATMEL_NAND_HW_PMECC=y
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CONFIG_PMECC_CAP=4
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CONFIG_DM_ETH=y
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CONFIG_DM_ETH=y
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CONFIG_MACB=y
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CONFIG_MACB=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL=y
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@ -59,6 +59,8 @@ CONFIG_DM_MMC=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_GENERIC_ATMEL_MCI=y
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CONFIG_NAND=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_NAND_ATMEL=y
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CONFIG_ATMEL_NAND_HW_PMECC=y
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CONFIG_PMECC_CAP=8
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=30000000
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CONFIG_SF_DEFAULT_SPEED=30000000
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