mirror of
https://github.com/Fishwaldo/u-boot.git
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lpc32xx: import device tree from Linux
Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board directly and unmodified from the latest Linux kernel. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
This commit is contained in:
Trevor Woerner
Tom Rini
parent
bd4dbf9e43
commit
eb5807e68f
3 changed files with 839 additions and 0 deletions
273
arch/arm/dts/lpc3250-ea3250.dts
Normal file
273
arch/arm/dts/lpc3250-ea3250.dts
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@ -0,0 +1,273 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Embedded Artists LPC3250 board
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*
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* Copyright 2012 Roland Stigge <stigge@antcom.de>
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*/
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/dts-v1/;
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#include "lpc32xx.dtsi"
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/ {
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model = "Embedded Artists LPC3250 board based on NXP LPC3250";
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compatible = "ea,ea3250", "nxp,lpc3250";
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x4000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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button {
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label = "Interrupt Key";
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linux,code = <103>;
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gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
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};
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key1 {
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label = "KEY1";
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linux,code = <1>;
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gpios = <&pca9532 0 0>;
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};
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key2 {
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label = "KEY2";
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linux,code = <2>;
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gpios = <&pca9532 1 0>;
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};
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key3 {
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label = "KEY3";
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linux,code = <3>;
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gpios = <&pca9532 2 0>;
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};
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key4 {
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label = "KEY4";
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linux,code = <4>;
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gpios = <&pca9532 3 0>;
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};
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joy0 {
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label = "Joystick Key 0";
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linux,code = <10>;
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gpios = <&gpio 2 0 0>; /* P2.0 */
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};
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joy1 {
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label = "Joystick Key 1";
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linux,code = <11>;
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gpios = <&gpio 2 1 0>; /* P2.1 */
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};
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joy2 {
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label = "Joystick Key 2";
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linux,code = <12>;
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gpios = <&gpio 2 2 0>; /* P2.2 */
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};
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joy3 {
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label = "Joystick Key 3";
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linux,code = <13>;
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gpios = <&gpio 2 3 0>; /* P2.3 */
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};
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joy4 {
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label = "Joystick Key 4";
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linux,code = <14>;
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gpios = <&gpio 2 4 0>; /* P2.4 */
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};
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};
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leds {
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compatible = "gpio-leds";
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/* LEDs on OEM Board */
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led1 {
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gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
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linux,default-trigger = "timer";
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default-state = "off";
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};
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led2 {
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gpios = <&gpio 2 10 1>; /* P2.10, active low */
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default-state = "off";
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};
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led3 {
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gpios = <&gpio 2 11 1>; /* P2.11, active low */
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default-state = "off";
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};
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led4 {
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gpios = <&gpio 2 12 1>; /* P2.12, active low */
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default-state = "off";
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};
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/* LEDs on Base Board */
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lede1 {
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gpios = <&pca9532 8 0>;
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default-state = "off";
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};
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lede2 {
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gpios = <&pca9532 9 0>;
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default-state = "off";
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};
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lede3 {
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gpios = <&pca9532 10 0>;
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default-state = "off";
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};
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lede4 {
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gpios = <&pca9532 11 0>;
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default-state = "off";
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};
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lede5 {
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gpios = <&pca9532 12 0>;
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default-state = "off";
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};
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lede6 {
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gpios = <&pca9532 13 0>;
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default-state = "off";
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};
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lede7 {
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gpios = <&pca9532 14 0>;
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default-state = "off";
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};
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lede8 {
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gpios = <&pca9532 15 0>;
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default-state = "off";
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};
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};
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};
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/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
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&adc {
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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uda1380: uda1380@18 {
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compatible = "nxp,uda1380";
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reg = <0x18>;
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power-gpio = <&gpio 3 10 0>;
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reset-gpio = <&gpio 3 2 0>;
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dac-clk = "wspll";
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};
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eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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};
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eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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};
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pca9532: pca9532@60 {
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compatible = "nxp,pca9532";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x60>;
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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};
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&i2cusb {
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clock-frequency = <100000>;
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isp1301: usb-transceiver@2d {
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compatible = "nxp,isp1301";
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reg = <0x2d>;
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};
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};
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&mac {
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phy-mode = "rmii";
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use-iram;
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status = "okay";
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};
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/* Here, choose exactly one from: ohci, usbd */
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&ohci /* &usbd */ {
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transceiver = <&isp1301>;
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status = "okay";
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};
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&sd {
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wp-gpios = <&pca9532 5 0>;
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cd-gpios = <&pca9532 4 0>;
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cd-inverted;
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bus-width = <4>;
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status = "okay";
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};
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/* 128MB Flash via SLC NAND controller */
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&slc {
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status = "okay";
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nxp,wdr-clks = <14>;
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nxp,wwidth = <260000000>;
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nxp,whold = <104000000>;
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nxp,wsetup = <200000000>;
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nxp,rdr-clks = <14>;
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nxp,rwidth = <34666666>;
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nxp,rhold = <104000000>;
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nxp,rsetup = <200000000>;
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nand-on-flash-bbt;
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gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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mtd0@0 {
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label = "ea3250-boot";
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reg = <0x00000000 0x00080000>;
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read-only;
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};
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mtd1@80000 {
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label = "ea3250-uboot";
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reg = <0x00080000 0x000c0000>;
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read-only;
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};
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mtd2@140000 {
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label = "ea3250-kernel";
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reg = <0x00140000 0x00400000>;
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};
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mtd3@540000 {
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label = "ea3250-rootfs";
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reg = <0x00540000 0x07ac0000>;
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};
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};
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};
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&uart1 {
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status = "okay";
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};
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&uart3 {
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status = "okay";
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};
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&uart5 {
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status = "okay";
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};
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&uart6 {
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status = "okay";
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};
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508
arch/arm/dts/lpc32xx.dtsi
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508
arch/arm/dts/lpc32xx.dtsi
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@ -0,0 +1,508 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* NXP LPC32xx SoC
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*
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* Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
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* Copyright 2012 Roland Stigge <stigge@antcom.de>
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*/
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#include <dt-bindings/clock/lpc32xx-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "nxp,lpc3220";
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interrupt-parent = <&mic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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reg = <0x0>;
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};
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};
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clocks {
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xtal_32k: xtal_32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xtal_32k";
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};
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xtal: xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <13000000>;
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clock-output-names = "xtal";
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};
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};
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x00000000 0x00000000 0x10000000>,
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<0x20000000 0x20000000 0x30000000>,
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<0xe0000000 0xe0000000 0x04000000>;
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iram: sram@8000000 {
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compatible = "mmio-sram";
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reg = <0x08000000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x08000000 0x20000>;
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};
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/*
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* Enable either SLC or MLC
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*/
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slc: flash@20020000 {
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compatible = "nxp,lpc3220-slc";
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reg = <0x20020000 0x1000>;
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clocks = <&clk LPC32XX_CLK_SLC>;
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status = "disabled";
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};
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mlc: flash@200a8000 {
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compatible = "nxp,lpc3220-mlc";
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reg = <0x200a8000 0x11000>;
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interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_MLC>;
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status = "disabled";
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};
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dma: dma@31000000 {
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compatible = "arm,pl080", "arm,primecell";
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reg = <0x31000000 0x1000>;
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interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_DMA>;
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clock-names = "apb_pclk";
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};
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usb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0x31020000 0x00001000>;
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/*
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* Enable either ohci or usbd (gadget)!
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*/
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ohci: ohci@0 {
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compatible = "nxp,ohci-nxp", "usb-ohci";
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reg = <0x0 0x300>;
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interrupt-parent = <&sic1>;
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interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
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status = "disabled";
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};
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usbd: usbd@0 {
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compatible = "nxp,lpc3220-udc";
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reg = <0x0 0x300>;
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interrupt-parent = <&sic1>;
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interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
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<30 IRQ_TYPE_LEVEL_HIGH>,
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<28 IRQ_TYPE_LEVEL_HIGH>,
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<26 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
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status = "disabled";
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};
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i2cusb: i2c@300 {
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compatible = "nxp,pnx-i2c";
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reg = <0x300 0x100>;
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interrupt-parent = <&sic1>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usbclk: clock-controller@f00 {
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compatible = "nxp,lpc3220-usb-clk";
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reg = <0xf00 0x100>;
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#clock-cells = <1>;
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};
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};
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clcd: clcd@31040000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x31040000 0x1000>;
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interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
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clock-names = "clcdclk", "apb_pclk";
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status = "disabled";
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};
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mac: ethernet@31060000 {
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compatible = "nxp,lpc-eth";
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reg = <0x31060000 0x1000>;
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interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_MAC>;
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status = "disabled";
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};
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emc: memory-controller@31080000 {
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compatible = "arm,pl175", "arm,primecell";
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reg = <0x31080000 0x1000>;
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clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
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clock-names = "mpmcclk", "apb_pclk";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xe0000000 0x01000000>,
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<1 0xe1000000 0x01000000>,
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<2 0xe2000000 0x01000000>,
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<3 0xe3000000 0x01000000>;
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status = "disabled";
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x20000000 0x20000000 0x30000000>;
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/*
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* ssp0 and spi1 are shared pins;
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* enable one in your board dts, as needed.
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*/
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ssp0: spi@20084000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x20084000 0x1000>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_SSP0>;
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clock-names = "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@20088000 {
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compatible = "nxp,lpc3220-spi";
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reg = <0x20088000 0x1000>;
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clocks = <&clk LPC32XX_CLK_SPI1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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/*
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* ssp1 and spi2 are shared pins;
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* enable one in your board dts, as needed.
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*/
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ssp1: spi@2008c000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x2008c000 0x1000>;
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interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_SSP1>;
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clock-names = "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@20090000 {
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compatible = "nxp,lpc3220-spi";
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reg = <0x20090000 0x1000>;
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clocks = <&clk LPC32XX_CLK_SPI2>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2s0: i2s@20094000 {
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compatible = "nxp,lpc3220-i2s";
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reg = <0x20094000 0x1000>;
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status = "disabled";
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};
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sd: sd@20098000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x20098000 0x1000>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
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<13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_SD>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s1: i2s@2009c000 {
|
||||
compatible = "nxp,lpc3220-i2s";
|
||||
reg = <0x2009c000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* UART5 first since it is the default console, ttyS0 */
|
||||
uart5: serial@40090000 {
|
||||
/* actually, ns16550a w/ 64 byte fifos! */
|
||||
compatible = "nxp,lpc3220-uart";
|
||||
reg = <0x40090000 0x1000>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clk LPC32XX_CLK_UART5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@40080000 {
|
||||
compatible = "nxp,lpc3220-uart";
|
||||
reg = <0x40080000 0x1000>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clk LPC32XX_CLK_UART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@40088000 {
|
||||
compatible = "nxp,lpc3220-uart";
|
||||
reg = <0x40088000 0x1000>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clk LPC32XX_CLK_UART4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@40098000 {
|
||||
compatible = "nxp,lpc3220-uart";
|
||||
reg = <0x40098000 0x1000>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
clocks = <&clk LPC32XX_CLK_UART6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@400a0000 {
|
||||
compatible = "nxp,pnx-i2c";
|
||||
reg = <0x400a0000 0x100>;
|
||||
interrupt-parent = <&sic1>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk LPC32XX_CLK_I2C1>;
|
||||
};
|
||||
|
||||
i2c2: i2c@400a8000 {
|
||||
compatible = "nxp,pnx-i2c";
|
||||
reg = <0x400a8000 0x100>;
|
||||
interrupt-parent = <&sic1>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk LPC32XX_CLK_I2C2>;
|
||||
};
|
||||
|
||||
mpwm: mpwm@400e8000 {
|
||||
compatible = "nxp,lpc3220-motor-pwm";
|
||||
reg = <0x400e8000 0x78>;
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
fab {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x20000000 0x20000000 0x30000000>;
|
||||
|
||||
/* System Control Block */
|
||||
scb {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x040004000 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clk: clock-controller@0 {
|
||||
compatible = "nxp,lpc3220-clk";
|
||||
reg = <0x00 0x114>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtal_32k>, <&xtal>;
|
||||
clock-names = "xtal_32k", "xtal";
|
||||
};
|
||||
};
|
||||
|
||||
mic: interrupt-controller@40008000 {
|
||||
compatible = "nxp,lpc3220-mic";
|
||||
reg = <0x40008000 0x4000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sic1: interrupt-controller@4000c000 {
|
||||
compatible = "nxp,lpc3220-sic";
|
||||
reg = <0x4000c000 0x4000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&mic>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
|
||||
<30 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
sic2: interrupt-controller@40010000 {
|
||||
compatible = "nxp,lpc3220-sic";
|
||||
reg = <0x40010000 0x4000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&mic>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
|
||||
<31 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
uart1: serial@40014000 {
|
||||
compatible = "nxp,lpc3220-hsuart";
|
||||
reg = <0x40014000 0x1000>;
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@40018000 {
|
||||
compatible = "nxp,lpc3220-hsuart";
|
||||
reg = <0x40018000 0x1000>;
|
||||
interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@4001c000 {
|
||||
compatible = "nxp,lpc3220-hsuart";
|
||||
reg = <0x4001c000 0x1000>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@40024000 {
|
||||
compatible = "nxp,lpc3220-rtc";
|
||||
reg = <0x40024000 0x1000>;
|
||||
interrupt-parent = <&sic1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk LPC32XX_CLK_RTC>;
|
||||
};
|
||||
|
||||
gpio: gpio@40028000 {
|
||||
compatible = "nxp,lpc3220-gpio";
|
||||
reg = <0x40028000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <3>; /* bank, pin, flags */
|
||||
};
|
||||
|
||||
timer4: timer@4002c000 {
|
||||
compatible = "nxp,lpc3220-timer";
|
||||
reg = <0x4002c000 0x1000>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk LPC32XX_CLK_TIMER4>;
|
||||
clock-names = "timerclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer5: timer@40030000 {
|
||||
compatible = "nxp,lpc3220-timer";
|
||||
reg = <0x40030000 0x1000>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk LPC32XX_CLK_TIMER5>;
|
||||
clock-names = "timerclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog: watchdog@4003c000 {
|
||||
compatible = "nxp,pnx4008-wdt";
|
||||
reg = <0x4003c000 0x1000>;
|
||||
clocks = <&clk LPC32XX_CLK_WDOG>;
|
||||
};
|
||||
|
||||
timer0: timer@40044000 {
|
||||
compatible = "nxp,lpc3220-timer";
|
||||
reg = <0x40044000 0x1000>;
|
||||
clocks = <&clk LPC32XX_CLK_TIMER0>;
|
||||
clock-names = "timerclk";
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
/*
|
||||
* TSC vs. ADC: Since those two share the same
|
||||
* hardware, you need to choose from one of the
|
||||
* following two and do 'status = "okay";' for one of
|
||||
* them
|
||||
*/
|
||||
|
||||
adc: adc@40048000 {
|
||||
compatible = "nxp,lpc3220-adc";
|
||||
reg = <0x40048000 0x1000>;
|
||||
interrupt-parent = <&sic1>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk LPC32XX_CLK_ADC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tsc: tsc@40048000 {
|
||||
compatible = "nxp,lpc3220-tsc";
|
||||
reg = <0x40048000 0x1000>;
|
||||
interrupt-parent = <&sic1>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk LPC32XX_CLK_ADC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer1: timer@4004c000 {
|
||||
compatible = "nxp,lpc3220-timer";
|
||||
reg = <0x4004c000 0x1000>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk LPC32XX_CLK_TIMER1>;
|
||||
clock-names = "timerclk";
|
||||
};
|
||||
|
||||
key: key@40050000 {
|
||||
compatible = "nxp,lpc3220-key";
|
||||
reg = <0x40050000 0x1000>;
|
||||
clocks = <&clk LPC32XX_CLK_KEY>;
|
||||
interrupt-parent = <&sic1>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer2: timer@40058000 {
|
||||
compatible = "nxp,lpc3220-timer";
|
||||
reg = <0x40058000 0x1000>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk LPC32XX_CLK_TIMER2>;
|
||||
clock-names = "timerclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@4005c000 {
|
||||
compatible = "nxp,lpc3220-pwm";
|
||||
reg = <0x4005c000 0x4>;
|
||||
clocks = <&clk LPC32XX_CLK_PWM1>;
|
||||
assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
|
||||
assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@4005c004 {
|
||||
compatible = "nxp,lpc3220-pwm";
|
||||
reg = <0x4005c004 0x4>;
|
||||
clocks = <&clk LPC32XX_CLK_PWM2>;
|
||||
assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
|
||||
assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer3: timer@40060000 {
|
||||
compatible = "nxp,lpc3220-timer";
|
||||
reg = <0x40060000 0x1000>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&clk LPC32XX_CLK_TIMER3>;
|
||||
clock-names = "timerclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
58
include/dt-bindings/clock/lpc32xx-clock.h
Normal file
58
include/dt-bindings/clock/lpc32xx-clock.h
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* This code is released using a dual license strategy: BSD/GPL
|
||||
* You can choose the licence that better fits your requirements.
|
||||
*
|
||||
* Released under the terms of 3-clause BSD License
|
||||
* Released under the terms of GNU General Public License Version 2.0
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
|
||||
#define __DT_BINDINGS_LPC32XX_CLOCK_H
|
||||
|
||||
/* LPC32XX System Control Block clocks */
|
||||
#define LPC32XX_CLK_RTC 1
|
||||
#define LPC32XX_CLK_DMA 2
|
||||
#define LPC32XX_CLK_MLC 3
|
||||
#define LPC32XX_CLK_SLC 4
|
||||
#define LPC32XX_CLK_LCD 5
|
||||
#define LPC32XX_CLK_MAC 6
|
||||
#define LPC32XX_CLK_SD 7
|
||||
#define LPC32XX_CLK_DDRAM 8
|
||||
#define LPC32XX_CLK_SSP0 9
|
||||
#define LPC32XX_CLK_SSP1 10
|
||||
#define LPC32XX_CLK_UART3 11
|
||||
#define LPC32XX_CLK_UART4 12
|
||||
#define LPC32XX_CLK_UART5 13
|
||||
#define LPC32XX_CLK_UART6 14
|
||||
#define LPC32XX_CLK_IRDA 15
|
||||
#define LPC32XX_CLK_I2C1 16
|
||||
#define LPC32XX_CLK_I2C2 17
|
||||
#define LPC32XX_CLK_TIMER0 18
|
||||
#define LPC32XX_CLK_TIMER1 19
|
||||
#define LPC32XX_CLK_TIMER2 20
|
||||
#define LPC32XX_CLK_TIMER3 21
|
||||
#define LPC32XX_CLK_TIMER4 22
|
||||
#define LPC32XX_CLK_TIMER5 23
|
||||
#define LPC32XX_CLK_WDOG 24
|
||||
#define LPC32XX_CLK_I2S0 25
|
||||
#define LPC32XX_CLK_I2S1 26
|
||||
#define LPC32XX_CLK_SPI1 27
|
||||
#define LPC32XX_CLK_SPI2 28
|
||||
#define LPC32XX_CLK_MCPWM 29
|
||||
#define LPC32XX_CLK_HSTIMER 30
|
||||
#define LPC32XX_CLK_KEY 31
|
||||
#define LPC32XX_CLK_PWM1 32
|
||||
#define LPC32XX_CLK_PWM2 33
|
||||
#define LPC32XX_CLK_ADC 34
|
||||
#define LPC32XX_CLK_HCLK_PLL 35
|
||||
#define LPC32XX_CLK_PERIPH 36
|
||||
|
||||
/* LPC32XX USB clocks */
|
||||
#define LPC32XX_USB_CLK_I2C 1
|
||||
#define LPC32XX_USB_CLK_DEVICE 2
|
||||
#define LPC32XX_USB_CLK_HOST 3
|
||||
|
||||
#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */
|
||||
Loading…
Add table
Reference in a new issue