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x86: apl: Drop the I2C config in FSP-S
This config is not actually used here and in U-Boot it seems better to set this using the device tree for each individual controller. The monolithic config of the FSP-S is only necessary if the FSP is actually configuring something, but here it is not. The FSP-S does enable/disable the various I2C ports. It might be nice to handle this using the okay/disabled property of each port, but that can be considered later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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1 changed files with 0 additions and 58 deletions
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@ -24,7 +24,6 @@
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#define HIDE_BIT BIT(0)
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#define INTEL_GSPI_MAX 3
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#define INTEL_I2C_DEV_MAX 8
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#define MAX_USB2_PORTS 8
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enum {
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@ -32,36 +31,6 @@ enum {
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CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
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};
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enum i2c_speed {
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I2C_SPEED_STANDARD = 100000,
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I2C_SPEED_FAST = 400000,
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I2C_SPEED_FAST_PLUS = 1000000,
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I2C_SPEED_HIGH = 3400000,
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I2C_SPEED_FAST_ULTRA = 5000000,
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};
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/*
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* Timing values are in units of clock period, with the clock speed
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* provided by the SOC
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*
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* TODO(sjg@chromium.org): Connect this up to the I2C driver
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*/
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struct dw_i2c_speed_config {
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enum i2c_speed speed;
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/* SCL high and low period count */
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u16 scl_lcnt;
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u16 scl_hcnt;
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/*
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* SDA hold time should be 300ns in standard and fast modes
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* and long enough for deterministic logic level change in
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* fast-plus and high speed modes.
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*
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* [15:0] SDA TX Hold Time
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* [23:16] SDA RX Hold Time
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*/
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u32 sda_hold;
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};
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/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
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enum serirq_mode {
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SERIRQ_QUIET,
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@ -69,32 +38,6 @@ enum serirq_mode {
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SERIRQ_OFF,
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};
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/*
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* This I2C controller has support for 3 independent speed configs but can
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* support both FAST_PLUS and HIGH speeds through the same set of speed
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* config registers. These are treated separately so the speed config values
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* can be provided via ACPI to the OS.
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*/
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#define DW_I2C_SPEED_CONFIG_COUNT 4
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struct dw_i2c_bus_config {
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/* Bus should be enabled in TPL with temporary base */
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int early_init;
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/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
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enum i2c_speed speed;
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/*
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* If rise_time_ns is non-zero the calculations for lcnt and hcnt
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* registers take into account the times of the bus. However, if
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* there is a match in speed_config those register values take
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* precedence
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*/
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int rise_time_ns;
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int fall_time_ns;
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int data_hold_time_ns;
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/* Specific bus speed configuration */
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struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT];
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};
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struct gspi_cfg {
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/* Bus speed in MHz */
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u32 speed_mhz;
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@ -110,7 +53,6 @@ struct gspi_cfg {
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struct soc_intel_common_config {
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int chipset_lockdown;
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struct gspi_cfg gspi[INTEL_GSPI_MAX];
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struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX];
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};
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enum pnp_settings {
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