Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

This commit is contained in:
Tom Rini 2015-01-22 20:04:17 -05:00
commit ec0cc98f2c
48 changed files with 1582 additions and 132 deletions

View file

@ -57,7 +57,7 @@ struct liodn_id_table liodn_tbl[] = {
SET_USB_LIODN(1, "fsl-usb2-dr", 553), SET_USB_LIODN(1, "fsl-usb2-dr", 553),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_DMA_LIODN(1, "fsl,elo3-dma", 147), SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227), SET_DMA_LIODN(2, "fsl,elo3-dma", 227),

View file

@ -424,7 +424,6 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void) ulong cpu_init_f(void)
{ {
ulong flag = 0;
extern void m8560_cpm_reset (void); extern void m8560_cpm_reset (void);
#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \ #if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)) (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
@ -499,18 +498,11 @@ ulong cpu_init_f(void)
in_be32(&gur->dcsrcr); in_be32(&gur->dcsrcr);
#endif #endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround(); fsl_erratum_a007212_workaround();
#endif #endif
return flag; return 0;
} }
/* Implement a dummy function for those platforms w/o SERDES */ /* Implement a dummy function for those platforms w/o SERDES */

View file

@ -15,16 +15,16 @@
#include "fsl_corenet2_serdes.h" #include "fsl_corenet2_serdes.h"
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
static u64 serdes1_prtcl_map; static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
static u64 serdes2_prtcl_map; static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_3 #ifdef CONFIG_SYS_FSL_SRDS_3
static u64 serdes3_prtcl_map; static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_4 #ifdef CONFIG_SYS_FSL_SRDS_4
static u64 serdes4_prtcl_map; static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
#endif #endif
#ifdef DEBUG #ifdef DEBUG
@ -78,24 +78,30 @@ static const char *serdes_prtcl_str[] = {
[INTERLAKEN] = "INTERLAKEN", [INTERLAKEN] = "INTERLAKEN",
[QSGMII_SW1_A] = "QSGMII_SW1_A", [QSGMII_SW1_A] = "QSGMII_SW1_A",
[QSGMII_SW1_B] = "QSGMII_SW1_B", [QSGMII_SW1_B] = "QSGMII_SW1_B",
[SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
[SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
[SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
[SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
[SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
[SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
}; };
#endif #endif
int is_serdes_configured(enum srds_prtcl device) int is_serdes_configured(enum srds_prtcl device)
{ {
u64 ret = 0; int ret = 0;
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
ret |= (1ULL << device) & serdes1_prtcl_map; ret |= serdes1_prtcl_map[device];
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
ret |= (1ULL << device) & serdes2_prtcl_map; ret |= serdes2_prtcl_map[device];
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_3 #ifdef CONFIG_SYS_FSL_SRDS_3
ret |= (1ULL << device) & serdes3_prtcl_map; ret |= serdes3_prtcl_map[device];
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_4 #ifdef CONFIG_SYS_FSL_SRDS_4
ret |= (1ULL << device) & serdes4_prtcl_map; ret |= serdes4_prtcl_map[device];
#endif #endif
return !!ret; return !!ret;
@ -171,12 +177,14 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
#define BCAP_OVD_MASK 0x10000000 #define BCAP_OVD_MASK 0x10000000
#define BYP_CAL_MASK 0x02000000 #define BYP_CAL_MASK 0x02000000
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{ {
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg; u32 cfg;
int lane; int lane;
memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
struct ccsr_sfp_regs __iomem *sfp_regs = struct ccsr_sfp_regs __iomem *sfp_regs =
(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
@ -312,38 +320,43 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
for (lane = 0; lane < SRDS_MAX_LANES; lane++) { for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
serdes_prtcl_map |= (1ULL << lane_prtcl); if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
else
serdes_prtcl_map[lane_prtcl] = 1;
} }
return serdes_prtcl_map;
} }
void fsl_serdes_init(void) void fsl_serdes_init(void)
{ {
#ifdef CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_SYS_FSL_SRDS_1
serdes1_prtcl_map = serdes_init(FSL_SRDS_1, serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR, CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL, FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT); FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_2 #ifdef CONFIG_SYS_FSL_SRDS_2
serdes2_prtcl_map = serdes_init(FSL_SRDS_2, serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL, FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT); FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_3 #ifdef CONFIG_SYS_FSL_SRDS_3
serdes3_prtcl_map = serdes_init(FSL_SRDS_3, serdes_init(FSL_SRDS_3,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL, FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT); FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
serdes3_prtcl_map);
#endif #endif
#ifdef CONFIG_SYS_FSL_SRDS_4 #ifdef CONFIG_SYS_FSL_SRDS_4
serdes4_prtcl_map = serdes_init(FSL_SRDS_4, serdes_init(FSL_SRDS_4,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL, FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT); FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
serdes4_prtcl_map);
#endif #endif
} }

View file

@ -11,6 +11,7 @@
static u8 serdes_cfg_tbl[][4] = { static u8 serdes_cfg_tbl[][4] = {
[0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1}, [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1}, [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1}, [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
@ -20,6 +21,7 @@ static u8 serdes_cfg_tbl[][4] = {
[0x56] = {PCIE1, PCIE3, PCIE2, SATA1}, [0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1}, [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1}, [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,

View file

@ -33,10 +33,10 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
[0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A, [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
PCIE2, PCIE3, QSGMII_SW1_B, SATA1}, PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
[0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A, [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B}, PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

View file

@ -15,6 +15,7 @@
#include <netdev.h> #include <netdev.h>
#include <asm/cache.h> #include <asm/cache.h>
#include <asm/io.h> #include <asm/io.h>
#include <vsc9953.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -271,5 +272,9 @@ int cpu_eth_init(bd_t *bis)
#ifdef CONFIG_FMAN_ENET #ifdef CONFIG_FMAN_ENET
fm_standard_init(bis); fm_standard_init(bis);
#endif #endif
#ifdef CONFIG_VSC9953
vsc9953_init(bis);
#endif
return 0; return 0;
} }

View file

@ -0,0 +1,15 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Dummy header file to enable CONFIG_OF_CONTROL.
* If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
* It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
* OF_CONTROL must have arch/gpio.h.
*/
#ifndef __ASM_ARCH_MX85XX_GPIO_H
#define __ASM_ARCH_MX85XX_GPIO_H
#endif

View file

@ -12,6 +12,8 @@
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
#elif defined(CONFIG_BSC9132QDS) #elif defined(CONFIG_BSC9132QDS)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
#elif defined(CONFIG_C29XPCIE)
#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
#else #else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif #endif

View file

@ -87,6 +87,13 @@ enum srds_prtcl {
SGMII_2500_FM2_DTSEC6, SGMII_2500_FM2_DTSEC6,
SGMII_2500_FM2_DTSEC9, SGMII_2500_FM2_DTSEC9,
SGMII_2500_FM2_DTSEC10, SGMII_2500_FM2_DTSEC10,
SGMII_SW1_MAC1,
SGMII_SW1_MAC2,
SGMII_SW1_MAC3,
SGMII_SW1_MAC4,
SGMII_SW1_MAC5,
SGMII_SW1_MAC6,
SERDES_PRCTL_COUNT /* Keep this item the last one */
}; };
enum srds { enum srds {

View file

@ -346,13 +346,6 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_PRAM #ifdef CONFIG_PRAM
ulong reg; ulong reg;
#endif #endif
#ifdef CONFIG_DEEP_SLEEP
const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
u32 start_addr;
typedef void (*func_t)(void);
func_t kernel_resume;
#endif
/* Pointer is writable since we allocated a register for it */ /* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@ -372,20 +365,6 @@ void board_init_f(ulong bootflag)
if ((*init_fnc_ptr) () != 0) if ((*init_fnc_ptr) () != 0)
hang(); hang();
#ifdef CONFIG_DEEP_SLEEP
/* Jump to kernel in deep sleep case */
if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
l2cache_init();
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram();
#endif
enable_cpc();
start_addr = in_be32(&scfg->sparecr[1]);
kernel_resume = (func_t)start_addr;
kernel_resume();
}
#endif
#ifdef CONFIG_POST #ifdef CONFIG_POST
post_bootmode_init(); post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL)); post_run(NULL, POST_ROM | post_bootmode_get(NULL));

View file

@ -6,3 +6,5 @@ F: include/configs/C29XPCIE.h
F: configs/C29XPCIE_defconfig F: configs/C29XPCIE_defconfig
F: configs/C29XPCIE_NAND_defconfig F: configs/C29XPCIE_NAND_defconfig
F: configs/C29XPCIE_SPIFLASH_defconfig F: configs/C29XPCIE_SPIFLASH_defconfig
F: configs/C29XPCIE_NOR_SECBOOT_defconfig
F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig

View file

@ -27,3 +27,4 @@ F: configs/P5040DS_defconfig
F: configs/P5040DS_NAND_defconfig F: configs/P5040DS_NAND_defconfig
F: configs/P5040DS_SDCARD_defconfig F: configs/P5040DS_SDCARD_defconfig
F: configs/P5040DS_SPIFLASH_defconfig F: configs/P5040DS_SPIFLASH_defconfig
F: configs/P5040DS_SECURE_BOOT_defconfig

View file

@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h> #include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h> #include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h> #include <asm/fsl_law.h>
#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -152,6 +153,19 @@ found:
#endif #endif
} }
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
void __iomem *qixis_base = (void *)QIXIS_BASE;
/* does not provide HW signals for power management */
clrbits_8(qixis_base + 0x21, 0x2);
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
phys_size_t initdram(int board_type) phys_size_t initdram(int board_type)
{ {
phys_size_t dram_size; phys_size_t dram_size;
@ -166,5 +180,10 @@ phys_size_t initdram(int board_type)
/* DDR has been initialised by first stage boot loader */ /* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size(); dram_size = fsl_ddr_sdram_size();
#endif #endif
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
return dram_size; return dram_size;
} }

View file

@ -19,10 +19,10 @@
#include <asm/fsl_liodn.h> #include <asm/fsl_liodn.h>
#include <fm_eth.h> #include <fm_eth.h>
#include <hwconfig.h> #include <hwconfig.h>
#include <asm/mpc85xx_gpio.h>
#include "../common/qixis.h" #include "../common/qixis.h"
#include "t102xqds.h" #include "t102xqds.h"
#include "t102xqds_qixis.h" #include "t102xqds_qixis.h"
#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -242,6 +242,16 @@ void board_retimer_ds125df111_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1); i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
} }
int board_early_init_f(void)
{
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
return 0;
}
int board_early_init_r(void) int board_early_init_r(void)
{ {
#ifdef CONFIG_SYS_FLASH_BASE #ifdef CONFIG_SYS_FLASH_BASE
@ -395,14 +405,3 @@ void qixis_dump_switch(void)
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
} }
} }
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* does not provide HW signals for power management */
QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif

View file

@ -43,3 +43,7 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03 #define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80 #define CPLD_BOOT_SEL 0x80
#define CPLD_PCIE_SGMII_MUX 0x80
#define CPLD_OVERRIDE_BOOT_EN 0x01
#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */

View file

@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h> #include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h> #include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h> #include <asm/fsl_law.h>
#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -136,6 +137,19 @@ found:
#endif #endif
} }
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
/* does not provide HW signals for power management */
clrbits_8(cpld_base + 0x17, 0x40);
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
phys_size_t initdram(int board_type) phys_size_t initdram(int board_type)
{ {
phys_size_t dram_size; phys_size_t dram_size;
@ -150,5 +164,10 @@ phys_size_t initdram(int board_type)
/* DDR has been initialised by first stage boot loader */ /* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size(); dram_size = fsl_ddr_sdram_size();
#endif #endif
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
return dram_size; return dram_size;
} }

View file

@ -21,6 +21,7 @@
#include <phy.h> #include <phy.h>
#include <asm/fsl_dtsec.h> #include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h> #include <asm/fsl_serdes.h>
#include "../common/fman.h"
int board_eth_init(bd_t *bis) int board_eth_init(bd_t *bis)
{ {
@ -51,15 +52,22 @@ int board_eth_init(bd_t *bis)
/* Register the 10G MDIO bus */ /* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info); fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Set the two on-board RGMII PHY address */ /* Set the on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) { switch (srds_s1) {
case 0x95: case 0x95:
/* 10G XFI with Aquantia PHY */ /* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
/* set 10G XFI with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break; break;
case 0x77:
case 0x135:
/* set the on-board 2.5G SGMII AQR105 PHY */
fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
break;
default: default:
printf("SerDes protocol 0x%x is not supported on T102xRDB\n", printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
srds_s1); srds_s1);
@ -73,6 +81,10 @@ int board_eth_init(bd_t *bis)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev); fm_info_set_mdio(i, dev);
break; break;
case PHY_INTERFACE_MODE_SGMII_2500:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default: default:
break; break;
} }
@ -95,6 +107,18 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis); return pci_eth_init(bis);
} }
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
(port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
fdt_setprop(fdt, offset, "phy-connection-type",
"sgmii-2500", 10);
fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
}
}
void fdt_fixup_board_enet(void *fdt) void fdt_fixup_board_enet(void *fdt)
{ {
} }

View file

@ -11,6 +11,7 @@
#include <mmc.h> #include <mmc.h>
#include <fsl_esdhc.h> #include <fsl_esdhc.h>
#include <spi_flash.h> #include <spi_flash.h>
#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -42,6 +43,12 @@ void board_init_f(ulong bootflag)
console_init_f(); console_init_f();
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (is_warm_boot())
fsl_dp_disable_console();
#endif
/* initialize selected port with appropriate baud rate */ /* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk(); sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;

View file

@ -16,10 +16,10 @@
#include <asm/fsl_serdes.h> #include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h> #include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h> #include <asm/fsl_liodn.h>
#include <asm/mpc85xx_gpio.h>
#include <fm_eth.h> #include <fm_eth.h>
#include "t102xrdb.h" #include "t102xrdb.h"
#include "cpld.h" #include "cpld.h"
#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -27,6 +27,11 @@ int checkboard(void)
{ {
struct cpu_type *cpu = gd->arch.cpu; struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name); printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
@ -50,7 +55,40 @@ int checkboard(void)
#endif #endif
puts("SERDES Reference Clocks:\n"); puts("SERDES Reference Clocks:\n");
if (srds_s1 == 0x95)
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
else
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
return 0;
}
static void board_mux_lane(void)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1;
u8 reg = CPLD_READ(misc_ctl_status);
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
if (srds_prtcl_s1 == 0x95) {
/* Route Lane B to PCIE */
CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
} else {
/* Route Lane B to SGMII */
CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
}
CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
}
int board_early_init_f(void)
{
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
return 0; return 0;
} }
@ -86,6 +124,7 @@ int board_early_init_r(void)
#ifdef CONFIG_SYS_DPAA_QBMAN #ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals(); setup_portals();
#endif #endif
board_mux_lane();
return 0; return 0;
} }
@ -131,14 +170,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0; return 0;
} }
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* does not provide HW signals for power management */
CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif

View file

@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h> #include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h> #include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h> #include <asm/fsl_law.h>
#include <asm/mpc85xx_gpio.h>
#include "ddr.h" #include "ddr.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -100,6 +101,19 @@ found:
#endif #endif
} }
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
void __iomem *qixis_base = (void *)QIXIS_BASE;
/* does not provide HW signals for power management */
clrbits_8(qixis_base + 0x21, 0x2);
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
phys_size_t initdram(int board_type) phys_size_t initdram(int board_type)
{ {
phys_size_t dram_size; phys_size_t dram_size;
@ -112,5 +126,10 @@ phys_size_t initdram(int board_type)
dram_size *= 0x100000; dram_size *= 0x100000;
puts(" DDR: "); puts(" DDR: ");
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
return dram_size; return dram_size;
} }

View file

@ -18,6 +18,7 @@
#include <fsl_mdio.h> #include <fsl_mdio.h>
#include <malloc.h> #include <malloc.h>
#include <asm/fsl_dtsec.h> #include <asm/fsl_dtsec.h>
#include <vsc9953.h>
#include "../common/fman.h" #include "../common/fman.h"
#include "../common/qixis.h" #include "../common/qixis.h"
@ -216,6 +217,7 @@ static void initialize_lane_to_slot(void)
lane_to_slot[1] = 7; lane_to_slot[1] = 7;
lane_to_slot[2] = 7; lane_to_slot[2] = 7;
lane_to_slot[3] = 7; lane_to_slot[3] = 7;
lane_to_slot[6] = 7;
lane_to_slot[7] = 7; lane_to_slot[7] = 7;
break; break;
case 0x8d: case 0x8d:
@ -438,6 +440,12 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_FMAN_ENET #ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info; struct memac_mdio_info memac_mdio_info;
unsigned int i; unsigned int i;
#ifdef CONFIG_VSC9953
int lane;
int phy_addr;
phy_interface_t phy_int;
struct mii_dev *bus;
#endif
printf("Initializing Fman\n"); printf("Initializing Fman\n");
set_brdcfg9_for_gtx_clk(); set_brdcfg9_for_gtx_clk();
@ -477,6 +485,7 @@ int board_eth_init(bd_t *bis)
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
switch (fm_info_get_enet_if(i)) { switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_mdio(i, NULL);
break; break;
case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_SGMII:
t1040_handle_phy_interface_sgmii(i); t1040_handle_phy_interface_sgmii(i);
@ -491,6 +500,90 @@ int board_eth_init(bd_t *bis)
} }
} }
#ifdef CONFIG_VSC9953
for (i = 0; i < VSC9953_MAX_PORTS; i++) {
lane = -1;
phy_addr = 0;
phy_int = PHY_INTERFACE_MODE_NONE;
switch (i) {
case 0:
case 1:
case 2:
case 3:
lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
/* PHYs connected over QSGMII */
if (lane >= 0) {
phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
i;
phy_int = PHY_INTERFACE_MODE_QSGMII;
break;
}
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_SW1_MAC1 + i);
if (lane < 0)
break;
/* PHYs connected over QSGMII */
if (i != 3 || lane_to_slot[lane] == 7)
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ i;
else
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
phy_int = PHY_INTERFACE_MODE_SGMII;
break;
case 4:
case 5:
case 6:
case 7:
lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
/* PHYs connected over QSGMII */
if (lane >= 0) {
phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
i - 4;
phy_int = PHY_INTERFACE_MODE_QSGMII;
break;
}
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_SW1_MAC1 + i);
/* PHYs connected over SGMII */
if (lane >= 0) {
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ i - 3;
phy_int = PHY_INTERFACE_MODE_SGMII;
}
break;
case 8:
if (serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1) < 0)
/* FM1@DTSEC1 is connected to SW1@PORT8 */
vsc9953_port_enable(i);
break;
case 9:
if (serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC2) < 0) {
/* Enable L2 On MAC2 using SCFG */
struct ccsr_scfg *scfg = (struct ccsr_scfg *)
CONFIG_SYS_MPC85xx_SCFG;
out_be32(&scfg->esgmiiselcr,
in_be32(&scfg->esgmiiselcr) |
(0x80000000));
vsc9953_port_enable(i);
}
break;
}
if (lane >= 0) {
bus = mii_dev_for_muxval(lane_to_slot[lane]);
vsc9953_port_info_set_mdio(i, bus);
vsc9953_port_enable(i);
}
vsc9953_port_info_set_phy_address(i, phy_addr);
vsc9953_port_info_set_phy_int(i, phy_int);
}
#endif
cpu_eth_init(bis); cpu_eth_init(bis);
#endif #endif

View file

@ -19,8 +19,8 @@
#include <asm/fsl_liodn.h> #include <asm/fsl_liodn.h>
#include <fm_eth.h> #include <fm_eth.h>
#include <hwconfig.h> #include <hwconfig.h>
#include <asm/mpc85xx_gpio.h>
#include "../common/sleep.h"
#include "../common/qixis.h" #include "../common/qixis.h"
#include "t1040qds.h" #include "t1040qds.h"
#include "t1040qds_qixis.h" #include "t1040qds_qixis.h"
@ -115,6 +115,16 @@ static void qe_board_setup(void)
} }
} }
int board_early_init_f(void)
{
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
return 0;
}
int board_early_init_r(void) int board_early_init_r(void)
{ {
#ifdef CONFIG_SYS_FLASH_BASE #ifdef CONFIG_SYS_FLASH_BASE
@ -281,14 +291,3 @@ int board_need_mem_reset(void)
{ {
return 1; return 1;
} }
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* does not provide HW signals for power management */
QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif

View file

@ -21,3 +21,4 @@ T1040RDB_SECURE_BOOT BOARD
M: Aneesh Bansal <aneesh.bansal@freescale.com> M: Aneesh Bansal <aneesh.bansal@freescale.com>
S: Maintained S: Maintained
F: configs/T1040RDB_SECURE_BOOT_defconfig F: configs/T1040RDB_SECURE_BOOT_defconfig
F: configs/T1042RDB_SECURE_BOOT_defconfig

View file

@ -6,11 +6,13 @@
#include <common.h> #include <common.h>
#include <netdev.h> #include <netdev.h>
#include <asm/fsl_serdes.h>
#include <asm/immap_85xx.h> #include <asm/immap_85xx.h>
#include <fm_eth.h> #include <fm_eth.h>
#include <fsl_mdio.h> #include <fsl_mdio.h>
#include <malloc.h> #include <malloc.h>
#include <asm/fsl_dtsec.h> #include <asm/fsl_dtsec.h>
#include <vsc9953.h>
#include "../common/fman.h" #include "../common/fman.h"
@ -20,6 +22,11 @@ int board_eth_init(bd_t *bis)
struct memac_mdio_info memac_mdio_info; struct memac_mdio_info memac_mdio_info;
unsigned int i; unsigned int i;
int phy_addr = 0; int phy_addr = 0;
#ifdef CONFIG_VSC9953
phy_interface_t phy_int;
struct mii_dev *bus;
#endif
printf("Initializing Fman\n"); printf("Initializing Fman\n");
memac_mdio_info.regs = memac_mdio_info.regs =
@ -72,10 +79,58 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(i, 0); fm_info_set_phy_address(i, 0);
break; break;
} }
if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
fm_info_set_mdio(i, NULL);
else
fm_info_set_mdio(i, fm_info_set_mdio(i,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); miiphy_get_dev_by_name(
DEFAULT_FM_MDIO_NAME));
} }
#ifdef CONFIG_VSC9953
/* SerDes configured for QSGMII */
if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
for (i = 0; i < 4; i++) {
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus);
vsc9953_port_info_set_phy_address(i, phy_addr);
vsc9953_port_info_set_phy_int(i, phy_int);
vsc9953_port_enable(i);
}
}
if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
for (i = 4; i < 8; i++) {
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus);
vsc9953_port_info_set_phy_address(i, phy_addr);
vsc9953_port_info_set_phy_int(i, phy_int);
vsc9953_port_enable(i);
}
}
/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
vsc9953_port_enable(8);
/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
/* Enable L2 On MAC2 using SCFG */
struct ccsr_scfg *scfg = (struct ccsr_scfg *)
CONFIG_SYS_MPC85xx_SCFG;
out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
(0x80000000));
vsc9953_port_enable(9);
}
#endif
cpu_eth_init(bis); cpu_eth_init(bis);
#endif #endif

View file

@ -101,7 +101,7 @@ int board_eth_init(bd_t *bis)
} }
#if (CONFIG_SYS_NUM_FMAN == 2) #if (CONFIG_SYS_NUM_FMAN == 2)
if (srds_prtcl_s2 == 56) { if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
/* SGMII && XFI */ /* SGMII && XFI */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);

View file

@ -1,7 +1,7 @@
#PBL preamble and RCW header #PBL preamble and RCW header
aa55aa55 010e0100 aa55aa55 010e0100
#serdes protocol 27_56_1_9 #serdes protocol 27_55_1_9
16070019 18101916 00000000 00000000 16070019 18101916 00000000 00000000
6c700848 00448c00 6c020000 f5000000 6c6e0848 00448c00 6c020000 f5000000
00000000 ee0000ee 00000000 000287fc 00000000 ee0000ee 00000000 000287fc
00000000 50000000 00000000 00000028 00000000 50000000 00000000 00000028

View file

@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y

View file

@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y

View file

@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y

View file

@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XQDS=y

View file

@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T104XRDB=y

48
doc/README.t1040-l2switch Normal file
View file

@ -0,0 +1,48 @@
This file contains information for VSC9953, a Vitesse L2 Switch IP
which is integrated in the T1040/T1020 Freescale SoCs.
About Device:
=============
VSC9953 is an 8-port Gigabit Ethernet switch supports the following features:
- 8192 MAC addresses
- Static Address provisioning
- Dynamic learning of MAC addresses and aging
- 4096 VLANs
- Independent and shared VLAN learning (IVL, SVL)
- Policing with storm control and MC/BC protection
- IPv4 and IPv6 multicast
- Jumbo frames (9.6 KB)
- Access Control List
- VLAN editing, translation and remarking
- RMON counters per port
Switch interfaces:
- 8 Gigabit switch ports (ports 0 to 7) are external and are connected to external PHYs
- 2 switch ports (ports 8 and 9) of 2.5 G are connected (fixed links)
to FMan ports (FM1@DTSEC1 and FM1@DTSEC2)
Commands Overview:
=============
Commands supported
- enable/disable a port
- check a port's link speed, duplexity and status.
Commands syntax
ethsw port <port_nr> enable|disable - enable/disable an l2 switch port
ethsw port <port_nr> show - show an l2 switch port's configuration
port_nr=0..9; use "all" for all ports
=> ethsw port all show
Port Status Link Speed Duplex
0 enabled down 10 half
1 enabled down 10 half
2 enabled down 10 half
3 enabled up 1000 full
4 disabled down - half
5 disabled down - half
6 disabled down - half
7 disabled down - half
8 enabled up 2500 full
9 enabled up 2500 full
=>

View file

@ -66,3 +66,4 @@ obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/ obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/
obj-$(CONFIG_VSC9953) += vsc9953.o

View file

@ -410,11 +410,16 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd)
fmc_tx_port_graceful_stop_disable(fm_eth); fmc_tx_port_graceful_stop_disable(fm_eth);
#ifdef CONFIG_PHYLIB #ifdef CONFIG_PHYLIB
if (fm_eth->phydev) {
ret = phy_startup(fm_eth->phydev); ret = phy_startup(fm_eth->phydev);
if (ret) { if (ret) {
printf("%s: Could not initialize\n", fm_eth->phydev->dev->name); printf("%s: Could not initialize\n",
fm_eth->phydev->dev->name);
return ret; return ret;
} }
} else {
return 0;
}
#else #else
fm_eth->phydev->speed = SPEED_1000; fm_eth->phydev->speed = SPEED_1000;
fm_eth->phydev->link = 1; fm_eth->phydev->link = 1;
@ -447,6 +452,7 @@ static void fm_eth_halt(struct eth_device *dev)
/* disable bmi Rx port */ /* disable bmi Rx port */
bmi_rx_port_disable(fm_eth->rx_port); bmi_rx_port_disable(fm_eth->rx_port);
if (fm_eth->phydev)
phy_shutdown(fm_eth->phydev); phy_shutdown(fm_eth->phydev);
} }
@ -625,12 +631,13 @@ static int init_phy(struct eth_device *dev)
if (fm_eth->bus) { if (fm_eth->bus) {
phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev, phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
fm_eth->enet_if); fm_eth->enet_if);
}
if (!phydev) { if (!phydev) {
printf("Failed to connect\n"); printf("Failed to connect\n");
return -1; return -1;
} }
} else {
return 0;
}
if (fm_eth->type == FM_ETH_1G_E) { if (fm_eth->type == FM_ETH_1G_E) {
supported = (SUPPORTED_10baseT_Half | supported = (SUPPORTED_10baseT_Half |
@ -711,8 +718,7 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
if (!fm_eth_startup(fm_eth)) if (!fm_eth_startup(fm_eth))
return 0; return 0;
if (init_phy(dev)) init_phy(dev);
return 0;
/* clear the ethernet address */ /* clear the ethernet address */
for (i = 0; i < 6; i++) for (i = 0; i < 6; i++)

View file

@ -50,7 +50,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
switch (port) { switch (port) {
case FM1_DTSEC1: case FM1_DTSEC1:
case FM1_DTSEC2: case FM1_DTSEC2:
if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1)) if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) ||
is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_QSGMII; return PHY_INTERFACE_MODE_QSGMII;
case FM1_DTSEC3: case FM1_DTSEC3:
case FM1_DTSEC4: case FM1_DTSEC4:

View file

@ -11,6 +11,7 @@ obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o
obj-$(CONFIG_PHYLIB) += phy.o obj-$(CONFIG_PHYLIB) += phy.o
obj-$(CONFIG_PHYLIB_10G) += generic_10g.o obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o
obj-$(CONFIG_PHY_ATHEROS) += atheros.o obj-$(CONFIG_PHY_ATHEROS) += atheros.o
obj-$(CONFIG_PHY_BROADCOM) += broadcom.o obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
obj-$(CONFIG_PHY_CORTINA) += cortina.o obj-$(CONFIG_PHY_CORTINA) += cortina.o

156
drivers/net/phy/aquantia.c Normal file
View file

@ -0,0 +1,156 @@
/*
* Aquantia PHY drivers
*
* SPDX-License-Identifier: GPL-2.0+
*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#include <config.h>
#include <common.h>
#include <phy.h>
#ifndef CONFIG_PHYLIB_10G
#error The Aquantia PHY needs 10G support
#endif
#define AQUNTIA_10G_CTL 0x20
#define AQUNTIA_VENDOR_P1 0xc400
#define AQUNTIA_SPEED_LSB_MASK 0x2000
#define AQUNTIA_SPEED_MSB_MASK 0x40
int aquantia_config(struct phy_device *phydev)
{
u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
/* 1000BASE-T mode */
phydev->advertising = SUPPORTED_1000baseT_Full;
phydev->supported = phydev->advertising;
val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
} else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) {
/* 10GBASE-T mode */
phydev->advertising = SUPPORTED_10000baseT_Full;
phydev->supported = phydev->advertising;
if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
!(val & AQUNTIA_SPEED_MSB_MASK))
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
AQUNTIA_SPEED_LSB_MASK |
AQUNTIA_SPEED_MSB_MASK);
} else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) {
/* 2.5GBASE-T mode */
phydev->advertising = SUPPORTED_1000baseT_Full;
phydev->supported = phydev->advertising;
phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
} else if (phydev->interface == PHY_INTERFACE_MODE_MII) {
/* 100BASE-TX mode */
phydev->advertising = SUPPORTED_100baseT_Full;
phydev->supported = phydev->advertising;
val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
}
return 0;
}
int aquantia_startup(struct phy_device *phydev)
{
u32 reg, speed;
int i = 0;
phydev->duplex = DUPLEX_FULL;
/* if the AN is still in progress, wait till timeout. */
phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
if (!(reg & MDIO_AN_STAT1_COMPLETE)) {
printf("%s Waiting for PHY auto negotiation to complete",
phydev->dev->name);
do {
udelay(1000);
reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
if ((i++ % 500) == 0)
printf(".");
} while (!(reg & MDIO_AN_STAT1_COMPLETE) &&
i < (4 * PHY_ANEG_TIMEOUT));
if (i > PHY_ANEG_TIMEOUT)
printf(" TIMEOUT !\n");
}
/* Read twice because link state is latched and a
* read moves the current state into the register */
phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
phydev->link = 0;
else
phydev->link = 1;
speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
if (speed & AQUNTIA_SPEED_MSB_MASK) {
if (speed & AQUNTIA_SPEED_LSB_MASK)
phydev->speed = SPEED_10000;
else
phydev->speed = SPEED_1000;
} else {
if (speed & AQUNTIA_SPEED_LSB_MASK)
phydev->speed = SPEED_100;
else
phydev->speed = SPEED_10;
}
return 0;
}
struct phy_driver aq1202_driver = {
.name = "Aquantia AQ1202",
.uid = 0x3a1b445,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
};
struct phy_driver aq2104_driver = {
.name = "Aquantia AQ2104",
.uid = 0x3a1b460,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
};
struct phy_driver aqr105_driver = {
.name = "Aquantia AQR105",
.uid = 0x3a1b4a2,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
.mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
MDIO_MMD_PHYXS | MDIO_MMD_AN |
MDIO_MMD_VEND1),
.config = &aquantia_config,
.startup = &aquantia_startup,
.shutdown = &gen10g_shutdown,
};
int phy_aquantia_init(void)
{
phy_register(&aq1202_driver);
phy_register(&aq2104_driver);
phy_register(&aqr105_driver);
return 0;
}

View file

@ -442,6 +442,9 @@ static LIST_HEAD(phy_drivers);
int phy_init(void) int phy_init(void)
{ {
#ifdef CONFIG_PHY_AQUANTIA
phy_aquantia_init();
#endif
#ifdef CONFIG_PHY_ATHEROS #ifdef CONFIG_PHY_ATHEROS
phy_atheros_init(); phy_atheros_init();
#endif #endif

497
drivers/net/vsc9953.c Normal file
View file

@ -0,0 +1,497 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Driver for the Vitesse VSC9953 L2 Switch
*/
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <fm_eth.h>
#include <asm/fsl_memac.h>
#include <vsc9953.h>
static struct vsc9953_info vsc9953_l2sw = {
.port[0] = VSC9953_PORT_INFO_INITIALIZER(0),
.port[1] = VSC9953_PORT_INFO_INITIALIZER(1),
.port[2] = VSC9953_PORT_INFO_INITIALIZER(2),
.port[3] = VSC9953_PORT_INFO_INITIALIZER(3),
.port[4] = VSC9953_PORT_INFO_INITIALIZER(4),
.port[5] = VSC9953_PORT_INFO_INITIALIZER(5),
.port[6] = VSC9953_PORT_INFO_INITIALIZER(6),
.port[7] = VSC9953_PORT_INFO_INITIALIZER(7),
.port[8] = VSC9953_PORT_INFO_INITIALIZER(8),
.port[9] = VSC9953_PORT_INFO_INITIALIZER(9),
};
void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus)
{
if (!VSC9953_PORT_CHECK(port))
return;
vsc9953_l2sw.port[port].bus = bus;
}
void vsc9953_port_info_set_phy_address(int port, int address)
{
if (!VSC9953_PORT_CHECK(port))
return;
vsc9953_l2sw.port[port].phyaddr = address;
}
void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int)
{
if (!VSC9953_PORT_CHECK(port))
return;
vsc9953_l2sw.port[port].enet_if = phy_int;
}
void vsc9953_port_enable(int port)
{
if (!VSC9953_PORT_CHECK(port))
return;
vsc9953_l2sw.port[port].enabled = 1;
}
void vsc9953_port_disable(int port)
{
if (!VSC9953_PORT_CHECK(port))
return;
vsc9953_l2sw.port[port].enabled = 0;
}
static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr,
int regnum, int value)
{
int timeout = 50000;
out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) |
((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
(0x1 << 1));
asm("sync");
while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout)
udelay(1);
if (timeout == 0)
debug("Timeout waiting for MDIO write\n");
}
static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr,
int regnum)
{
int value = 0xFFFF;
int timeout = 50000;
while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout)
udelay(1);
if (timeout == 0) {
debug("Timeout waiting for MDIO operation to finish\n");
return value;
}
/* Put the address of the phy, and the register
* number into MIICMD
*/
out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) |
((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) |
(0x2 << 1));
timeout = 50000;
/* Wait for the the indication that the read is done */
while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout)
udelay(1);
if (timeout == 0)
debug("Timeout waiting for MDIO read\n");
/* Grab the value read from the PHY */
value = in_le32(&phyregs->miimdata);
if ((value & 0x00030000) == 0)
return value & 0x0000ffff;
return value;
}
static int init_phy(struct eth_device *dev)
{
struct vsc9953_port_info *l2sw_port = dev->priv;
struct phy_device *phydev = NULL;
#ifdef CONFIG_PHYLIB
if (!l2sw_port->bus)
return 0;
phydev = phy_connect(l2sw_port->bus, l2sw_port->phyaddr, dev,
l2sw_port->enet_if);
if (!phydev) {
printf("Failed to connect\n");
return -1;
}
phydev->supported &= SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Full;
phydev->advertising = phydev->supported;
l2sw_port->phydev = phydev;
phy_config(phydev);
#endif
return 0;
}
static int vsc9953_port_init(int port)
{
struct eth_device *dev;
/* Internal ports never have a PHY */
if (VSC9953_INTERNAL_PORT_CHECK(port))
return 0;
/* alloc eth device */
dev = (struct eth_device *)calloc(1, sizeof(struct eth_device));
if (!dev)
return 1;
sprintf(dev->name, "SW@PORT%d", port);
dev->priv = &vsc9953_l2sw.port[port];
dev->init = NULL;
dev->halt = NULL;
dev->send = NULL;
dev->recv = NULL;
if (init_phy(dev)) {
free(dev);
return 1;
}
return 0;
}
void vsc9953_init(bd_t *bis)
{
u32 i, hdx_cfg = 0, phy_addr = 0;
int timeout;
struct vsc9953_system_reg *l2sys_reg;
struct vsc9953_qsys_reg *l2qsys_reg;
struct vsc9953_dev_gmii *l2dev_gmii_reg;
struct vsc9953_analyzer *l2ana_reg;
struct vsc9953_devcpu_gcb *l2dev_gcb;
l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET +
VSC9953_DEV_GMII_OFFSET);
l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET +
VSC9953_ANA_OFFSET);
l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET +
VSC9953_SYS_OFFSET);
l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
VSC9953_QSYS_OFFSET);
l2dev_gcb = (struct vsc9953_devcpu_gcb *)(VSC9953_OFFSET +
VSC9953_DEVCPU_GCB);
out_le32(&l2dev_gcb->chip_regs.soft_rst,
CONFIG_VSC9953_SOFT_SWC_RST_ENA);
timeout = 50000;
while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) &
CONFIG_VSC9953_SOFT_SWC_RST_ENA) && --timeout)
udelay(1); /* busy wait for vsc9953 soft reset */
if (timeout == 0)
debug("Timeout waiting for VSC9953 to reset\n");
out_le32(&l2sys_reg->sys.reset_cfg, CONFIG_VSC9953_MEM_ENABLE |
CONFIG_VSC9953_MEM_INIT);
timeout = 50000;
while ((in_le32(&l2sys_reg->sys.reset_cfg) &
CONFIG_VSC9953_MEM_INIT) && --timeout)
udelay(1); /* busy wait for vsc9953 memory init */
if (timeout == 0)
debug("Timeout waiting for VSC9953 memory to initialize\n");
out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg)
| CONFIG_VSC9953_CORE_ENABLE));
/* VSC9953 Setting to be done once only */
out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00);
for (i = 0; i < VSC9953_MAX_PORTS; i++) {
if (vsc9953_port_init(i))
printf("Failed to initialize l2switch port %d\n", i);
/* Enable VSC9953 GMII Ports Port ID 0 - 7 */
if (VSC9953_INTERNAL_PORT_CHECK(i)) {
out_le32(&l2ana_reg->pfc[i].pfc_cfg,
CONFIG_VSC9953_PFC_FC_QSGMII);
out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
CONFIG_VSC9953_MAC_FC_CFG_QSGMII);
} else {
out_le32(&l2ana_reg->pfc[i].pfc_cfg,
CONFIG_VSC9953_PFC_FC);
out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i],
CONFIG_VSC9953_MAC_FC_CFG);
}
out_le32(&l2dev_gmii_reg->port_mode.clock_cfg,
CONFIG_VSC9953_CLOCK_CFG);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg,
CONFIG_VSC9953_MAC_ENA_CFG);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg,
CONFIG_VSC9953_MAC_MODE_CFG);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg,
CONFIG_VSC9953_MAC_IFG_CFG);
/* mac_hdx_cfg varies with port id*/
hdx_cfg = (CONFIG_VSC9953_MAC_HDX_CFG | (i << 16));
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg);
out_le32(&l2sys_reg->sys.front_port_mode[i],
CONFIG_VSC9953_FRONT_PORT_MODE);
out_le32(&l2qsys_reg->sys.switch_port_mode[i],
CONFIG_VSC9953_PORT_ENA);
out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg,
CONFIG_VSC9953_MAC_MAX_LEN);
out_le32(&l2sys_reg->pause_cfg.pause_cfg[i],
CONFIG_VSC9953_PAUSE_CFG);
/* WAIT FOR 2 us*/
udelay(2);
l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(
(char *)l2dev_gmii_reg
+ T1040_SWITCH_GMII_DEV_OFFSET);
/* Initialize Lynx PHY Wrappers */
phy_addr = 0;
if (vsc9953_l2sw.port[i].enet_if ==
PHY_INTERFACE_MODE_QSGMII)
phy_addr = (i + 0x4) & 0x1F;
else if (vsc9953_l2sw.port[i].enet_if ==
PHY_INTERFACE_MODE_SGMII)
phy_addr = (i + 1) & 0x1F;
if (phy_addr) {
/* SGMII IF mode + AN enable */
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
0x14, PHY_SGMII_IF_MODE_AN |
PHY_SGMII_IF_MODE_SGMII);
/* Dev ability according to SGMII specification */
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
0x4, PHY_SGMII_DEV_ABILITY_SGMII);
/* Adjust link timer for SGMII
* 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40
*/
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
0x13, 0x0003);
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
0x12, 0x0d40);
/* Restart AN */
vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr,
0x0, PHY_SGMII_CR_DEF_VAL |
PHY_SGMII_CR_RESET_AN);
timeout = 50000;
while ((vsc9953_mdio_read(&l2dev_gcb->mii_mng[0],
phy_addr, 0x01) & 0x0020) && --timeout)
udelay(1); /* wait for AN to complete */
if (timeout == 0)
debug("Timeout waiting for AN to complete\n");
}
}
printf("VSC9953 L2 switch initialized\n");
return;
}
#ifdef CONFIG_VSC9953_CMD
/* Enable/disable status of a VSC9953 port */
static void vsc9953_port_status_set(int port_nr, u8 enabled)
{
u32 val;
struct vsc9953_qsys_reg *l2qsys_reg;
/* Administrative down */
if (vsc9953_l2sw.port[port_nr].enabled == 0)
return;
l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
VSC9953_QSYS_OFFSET);
val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_nr]);
if (enabled == 1)
val |= (1 << 13);
else
val &= ~(1 << 13);
out_le32(&l2qsys_reg->sys.switch_port_mode[port_nr], val);
}
/* Set all VSC9953 ports' status */
static void vsc9953_port_all_status_set(u8 enabled)
{
int i;
for (i = 0; i < VSC9953_MAX_PORTS; i++)
vsc9953_port_status_set(i, enabled);
}
/* Start autonegotiation for a VSC9953 PHY */
static void vsc9953_phy_autoneg(int port_nr)
{
if (!vsc9953_l2sw.port[port_nr].phydev)
return;
if (vsc9953_l2sw.port[port_nr].phydev->drv->startup(
vsc9953_l2sw.port[port_nr].phydev))
printf("Failed to start PHY for port %d\n", port_nr);
}
/* Start autonegotiation for all VSC9953 PHYs */
static void vsc9953_phy_all_autoneg(void)
{
int i;
for (i = 0; i < VSC9953_MAX_PORTS; i++)
vsc9953_phy_autoneg(i);
}
/* Print a VSC9953 port's configuration */
static void vsc9953_port_config_show(int port)
{
int speed;
int duplex;
int link;
u8 enabled;
u32 val;
struct vsc9953_qsys_reg *l2qsys_reg;
l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET +
VSC9953_QSYS_OFFSET);
val = in_le32(&l2qsys_reg->sys.switch_port_mode[port]);
enabled = vsc9953_l2sw.port[port].enabled &
((val & 0x00002000) >> 13);
/* internal ports (8 and 9) are fixed */
if (VSC9953_INTERNAL_PORT_CHECK(port)) {
link = 1;
speed = SPEED_2500;
duplex = DUPLEX_FULL;
} else {
if (vsc9953_l2sw.port[port].phydev) {
link = vsc9953_l2sw.port[port].phydev->link;
speed = vsc9953_l2sw.port[port].phydev->speed;
duplex = vsc9953_l2sw.port[port].phydev->duplex;
} else {
link = -1;
speed = -1;
duplex = -1;
}
}
printf("%8d ", port);
printf("%8s ", enabled == 1 ? "enabled" : "disabled");
printf("%8s ", link == 1 ? "up" : "down");
switch (speed) {
case SPEED_10:
printf("%8d ", 10);
break;
case SPEED_100:
printf("%8d ", 100);
break;
case SPEED_1000:
printf("%8d ", 1000);
break;
case SPEED_2500:
printf("%8d ", 2500);
break;
case SPEED_10000:
printf("%8d ", 10000);
break;
default:
printf("%8s ", "-");
}
printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half");
}
/* Print VSC9953 ports' configuration */
static void vsc9953_port_all_config_show(void)
{
int i;
for (i = 0; i < VSC9953_MAX_PORTS; i++)
vsc9953_port_config_show(i);
}
/* function to interpret commands starting with "ethsw " */
static int do_ethsw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u8 enable;
u32 port;
if (argc < 4)
return -1;
if (strcmp(argv[1], "port"))
return -1;
if (!strcmp(argv[3], "show")) {
if (!strcmp(argv[2], "all")) {
vsc9953_phy_all_autoneg();
printf("%8s %8s %8s %8s %8s\n",
"Port", "Status", "Link", "Speed",
"Duplex");
vsc9953_port_all_config_show();
return 0;
} else {
port = simple_strtoul(argv[2], NULL, 10);
if (!VSC9953_PORT_CHECK(port))
return -1;
vsc9953_phy_autoneg(port);
printf("%8s %8s %8s %8s %8s\n",
"Port", "Status", "Link", "Speed",
"Duplex");
vsc9953_port_config_show(port);
return 0;
}
} else if (!strcmp(argv[3], "enable")) {
enable = 1;
} else if (!strcmp(argv[3], "disable")) {
enable = 0;
} else {
return -1;
}
if (!strcmp(argv[2], "all")) {
vsc9953_port_all_status_set(enable);
return 0;
} else {
port = simple_strtoul(argv[2], NULL, 10);
if (!VSC9953_PORT_CHECK(port))
return -1;
vsc9953_port_status_set(port, enable);
return 0;
}
return -1;
}
U_BOOT_CMD(ethsw, 5, 0, do_ethsw,
"vsc9953 l2 switch commands",
"port <port_nr> enable|disable\n"
" - enable/disable an l2 switch port\n"
" port_nr=0..9; use \"all\" for all ports\n"
"ethsw port <port_nr> show\n"
" - show an l2 switch port's configuration\n"
" port_nr=0..9; use \"all\" for all ports\n"
);
#endif /* CONFIG_VSC9953_CMD */

View file

@ -433,6 +433,7 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \ "netdev=eth0\0" \

View file

@ -675,6 +675,7 @@ combinations. this should be removed later
#define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
#ifdef CONFIG_SDCARD #ifdef CONFIG_SDCARD
#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"

View file

@ -581,4 +581,6 @@
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
#include <asm/fsl_secure_boot.h>
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */

View file

@ -35,7 +35,10 @@
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
#define CONFIG_DEEP_SLEEP #define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE #define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#endif
#ifdef CONFIG_RAMBOOT_PBL #ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg

View file

@ -36,7 +36,10 @@
/* support deep sleep */ /* support deep sleep */
#define CONFIG_DEEP_SLEEP #define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE #define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#endif
#ifdef CONFIG_RAMBOOT_PBL #ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
@ -51,7 +54,7 @@
#define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x00201000 #define CONFIG_SYS_TEXT_BASE 0x30001000
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
#define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_PAD_TO 0x40000
#define CONFIG_SPL_MAX_SIZE 0x28000 #define CONFIG_SPL_MAX_SIZE 0x28000
@ -67,21 +70,21 @@
#ifdef CONFIG_NAND #ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#define CONFIG_SPL_NAND_BOOT #define CONFIG_SPL_NAND_BOOT
#endif #endif
#ifdef CONFIG_SPIFLASH #ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD
@ -91,12 +94,12 @@
#endif #endif
#ifdef CONFIG_SDCARD #ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD
@ -759,8 +762,10 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FMAN_ENET #define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB_10G #define CONFIG_PHYLIB_10G
#define CONFIG_PHY_REALTEK #define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
#define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY1_ADDR 0x2
#define RGMII_PHY2_ADDR 0x6 #define RGMII_PHY2_ADDR 0x6
#define SGMII_PHY1_ADDR 0x2
#define FM1_10GEC1_PHY_ADDR 0x1 #define FM1_10GEC1_PHY_ADDR 0x1
#endif #endif

View file

@ -47,7 +47,10 @@
/* support deep sleep */ /* support deep sleep */
#define CONFIG_DEEP_SLEEP #define CONFIG_DEEP_SLEEP
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE #define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#endif
#ifndef CONFIG_SYS_TEXT_BASE #ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000 #define CONFIG_SYS_TEXT_BASE 0xeff40000
@ -689,6 +692,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif #endif
/* Enable VSC9953 L2 Switch driver */
#define CONFIG_VSC9953
#define CONFIG_VSC9953_CMD
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
/* /*
* Dynamic MTD Partition support with mtdparts * Dynamic MTD Partition support with mtdparts
*/ */

View file

@ -726,6 +726,14 @@
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
#ifdef CONFIG_T1040RDB
#define CONFIG_VSC9953
#define CONFIG_VSC9953_CMD
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
#endif
#define CONFIG_MII /* MII PHY management */ #define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC4" #define CONFIG_ETHPRIME "FM1@DTSEC4"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */

View file

@ -225,6 +225,7 @@ int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev); int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev); int gen10g_discover_mmds(struct phy_device *phydev);
int phy_aquantia_init(void);
int phy_atheros_init(void); int phy_atheros_init(void);
int phy_broadcom_init(void); int phy_broadcom_init(void);
int phy_cortina_init(void); int phy_cortina_init(void);

402
include/vsc9953.h Normal file
View file

@ -0,0 +1,402 @@
/*
* vsc9953.h
*
* Driver for the Vitesse VSC9953 L2 Switch
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* Copyright 2013 Freescale Semiconductor, Inc.
*
*/
#ifndef _VSC9953_H_
#define _VSC9953_H_
#include <config.h>
#include <miiphy.h>
#include <asm/types.h>
#include <malloc.h>
#define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
#define VSC9953_SYS_OFFSET 0x010000
#define VSC9953_DEV_GMII_OFFSET 0x100000
#define VSC9953_QSYS_OFFSET 0x200000
#define VSC9953_ANA_OFFSET 0x280000
#define VSC9953_DEVCPU_GCB 0x070000
#define VSC9953_ES0 0x040000
#define VSC9953_IS1 0x050000
#define VSC9953_IS2 0x060000
#define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
#define VSC9953_PHY_REGS_OFFST 0x0000AC
#define CONFIG_VSC9953_SOFT_SWC_RST_ENA 0x00000001
#define CONFIG_VSC9953_CORE_ENABLE 0x80
#define CONFIG_VSC9953_MEM_ENABLE 0x40
#define CONFIG_VSC9953_MEM_INIT 0x20
#define CONFIG_VSC9953_PORT_ENA 0x00003a00
#define CONFIG_VSC9953_MAC_ENA_CFG 0x00000011
#define CONFIG_VSC9953_MAC_MODE_CFG 0x00000011
#define CONFIG_VSC9953_MAC_IFG_CFG 0x00000515
#define CONFIG_VSC9953_MAC_HDX_CFG 0x00001043
#define CONFIG_VSC9953_CLOCK_CFG 0x00000001
#define CONFIG_VSC9953_CLOCK_CFG_1000M 0x00000001
#define CONFIG_VSC9953_PFC_FC 0x00000001
#define CONFIG_VSC9953_PFC_FC_QSGMII 0x00000000
#define CONFIG_VSC9953_MAC_FC_CFG 0x04700000
#define CONFIG_VSC9953_MAC_FC_CFG_QSGMII 0x00700000
#define CONFIG_VSC9953_PAUSE_CFG 0x001ffffe
#define CONFIG_VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
#define CONFIG_VSC9953_FRONT_PORT_MODE 0x00000000
#define CONFIG_VSC9953_MAC_MAX_LEN 0x000005ee
#define CONFIG_VSC9953_VCAP_MV_CFG 0x0000ffff
#define CONFIG_VSC9953_VCAP_UPDATE_CTRL 0x01000004
#define VSC9953_MAX_PORTS 10
#define VSC9953_PORT_CHECK(port) \
(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
( \
(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
) ? 0 : 1 \
)
#define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
#define MIIMIND_OPR_PEND 0x00000004
struct vsc9953_mdio_info {
struct vsc9953_mii_mng *regs;
char *name;
};
/* VSC9953 ANA structure for T1040 U-boot*/
struct vsc9953_ana_port {
u32 vlan_cfg;
u32 drop_cfg;
u32 qos_cfg;
u32 vcap_cfg;
u32 vcap_s1_key_cfg[3];
u32 vcap_s2_cfg;
u32 qos_pcp_dei_map_cfg[16];
u32 cpu_fwd_cfg;
u32 cpu_fwd_bpdu_cfg;
u32 cpu_fwd_garp_cfg;
u32 cpu_fwd_ccm_cfg;
u32 port_cfg;
u32 pol_cfg;
u32 reserved[34];
};
struct vsc9953_ana_pol {
u32 pol_pir_cfg;
u32 pol_cir_cfg;
u32 pol_mode_cfg;
u32 pol_pir_state;
u32 pol_cir_state;
u32 reserved1[3];
};
struct vsc9953_ana_ana_tables {
u32 entry_lim[11];
u32 an_moved;
u32 mach_data;
u32 macl_data;
u32 mac_access;
u32 mact_indx;
u32 vlan_access;
u32 vlan_tidx;
};
struct vsc9953_ana_ana {
u32 adv_learn;
u32 vlan_mask;
u32 anag_efil;
u32 an_events;
u32 storm_limit_burst;
u32 storm_limit_cfg[4];
u32 isolated_prts;
u32 community_ports;
u32 auto_age;
u32 mac_options;
u32 learn_disc;
u32 agen_ctrl;
u32 mirror_ports;
u32 emirror_ports;
u32 flooding;
u32 flooding_ipmc;
u32 sflow_cfg[11];
u32 port_mode[12];
};
struct vsc9953_ana_pgid {
u32 port_grp_id[91];
};
struct vsc9953_ana_pfc {
u32 pfc_cfg;
u32 reserved1[15];
};
struct vsc9953_ana_pol_misc {
u32 pol_flowc[10];
u32 reserved1[17];
u32 pol_hyst;
};
struct vsc9953_ana_common {
u32 aggr_cfg;
u32 cpuq_cfg;
u32 cpuq_8021_cfg;
u32 dscp_cfg;
u32 dscp_rewr_cfg;
u32 vcap_rng_type_cfg;
u32 vcap_rng_val_cfg;
u32 discard_cfg;
u32 fid_cfg;
};
struct vsc9953_analyzer {
struct vsc9953_ana_port port[11];
u32 reserved1[9536];
struct vsc9953_ana_pol pol[164];
struct vsc9953_ana_ana_tables ana_tables;
u32 reserved2[14];
struct vsc9953_ana_ana ana;
u32 reserved3[22];
struct vsc9953_ana_pgid port_id_tbl;
u32 reserved4[549];
struct vsc9953_ana_pfc pfc[10];
struct vsc9953_ana_pol_misc pol_misc;
u32 reserved5[196];
struct vsc9953_ana_common common;
};
/* END VSC9953 ANA structure for T1040 U-boot*/
/* VSC9953 DEV_GMII structure for T1040 U-boot*/
struct vsc9953_dev_gmii_port_mode {
u32 clock_cfg;
u32 port_misc;
u32 reserved1;
u32 eee_cfg;
};
struct vsc9953_dev_gmii_mac_cfg_status {
u32 mac_ena_cfg;
u32 mac_mode_cfg;
u32 mac_maxlen_cfg;
u32 mac_tags_cfg;
u32 mac_adv_chk_cfg;
u32 mac_ifg_cfg;
u32 mac_hdx_cfg;
u32 mac_fc_mac_low_cfg;
u32 mac_fc_mac_high_cfg;
u32 mac_sticky;
};
struct vsc9953_dev_gmii {
struct vsc9953_dev_gmii_port_mode port_mode;
struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
};
/* END VSC9953 DEV_GMII structure for T1040 U-boot*/
/* VSC9953 QSYS structure for T1040 U-boot*/
struct vsc9953_qsys_hsch {
u32 cir_cfg;
u32 reserved1;
u32 se_cfg;
u32 se_dwrr_cfg[8];
u32 cir_state;
u32 reserved2[20];
};
struct vsc9953_qsys_sys {
u32 port_mode[12];
u32 switch_port_mode[11];
u32 stat_cnt_cfg;
u32 eee_cfg[10];
u32 eee_thrs;
u32 igr_no_sharing;
u32 egr_no_sharing;
u32 sw_status[11];
u32 ext_cpu_cfg;
u32 cpu_group_map;
u32 reserved1[23];
};
struct vsc9953_qsys_qos_cfg {
u32 red_profile[16];
u32 res_qos_mode;
};
struct vsc9953_qsys_drop_cfg {
u32 egr_drop_mode;
};
struct vsc9953_qsys_mmgt {
u32 eq_cntrl;
u32 reserved1;
};
struct vsc9953_qsys_hsch_misc {
u32 hsch_misc_cfg;
u32 reserved1[546];
};
struct vsc9953_qsys_res_ctrl {
u32 res_cfg;
u32 res_stat;
};
struct vsc9953_qsys_reg {
struct vsc9953_qsys_hsch hsch[108];
struct vsc9953_qsys_sys sys;
struct vsc9953_qsys_qos_cfg qos_cfg;
struct vsc9953_qsys_drop_cfg drop_cfg;
struct vsc9953_qsys_mmgt mmgt;
struct vsc9953_qsys_hsch_misc hsch_misc;
struct vsc9953_qsys_res_ctrl res_ctrl[1024];
};
/* END VSC9953 QSYS structure for T1040 U-boot*/
/* VSC9953 SYS structure for T1040 U-boot*/
struct vsc9953_sys_stat {
u32 rx_cntrs[64];
u32 tx_cntrs[64];
u32 drop_cntrs[64];
u32 reserved1[6];
};
struct vsc9953_sys_sys {
u32 reset_cfg;
u32 reserved1;
u32 vlan_etype_cfg;
u32 port_mode[12];
u32 front_port_mode[10];
u32 frame_aging;
u32 stat_cfg;
u32 reserved2[50];
};
struct vsc9953_sys_pause_cfg {
u32 pause_cfg[11];
u32 pause_tot_cfg;
u32 tail_drop_level[11];
u32 tot_tail_drop_lvl;
u32 mac_fc_cfg[10];
};
struct vsc9953_sys_mmgt {
u16 free_cnt;
};
struct vsc9953_system_reg {
struct vsc9953_sys_stat stat;
struct vsc9953_sys_sys sys;
struct vsc9953_sys_pause_cfg pause_cfg;
struct vsc9953_sys_mmgt mmgt;
};
/* END VSC9953 SYS structure for T1040 U-boot*/
/* VSC9953 DEVCPU_GCB structure for T1040 U-boot*/
struct vsc9953_chip_regs {
u32 chipd_id;
u32 gpr;
u32 soft_rst;
};
struct vsc9953_gpio {
u32 gpio_out_set[10];
u32 gpio_out_clr[10];
u32 gpio_out[10];
u32 gpio_in[10];
};
struct vsc9953_mii_mng {
u32 miimstatus;
u32 reserved1;
u32 miimcmd;
u32 miimdata;
u32 miimcfg;
u32 miimscan_0;
u32 miimscan_1;
u32 miiscan_lst_rslts;
u32 miiscan_lst_rslts_valid;
};
struct vsc9953_mii_read_scan {
u32 mii_scan_results_sticky[2];
};
struct vsc9953_devcpu_gcb {
struct vsc9953_chip_regs chip_regs;
struct vsc9953_gpio gpio;
struct vsc9953_mii_mng mii_mng[2];
struct vsc9953_mii_read_scan mii_read_scan;
};
/* END VSC9953 DEVCPU_GCB structure for T1040 U-boot*/
/* VSC9953 IS* structure for T1040 U-boot*/
struct vsc9953_vcap_core_cfg {
u32 vcap_update_ctrl;
u32 vcap_mv_cfg;
};
struct vsc9953_vcap {
struct vsc9953_vcap_core_cfg vcap_core_cfg;
};
/* END VSC9953 IS* structure for T1040 U-boot*/
#define VSC9953_PORT_INFO_INITIALIZER(idx) \
{ \
.enabled = 0, \
.phyaddr = 0, \
.index = idx, \
.phy_regs = NULL, \
.enet_if = PHY_INTERFACE_MODE_NONE, \
.bus = NULL, \
.phydev = NULL, \
}
/* Structure to describe a VSC9953 port */
struct vsc9953_port_info {
u8 enabled;
u8 phyaddr;
int index;
void *phy_regs;
phy_interface_t enet_if;
struct mii_dev *bus;
struct phy_device *phydev;
};
/* Structure to describe a VSC9953 switch */
struct vsc9953_info {
struct vsc9953_port_info port[VSC9953_MAX_PORTS];
};
void vsc9953_init(bd_t *bis);
void vsc9953_port_info_set_mdio(int port, struct mii_dev *bus);
void vsc9953_port_info_set_phy_address(int port, int address);
void vsc9953_port_enable(int port);
void vsc9953_port_disable(int port);
void vsc9953_port_info_set_phy_int(int port, phy_interface_t phy_int);
#endif /* _VSC9953_H_ */