mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-19 13:41:31 +00:00
fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by: Dave Liu <daveliu@freescale.com>
This commit is contained in:
parent
ab467c512e
commit
ec145e87b8
1 changed files with 17 additions and 9 deletions
|
@ -1,9 +1,10 @@
|
||||||
/*
|
/*
|
||||||
* Copyright 2008-2009 Freescale Semiconductor, Inc.
|
* Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||||
*
|
*
|
||||||
* This program is free software; you can redistribute it and/or
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
* modify it under the terms of the GNU General Public License
|
* under the terms of the GNU General Public License as published by the Free
|
||||||
* Version 2 as published by the Free Software Foundation.
|
* Software Foundation; either version 2 of the License, or (at your option)
|
||||||
|
* any later version.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -934,7 +935,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
|
/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
|
||||||
static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
|
static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
|
||||||
|
const memctl_options_t *popts)
|
||||||
{
|
{
|
||||||
unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
|
unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
|
||||||
unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
|
unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
|
||||||
|
@ -943,9 +945,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
|
||||||
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
|
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
|
||||||
|
|
||||||
#if defined(CONFIG_FSL_DDR3)
|
#if defined(CONFIG_FSL_DDR3)
|
||||||
/* We need set BL/2 + 4 for BC4 or OTF */
|
if (popts->burst_length == DDR_BL8) {
|
||||||
rrt = 4; /* BL/2 + 4 clocks */
|
/* We set BL/2 for fixed BL8 */
|
||||||
wwt = 4; /* BL/2 + 4 clocks */
|
rrt = 0; /* BL/2 clocks */
|
||||||
|
wwt = 0; /* BL/2 clocks */
|
||||||
|
} else {
|
||||||
|
/* We need to set BL/2 + 2 to BC4 and OTF */
|
||||||
|
rrt = 2; /* BL/2 + 2 clocks */
|
||||||
|
wwt = 2; /* BL/2 + 2 clocks */
|
||||||
|
}
|
||||||
dll_lock = 1; /* tDLLK = 512 clocks from spec */
|
dll_lock = 1; /* tDLLK = 512 clocks from spec */
|
||||||
#endif
|
#endif
|
||||||
ddr->timing_cfg_4 = (0
|
ddr->timing_cfg_4 = (0
|
||||||
|
@ -1343,7 +1351,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
|
||||||
set_ddr_sdram_clk_cntl(ddr, popts);
|
set_ddr_sdram_clk_cntl(ddr, popts);
|
||||||
set_ddr_init_addr(ddr);
|
set_ddr_init_addr(ddr);
|
||||||
set_ddr_init_ext_addr(ddr);
|
set_ddr_init_ext_addr(ddr);
|
||||||
set_timing_cfg_4(ddr);
|
set_timing_cfg_4(ddr, popts);
|
||||||
set_timing_cfg_5(ddr);
|
set_timing_cfg_5(ddr);
|
||||||
|
|
||||||
set_ddr_zq_cntl(ddr, zq_en);
|
set_ddr_zq_cntl(ddr, zq_en);
|
||||||
|
|
Loading…
Add table
Reference in a new issue