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fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by: Dave Liu <daveliu@freescale.com>
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1 changed files with 17 additions and 9 deletions
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@ -1,9 +1,10 @@
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/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc.
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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/*
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@ -934,7 +935,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
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}
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/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
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static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
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static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
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const memctl_options_t *popts)
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{
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unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
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unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
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@ -943,9 +945,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
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unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
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#if defined(CONFIG_FSL_DDR3)
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/* We need set BL/2 + 4 for BC4 or OTF */
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rrt = 4; /* BL/2 + 4 clocks */
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wwt = 4; /* BL/2 + 4 clocks */
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if (popts->burst_length == DDR_BL8) {
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/* We set BL/2 for fixed BL8 */
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rrt = 0; /* BL/2 clocks */
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wwt = 0; /* BL/2 clocks */
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} else {
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/* We need to set BL/2 + 2 to BC4 and OTF */
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rrt = 2; /* BL/2 + 2 clocks */
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wwt = 2; /* BL/2 + 2 clocks */
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}
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dll_lock = 1; /* tDLLK = 512 clocks from spec */
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#endif
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ddr->timing_cfg_4 = (0
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@ -1343,7 +1351,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
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set_ddr_sdram_clk_cntl(ddr, popts);
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set_ddr_init_addr(ddr);
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set_ddr_init_ext_addr(ddr);
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set_timing_cfg_4(ddr);
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set_timing_cfg_4(ddr, popts);
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set_timing_cfg_5(ddr);
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set_ddr_zq_cntl(ddr, zq_en);
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