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https://github.com/Fishwaldo/u-boot.git
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x86: Add a CPU driver for baytrail
This driver supports multi-core init and sets up the CPU frequencies correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
parent
bcb0c61e1a
commit
ede9709316
5 changed files with 227 additions and 6 deletions
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@ -4,6 +4,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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obj-y += early_uart.o
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obj-y += fsp_configs.o
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obj-y += pci.o
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205
arch/x86/cpu/baytrail/cpu.c
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205
arch/x86/cpu/baytrail/cpu.c
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@ -0,0 +1,205 @@
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/*
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* Copyright (C) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Based on code from coreboot
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <asm/cpu.h>
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#include <asm/lapic.h>
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#include <asm/mp.h>
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#include <asm/msr.h>
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#include <asm/turbo.h>
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#ifdef CONFIG_SMP
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static int enable_smis(struct udevice *cpu, void *unused)
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{
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return 0;
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}
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static struct mp_flight_record mp_steps[] = {
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MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
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/* Wait for APs to finish initialization before proceeding. */
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MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
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};
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static int detect_num_cpus(void)
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{
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int ecx = 0;
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/*
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* Use the algorithm described in Intel 64 and IA-32 Architectures
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* Software Developer's Manual Volume 3 (3A, 3B & 3C): System
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* Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
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* of CPUID Extended Topology Leaf.
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*/
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while (1) {
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struct cpuid_result leaf_b;
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leaf_b = cpuid_ext(0xb, ecx);
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/*
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* Bay Trail doesn't have hyperthreading so just determine the
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* number of cores by from level type (ecx[15:8] == * 2)
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*/
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if ((leaf_b.ecx & 0xff00) == 0x0200)
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return leaf_b.ebx & 0xffff;
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ecx++;
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}
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}
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static int baytrail_init_cpus(void)
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{
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struct mp_params mp_params;
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lapic_setup();
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mp_params.num_cpus = detect_num_cpus();
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mp_params.parallel_microcode_load = 0,
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mp_params.flight_plan = &mp_steps[0];
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mp_params.num_records = ARRAY_SIZE(mp_steps);
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mp_params.microcode_pointer = 0;
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if (mp_init(&mp_params)) {
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printf("Warning: MP init failure\n");
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return -EIO;
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}
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return 0;
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}
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#endif
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int x86_init_cpus(void)
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{
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#ifdef CONFIG_SMP
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debug("Init additional CPUs\n");
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baytrail_init_cpus();
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#endif
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return 0;
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}
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static void set_max_freq(void)
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{
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msr_t perf_ctl;
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msr_t msr;
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/* Enable speed step */
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msr = msr_read(MSR_IA32_MISC_ENABLES);
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msr.lo |= (1 << 16);
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msr_write(MSR_IA32_MISC_ENABLES, msr);
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/*
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* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
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* the PERF_CTL
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*/
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msr = msr_read(MSR_IACORE_RATIOS);
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perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
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/*
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* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
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* the PERF_CTL
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*/
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msr = msr_read(MSR_IACORE_VIDS);
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perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
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perf_ctl.hi = 0;
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msr_write(MSR_IA32_PERF_CTL, perf_ctl);
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}
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static int cpu_x86_baytrail_probe(struct udevice *dev)
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{
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debug("Init BayTrail core\n");
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/*
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* On BayTrail the turbo disable bit is actually scoped at the
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* building-block level, not package. For non-BSP cores that are
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* within a building block, enable turbo. The cores within the BSP's
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* building block will just see it already enabled and move on.
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*/
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if (lapicid())
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turbo_enable();
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/* Dynamic L2 shrink enable and threshold */
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msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f000f, 0xe0008),
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/* Disable C1E */
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msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
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msr_setbits_64(MSR_POWER_MISC, 0x44);
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/* Set this core to max frequency ratio */
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set_max_freq();
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return 0;
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}
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static unsigned bus_freq(void)
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{
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msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
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switch (clk_info.lo & 0x3) {
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case 0:
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return 83333333;
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case 1:
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return 100000000;
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case 2:
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return 133333333;
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case 3:
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return 116666666;
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default:
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return 0;
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}
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}
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static unsigned long tsc_freq(void)
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{
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msr_t platform_info;
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ulong bclk = bus_freq();
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if (!bclk)
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return 0;
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platform_info = msr_read(MSR_PLATFORM_INFO);
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return bclk * ((platform_info.lo >> 8) & 0xff);
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}
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static int baytrail_get_info(struct udevice *dev, struct cpu_info *info)
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{
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info->cpu_freq = tsc_freq();
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info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
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return 0;
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}
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static int cpu_x86_baytrail_bind(struct udevice *dev)
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{
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struct cpu_platdata *plat = dev_get_parent_platdata(dev);
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plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"intel,apic-id", -1);
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return 0;
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}
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static const struct cpu_ops cpu_x86_baytrail_ops = {
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.get_desc = x86_cpu_get_desc,
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.get_info = baytrail_get_info,
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};
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static const struct udevice_id cpu_x86_baytrail_ids[] = {
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{ .compatible = "intel,baytrail-cpu" },
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{ }
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};
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U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {
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.name = "cpu_x86_baytrail",
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.id = UCLASS_CPU,
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.of_match = cpu_x86_baytrail_ids,
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.bind = cpu_x86_baytrail_bind,
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.probe = cpu_x86_baytrail_probe,
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.ops = &cpu_x86_baytrail_ops,
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};
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@ -37,7 +37,6 @@
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#define MSR_MISC_PWR_MGMT 0x1aa
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#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
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#define MSR_TURBO_RATIO_LIMIT 0x1ad
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#define MSR_POWER_CTL 0x1fc
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#define MSR_PKGC3_IRTL 0x60a
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#define MSR_PKGC6_IRTL 0x60b
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@ -63,7 +62,6 @@
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#define MSR_PP1_CURRENT_CONFIG 0x602
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#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
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#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
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#define MSR_PKG_POWER_SKU_UNIT 0x606
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#define MSR_PKG_POWER_SKU 0x614
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#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
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#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
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#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
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#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd
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#define MSR_PLATFORM_INFO 0x000000ce
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#define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2
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#define SINGLE_PCTL (1 << 11)
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#define MSR_MTRRcap 0x000000fe
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#define MSR_IA32_BBL_CR_CTL 0x00000119
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#define MSR_IA32_BBL_CR_CTL3 0x0000011e
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#define MSR_POWER_MISC 0x00000120
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#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
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#define ENABLE_INDP_AUTOCM_MASK (1 << 3)
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#define MSR_IA32_SYSENTER_CS 0x00000174
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#define MSR_IA32_SYSENTER_ESP 0x00000175
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#define MSR_IA32_MCG_STATUS 0x0000017a
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#define MSR_IA32_MCG_CTL 0x0000017b
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#define MSR_IA32_MISC_ENABLES 0x000001a0
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#define MSR_OFFCORE_RSP_0 0x000001a6
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#define MSR_OFFCORE_RSP_1 0x000001a7
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#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
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@ -73,6 +81,7 @@
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#define MSR_LBR_SELECT 0x000001c8
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#define MSR_LBR_TOS 0x000001c9
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#define MSR_POWER_CTL 0x000001fc
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#define MSR_LBR_NHM_FROM 0x00000680
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#define MSR_LBR_NHM_TO 0x000006c0
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#define MSR_LBR_CORE_FROM 0x00000040
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@ -136,7 +145,7 @@
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/* Run Time Average Power Limiting (RAPL) Interface */
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#define MSR_RAPL_POWER_UNIT 0x00000606
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#define MSR_PKG_POWER_SKU_UNIT 0x00000606
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#define MSR_PKG_POWER_LIMIT 0x00000610
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#define MSR_PKG_ENERGY_STATUS 0x00000611
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@ -158,6 +167,16 @@
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#define MSR_PP1_POLICY 0x00000642
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#define MSR_CORE_C1_RES 0x00000660
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#define MSR_IACORE_RATIOS 0x0000066a
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#define MSR_IACORE_TURBO_RATIOS 0x0000066c
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#define MSR_IACORE_VIDS 0x0000066b
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#define MSR_IACORE_TURBO_VIDS 0x0000066d
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#define MSR_PKG_TURBO_CFG1 0x00000670
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#define MSR_CPU_TURBO_WKLD_CFG1 0x00000671
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#define MSR_CPU_TURBO_WKLD_CFG2 0x00000672
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#define MSR_CPU_THERM_CFG1 0x00000673
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#define MSR_CPU_THERM_CFG2 0x00000674
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#define MSR_CPU_THERM_SENS_CFG 0x00000675
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#define MSR_AMD64_MC0_MASK 0xc0010044
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@ -348,6 +367,7 @@
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#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
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#define MSR_IA32_MISC_ENABLE 0x000001a0
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#define H_MISC_DISABLE_TURBO (1 << 6)
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#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
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#define CPUID_LEAF_PM 6
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#define PM_CAP_TURBO_MODE (1 << 1)
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#define MSR_IA32_MISC_ENABLES 0x1a0
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#define H_MISC_DISABLE_TURBO (1 << 6)
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enum {
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TURBO_UNKNOWN,
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TURBO_UNAVAILABLE,
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