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net: zynq: Add clk framework support to zynq ethernet driver

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If available use the clock framework to set the tx clock rate of the
zynq ethernet controller.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Stefan Herbrechtsmeier 2017-01-17 16:27:25 +01:00 • committed by Michal Simek
parent a259243e9d
commit eff55c55c7
2 changed files with 15 additions and 14 deletions
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7
arch/arm/include/asm/arch-zynqmp/sys_proto.h
View file

@ -8,13 +8,6 @@
#ifndef _ASM_ARCH_SYS_PROTO_H #ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H
#ifndef CONFIG_CLK_ZYNQMP
/* Setup clk for network */
static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
}
#endif
int zynq_slcr_get_mio_pin_status(const char *periph); int zynq_slcr_get_mio_pin_status(const char *periph);
unsigned int zynqmp_get_silicon_version(void); unsigned int zynqmp_get_silicon_version(void);

22
drivers/net/zynq_gem.c
View file

@ -181,7 +181,7 @@ struct zynq_gem_priv {
struct phy_device *phydev; struct phy_device *phydev;
int phy_of_handle; int phy_of_handle;
struct mii_dev *bus; struct mii_dev *bus;
#ifdef CONFIG_CLK_ZYNQMP #if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
struct clk clk; struct clk clk;
#endif #endif
}; };
@ -456,13 +456,21 @@ static int zynq_gem_init(struct udevice *dev)
break; break;
} }
#ifndef CONFIG_CLK_ZYNQMP #if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
dev_err(dev, "failed to set tx clock rate\n");
return ret;
}
ret = clk_enable(&priv->clk);
if (ret && ret != -ENOSYS) {
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
#else
zynq_slcr_gem_clk_setup((ulong)priv->iobase != zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
ZYNQ_GEM_BASEADDR0, clk_rate); ZYNQ_GEM_BASEADDR0, clk_rate);
#else
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret))
return -1;
#endif #endif
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
@ -636,7 +644,7 @@ static int zynq_gem_probe(struct udevice *dev)
priv->tx_bd = (struct emac_bd *)bd_space; priv->tx_bd = (struct emac_bd *)bd_space;
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
#ifdef CONFIG_CLK_ZYNQMP #if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
ret = clk_get_by_name(dev, "tx_clk", &priv->clk); ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
if (ret < 0) { if (ret < 0) {
dev_err(dev, "failed to get clock\n"); dev_err(dev, "failed to get clock\n");