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net: sh_eth: Unify CONFIG_R8A779[01234] as CONFIG_RCAR_GEN2

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Use the common RCAR_GEN2 config option instead of enumerating
each SoC and having a lengthy ifdef clause. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Marek Vasut 2018-01-22 01:42:32 +01:00 • committed by Marek Vasut
parent e3105eacf5
commit effb79027e
2 changed files with 4 additions and 9 deletions
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7
drivers/net/sh_eth.c
View file

@ -421,8 +421,7 @@ static int sh_eth_config(struct sh_eth_dev *eth)
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ #elif defined(CONFIG_RCAR_GEN2)
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR); sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
#endif #endif
/* Configure phy */ /* Configure phy */
@ -447,9 +446,7 @@ static int sh_eth_config(struct sh_eth_dev *eth)
sh_eth_write(port_info, GECMR_100B, GECMR); sh_eth_write(port_info, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(port_info, 1, RTRATE); sh_eth_write(port_info, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
defined(CONFIG_R8A7794)
val = ECMR_RTM; val = ECMR_RTM;
#endif #endif
} else if (phy->speed == 10) { } else if (phy->speed == 10) {

6
drivers/net/sh_eth.h
View file

@ -302,8 +302,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
#elif defined(CONFIG_R8A7740) #elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER #define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000 #define BASE_IO_ADDR 0xE9A00000
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ #elif defined(CONFIG_RCAR_GEN2)
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define SH_ETH_TYPE_ETHER #define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200 #define BASE_IO_ADDR 0xEE700200
#elif defined(CONFIG_R7S72100) #elif defined(CONFIG_R7S72100)
@ -514,8 +513,7 @@ enum FELIC_MODE_BIT {
ECMR_PRM = 0x00000001, ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724 #ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010, ECMR_RTM = 0x00000010,
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ #elif defined(CONFIG_RCAR_GEN2)
defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
ECMR_RTM = 0x00000004, ECMR_RTM = 0x00000004,
#endif #endif