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riscv: dts: Support four cores SMP
Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
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parent
444c46413f
commit
f05b6569a9
2 changed files with 108 additions and 6 deletions
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@ -62,6 +62,48 @@
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compatible = "riscv,cpu-intc";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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reg = <2>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv32imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <32>;
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next-level-cache = <&L2>;
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CPU2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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reg = <3>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv32imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <32>;
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next-level-cache = <&L2>;
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CPU3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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L2: l2-cache@e0500000 {
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@ -94,7 +136,10 @@
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interrupt-controller;
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reg = <0xe4000000 0x2000000>;
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riscv,ndev=<71>;
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interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
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interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
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&CPU1_intc 11 &CPU1_intc 9
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&CPU2_intc 11 &CPU2_intc 9
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&CPU3_intc 11 &CPU3_intc 9>;
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};
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plic1: interrupt-controller@e6400000 {
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@ -104,12 +149,18 @@
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interrupt-controller;
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reg = <0xe6400000 0x400000>;
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riscv,ndev=<2>;
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interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
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interrupts-extended = <&CPU0_intc 3
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&CPU1_intc 3
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&CPU2_intc 3
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&CPU3_intc 3>;
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};
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plmt0@e6000000 {
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compatible = "riscv,plmt0";
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interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
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interrupts-extended = <&CPU0_intc 7
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&CPU1_intc 7
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&CPU2_intc 7
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&CPU3_intc 7>;
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reg = <0xe6000000 0x100000>;
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};
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};
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@ -62,6 +62,48 @@
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compatible = "riscv,cpu-intc";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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reg = <2>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv39";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <32>;
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next-level-cache = <&L2>;
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CPU2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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reg = <3>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv39";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <32>;
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next-level-cache = <&L2>;
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CPU3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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L2: l2-cache@e0500000 {
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@ -94,7 +136,10 @@
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interrupt-controller;
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reg = <0x0 0xe4000000 0x0 0x2000000>;
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riscv,ndev=<71>;
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interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9>;
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interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
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&CPU1_intc 11 &CPU1_intc 9
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&CPU2_intc 11 &CPU2_intc 9
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&CPU3_intc 11 &CPU3_intc 9>;
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};
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plic1: interrupt-controller@e6400000 {
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@ -104,12 +149,18 @@
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interrupt-controller;
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reg = <0x0 0xe6400000 0x0 0x400000>;
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riscv,ndev=<2>;
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interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3>;
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interrupts-extended = <&CPU0_intc 3
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&CPU1_intc 3
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&CPU2_intc 3
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&CPU3_intc 3>;
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};
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plmt0@e6000000 {
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compatible = "riscv,plmt0";
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interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7>;
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interrupts-extended = <&CPU0_intc 7
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&CPU1_intc 7
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&CPU2_intc 7
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&CPU3_intc 7>;
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reg = <0x0 0xe6000000 0x0 0x100000>;
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};
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};
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