mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
This commit is contained in:
commit
f15ea6e1d6
588 changed files with 10139 additions and 7990 deletions
2
CREDITS
2
CREDITS
|
@ -143,7 +143,7 @@ W: www.freescale.com
|
|||
|
||||
N: Dr. Wolfgang Grandegger
|
||||
E: wg@denx.de
|
||||
D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
|
||||
D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
|
||||
W: www.denx.de
|
||||
|
||||
N: Peter Figuli
|
||||
|
|
17
MAKEALL
17
MAKEALL
|
@ -18,6 +18,7 @@ usage()
|
|||
-c CPU, --cpu CPU Build all boards with cpu CPU
|
||||
-v VENDOR, --vendor VENDOR Build all boards with vendor VENDOR
|
||||
-s SOC, --soc SOC Build all boards with soc SOC
|
||||
-b BOARD, --board BOARD Build all boards with board name BOARD
|
||||
-l, --list List all targets to be built
|
||||
-m, --maintainers List all targets and maintainer email
|
||||
-M, --mails List all targets and all affilated emails
|
||||
|
@ -59,8 +60,8 @@ usage()
|
|||
exit ${ret}
|
||||
}
|
||||
|
||||
SHORT_OPTS="ha:c:v:s:lmMCnr"
|
||||
LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check,continue,rebuild-errors"
|
||||
SHORT_OPTS="ha:c:v:s:b:lmMCnr"
|
||||
LONG_OPTS="help,arch:,cpu:,vendor:,soc:,board:,list,maintainers,mails,check,continue,rebuild-errors"
|
||||
|
||||
# Option processing based on util-linux-2.13/getopt-parse.bash
|
||||
|
||||
|
@ -121,6 +122,17 @@ while true ; do
|
|||
fi
|
||||
SELECTED='y'
|
||||
shift 2 ;;
|
||||
-b|--board)
|
||||
# echo "Option BOARD: argument \`$2'"
|
||||
if [ "$opt_b" ] ; then
|
||||
opt_b="${opt_b%)} || \$6 == \"$2\" || \$7 == \"$2\")"
|
||||
else
|
||||
# We need to check the 7th field too
|
||||
# for boards whose 6th field is "-"
|
||||
opt_b="(\$6 == \"$2\" || \$7 == \"$2\")"
|
||||
fi
|
||||
SELECTED='y'
|
||||
shift 2 ;;
|
||||
-C|--check)
|
||||
CHECK='C=1'
|
||||
shift ;;
|
||||
|
@ -158,6 +170,7 @@ FILTER="\$1 !~ /^#/"
|
|||
[ "$opt_c" ] && FILTER="${FILTER} && $opt_c"
|
||||
[ "$opt_s" ] && FILTER="${FILTER} && $opt_s"
|
||||
[ "$opt_v" ] && FILTER="${FILTER} && $opt_v"
|
||||
[ "$opt_b" ] && FILTER="${FILTER} && $opt_b"
|
||||
|
||||
if [ "$SELECTED" ] ; then
|
||||
SELECTED=$(awk '('"$FILTER"') { print $7 }' boards.cfg)
|
||||
|
|
163
Makefile
163
Makefile
|
@ -5,10 +5,10 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
VERSION = 2013
|
||||
PATCHLEVEL = 10
|
||||
VERSION = 2014
|
||||
PATCHLEVEL = 01
|
||||
SUBLEVEL =
|
||||
EXTRAVERSION =
|
||||
EXTRAVERSION = -rc1
|
||||
ifneq "$(SUBLEVEL)" ""
|
||||
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
|
||||
else
|
||||
|
@ -65,11 +65,9 @@ endif
|
|||
# the object files are placed in the source directory.
|
||||
#
|
||||
|
||||
ifdef O
|
||||
ifeq ("$(origin O)", "command line")
|
||||
BUILD_DIR := $(O)
|
||||
endif
|
||||
endif
|
||||
|
||||
# Call a source code checker (by default, "sparse") as part of the
|
||||
# C compilation.
|
||||
|
@ -138,7 +136,6 @@ unexport CDPATH
|
|||
# The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC
|
||||
# is "yes"), so compile examples after U-Boot is compiled.
|
||||
SUBDIR_TOOLS = tools
|
||||
SUBDIR_EXAMPLES = examples/standalone examples/api
|
||||
SUBDIRS = $(SUBDIR_TOOLS)
|
||||
|
||||
.PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE)
|
||||
|
@ -152,8 +149,10 @@ all:
|
|||
sinclude $(obj)include/autoconf.mk.dep
|
||||
sinclude $(obj)include/autoconf.mk
|
||||
|
||||
SUBDIR_EXAMPLES-y := examples/standalone
|
||||
SUBDIR_EXAMPLES-$(CONFIG_API) += examples/api
|
||||
ifndef CONFIG_SANDBOX
|
||||
SUBDIRS += $(SUBDIR_EXAMPLES)
|
||||
SUBDIRS += $(SUBDIR_EXAMPLES-y)
|
||||
endif
|
||||
|
||||
# load ARCH, BOARD, and CPU configuration
|
||||
|
@ -231,87 +230,67 @@ OBJS := $(addprefix $(obj),$(OBJS))
|
|||
|
||||
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
|
||||
|
||||
LIBS-y += lib/libgeneric.o
|
||||
LIBS-y += lib/rsa/librsa.o
|
||||
LIBS-y += lib/lzma/liblzma.o
|
||||
LIBS-y += lib/lzo/liblzo.o
|
||||
LIBS-y += lib/zlib/libz.o
|
||||
LIBS-$(CONFIG_TIZEN) += lib/tizen/libtizen.o
|
||||
LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
|
||||
LIBS-y += $(CPUDIR)/lib$(CPU).o
|
||||
LIBS-y += lib/
|
||||
LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
|
||||
LIBS-y += $(CPUDIR)/
|
||||
ifdef SOC
|
||||
LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
|
||||
LIBS-y += $(CPUDIR)/$(SOC)/
|
||||
endif
|
||||
ifeq ($(CPU),ixp)
|
||||
LIBS-y += drivers/net/npe/libnpe.o
|
||||
endif
|
||||
LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
|
||||
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
|
||||
LIBS-y += fs/libfs.o \
|
||||
fs/fat/libfat.o
|
||||
LIBS-y += net/libnet.o
|
||||
LIBS-y += disk/libdisk.o
|
||||
LIBS-y += drivers/libdrivers.o
|
||||
LIBS-y += drivers/dma/libdma.o
|
||||
LIBS-y += drivers/gpio/libgpio.o
|
||||
LIBS-y += drivers/i2c/libi2c.o
|
||||
LIBS-y += drivers/input/libinput.o
|
||||
LIBS-y += drivers/mmc/libmmc.o
|
||||
LIBS-y += drivers/mtd/libmtd.o
|
||||
LIBS-y += drivers/mtd/nand/libnand.o
|
||||
LIBS-y += drivers/mtd/onenand/libonenand.o
|
||||
LIBS-y += drivers/mtd/ubi/libubi.o
|
||||
LIBS-y += drivers/mtd/spi/libspi_flash.o
|
||||
LIBS-y += drivers/net/libnet.o
|
||||
LIBS-y += drivers/net/phy/libphy.o
|
||||
LIBS-y += drivers/pci/libpci.o
|
||||
LIBS-y += drivers/power/libpower.o \
|
||||
drivers/power/fuel_gauge/libfuel_gauge.o \
|
||||
drivers/power/mfd/libmfd.o \
|
||||
drivers/power/pmic/libpmic.o \
|
||||
drivers/power/battery/libbattery.o
|
||||
LIBS-y += drivers/spi/libspi.o
|
||||
ifeq ($(CPU),mpc83xx)
|
||||
LIBS-y += drivers/qe/libqe.o
|
||||
LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
|
||||
LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
|
||||
endif
|
||||
ifeq ($(CPU),mpc85xx)
|
||||
LIBS-y += drivers/qe/libqe.o
|
||||
LIBS-y += drivers/net/fm/libfm.o
|
||||
LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
|
||||
LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
|
||||
endif
|
||||
ifeq ($(CPU),mpc86xx)
|
||||
LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
|
||||
LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
|
||||
endif
|
||||
LIBS-y += drivers/serial/libserial.o
|
||||
LIBS-y += drivers/usb/eth/libusb_eth.o
|
||||
LIBS-y += drivers/usb/gadget/libusb_gadget.o
|
||||
LIBS-y += drivers/usb/host/libusb_host.o
|
||||
LIBS-y += drivers/usb/musb/libusb_musb.o
|
||||
LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
|
||||
LIBS-y += drivers/usb/phy/libusb_phy.o
|
||||
LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
|
||||
LIBS-y += common/libcommon.o
|
||||
LIBS-y += lib/libfdt/libfdt.o
|
||||
LIBS-y += api/libapi.o
|
||||
LIBS-y += post/libpost.o
|
||||
LIBS-y += test/libtest.o
|
||||
LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/
|
||||
LIBS-$(CONFIG_OF_EMBED) += dts/
|
||||
LIBS-y += arch/$(ARCH)/lib/
|
||||
LIBS-y += fs/
|
||||
LIBS-y += net/
|
||||
LIBS-y += disk/
|
||||
LIBS-y += drivers/
|
||||
LIBS-y += drivers/dma/
|
||||
LIBS-y += drivers/gpio/
|
||||
LIBS-y += drivers/i2c/
|
||||
LIBS-y += drivers/input/
|
||||
LIBS-y += drivers/mmc/
|
||||
LIBS-y += drivers/mtd/
|
||||
LIBS-y += drivers/mtd/nand/
|
||||
LIBS-y += drivers/mtd/onenand/
|
||||
LIBS-y += drivers/mtd/ubi/
|
||||
LIBS-y += drivers/mtd/spi/
|
||||
LIBS-y += drivers/net/
|
||||
LIBS-y += drivers/net/phy/
|
||||
LIBS-y += drivers/pci/
|
||||
LIBS-y += drivers/power/ \
|
||||
drivers/power/fuel_gauge/ \
|
||||
drivers/power/mfd/ \
|
||||
drivers/power/pmic/ \
|
||||
drivers/power/battery/
|
||||
LIBS-y += drivers/spi/
|
||||
LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/
|
||||
LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
|
||||
LIBS-y += drivers/serial/
|
||||
LIBS-y += drivers/usb/eth/
|
||||
LIBS-y += drivers/usb/gadget/
|
||||
LIBS-y += drivers/usb/host/
|
||||
LIBS-y += drivers/usb/musb/
|
||||
LIBS-y += drivers/usb/musb-new/
|
||||
LIBS-y += drivers/usb/phy/
|
||||
LIBS-y += drivers/usb/ulpi/
|
||||
LIBS-y += common/
|
||||
LIBS-y += lib/libfdt/
|
||||
LIBS-$(CONFIG_API) += api/
|
||||
LIBS-y += post/
|
||||
LIBS-y += test/
|
||||
|
||||
ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
|
||||
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
|
||||
LIBS-y += arch/$(ARCH)/imx-common/
|
||||
endif
|
||||
|
||||
LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o
|
||||
LIBS-$(CONFIG_ARM) += arch/arm/cpu/
|
||||
LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/
|
||||
|
||||
LIBS-y += board/$(BOARDDIR)/
|
||||
|
||||
LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y))
|
||||
LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
|
||||
.PHONY : $(LIBS)
|
||||
|
||||
LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o
|
||||
LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
|
||||
|
||||
# Add GCC lib
|
||||
ifdef USE_PRIVATE_LIBGCC
|
||||
ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
|
||||
|
@ -335,7 +314,7 @@ LDPPFLAGS += \
|
|||
sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
|
||||
|
||||
__OBJS := $(subst $(obj),,$(OBJS))
|
||||
__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
|
||||
__LIBS := $(subst $(obj),,$(LIBS))
|
||||
|
||||
#########################################################################
|
||||
#########################################################################
|
||||
|
@ -380,7 +359,7 @@ endif
|
|||
|
||||
build := -f $(TOPDIR)/scripts/Makefile.build -C
|
||||
|
||||
all: $(ALL-y) $(SUBDIR_EXAMPLES)
|
||||
all: $(ALL-y) $(SUBDIR_EXAMPLES-y)
|
||||
|
||||
$(obj)u-boot.dtb: checkdtc $(obj)u-boot
|
||||
$(MAKE) $(build) dts binary
|
||||
|
@ -549,7 +528,7 @@ GEN_UBOOT = \
|
|||
endif
|
||||
|
||||
$(obj)u-boot: depend \
|
||||
$(SUBDIR_TOOLS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
|
||||
$(SUBDIR_TOOLS) $(OBJS) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
|
||||
$(GEN_UBOOT)
|
||||
ifeq ($(CONFIG_KALLSYMS),y)
|
||||
smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \
|
||||
|
@ -564,16 +543,11 @@ $(OBJS):
|
|||
|
||||
$(LIBS): depend $(SUBDIR_TOOLS)
|
||||
$(MAKE) $(build) $(dir $(subst $(obj),,$@))
|
||||
mv $(dir $@)built-in.o $@
|
||||
|
||||
$(LIBBOARD): depend $(LIBS)
|
||||
$(MAKE) $(build) $(dir $(subst $(obj),,$@))
|
||||
mv $(dir $@)built-in.o $@
|
||||
|
||||
$(SUBDIRS): depend
|
||||
$(MAKE) -C $@ all
|
||||
|
||||
$(SUBDIR_EXAMPLES): $(obj)u-boot
|
||||
$(SUBDIR_EXAMPLES-y): $(obj)u-boot
|
||||
|
||||
$(LDSCRIPT): depend
|
||||
$(MAKE) -C $(dir $@) $(notdir $@)
|
||||
|
@ -593,9 +567,6 @@ $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend
|
|||
$(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend
|
||||
$(MAKE) -C spl all CONFIG_TPL_BUILD=y
|
||||
|
||||
updater:
|
||||
$(MAKE) -C tools/updater all
|
||||
|
||||
# Explicitly make _depend in subdirs containing multiple targets to prevent
|
||||
# parallel sub-makes creating .depend files simultaneously.
|
||||
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
|
||||
|
@ -634,7 +605,7 @@ SYSTEM_MAP = \
|
|||
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
|
||||
LC_ALL=C sort
|
||||
$(obj)System.map: $(obj)u-boot
|
||||
@$(call SYSTEM_MAP,$<) > $(obj)System.map
|
||||
@$(call SYSTEM_MAP,$<) > $@
|
||||
|
||||
checkthumb:
|
||||
@if test $(call cc-version) -lt 0404; then \
|
||||
|
@ -738,7 +709,7 @@ else # !config.mk
|
|||
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
|
||||
$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
|
||||
$(filter-out tools,$(SUBDIRS)) \
|
||||
updater depend dep tags ctags etags cscope $(obj)System.map:
|
||||
depend dep tags ctags etags cscope $(obj)System.map:
|
||||
@echo "System not configured - see README" >&2
|
||||
@ exit 1
|
||||
|
||||
|
@ -806,12 +777,6 @@ sinclude $(obj).boards.depend
|
|||
$(obj).boards.depend: boards.cfg
|
||||
@awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@
|
||||
|
||||
#
|
||||
# Functions to generate common board directory names
|
||||
#
|
||||
lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
|
||||
ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
|
||||
|
||||
#########################################################################
|
||||
#########################################################################
|
||||
|
||||
|
@ -888,8 +853,6 @@ clobber: tidy
|
|||
@rm -f $(obj)MLO MLO.byteswap
|
||||
@rm -f $(obj)SPL
|
||||
@rm -f $(obj)tools/xway-swap-bytes
|
||||
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
|
||||
@rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
|
||||
@rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
|
||||
@rm -fr $(obj)include/generated
|
||||
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
|
||||
|
|
95
README
95
README
|
@ -423,16 +423,50 @@ The following options need to be configured:
|
|||
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
|
||||
This value denotes start offset of DSP CCSR space.
|
||||
|
||||
CONFIG_SYS_FSL_DDR_EMU
|
||||
Specify emulator support for DDR. Some DDR features such as
|
||||
deskew training are not available.
|
||||
|
||||
- Generic CPU options:
|
||||
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
|
||||
|
||||
Defines the endianess of the CPU. Implementation of those
|
||||
values is arch specific.
|
||||
|
||||
CONFIG_SYS_FSL_DDR
|
||||
Freescale DDR driver in use. This type of DDR controller is
|
||||
found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
|
||||
SoCs.
|
||||
|
||||
CONFIG_SYS_FSL_DDR_ADDR
|
||||
Freescale DDR memory-mapped register base.
|
||||
|
||||
CONFIG_SYS_FSL_DDR_EMU
|
||||
Specify emulator support for DDR. Some DDR features such as
|
||||
deskew training are not available.
|
||||
|
||||
CONFIG_SYS_FSL_DDRC_GEN1
|
||||
Freescale DDR1 controller.
|
||||
|
||||
CONFIG_SYS_FSL_DDRC_GEN2
|
||||
Freescale DDR2 controller.
|
||||
|
||||
CONFIG_SYS_FSL_DDRC_GEN3
|
||||
Freescale DDR3 controller.
|
||||
|
||||
CONFIG_SYS_FSL_DDRC_ARM_GEN3
|
||||
Freescale DDR3 controller for ARM-based SoCs.
|
||||
|
||||
CONFIG_SYS_FSL_DDR1
|
||||
Board config to use DDR1. It can be enabled for SoCs with
|
||||
Freescale DDR1 or DDR2 controllers, depending on the board
|
||||
implemetation.
|
||||
|
||||
CONFIG_SYS_FSL_DDR2
|
||||
Board config to use DDR2. It can be eanbeld for SoCs with
|
||||
Freescale DDR2 or DDR3 controllers, depending on the board
|
||||
implementation.
|
||||
|
||||
CONFIG_SYS_FSL_DDR3
|
||||
Board config to use DDR3. It can be enabled for SoCs with
|
||||
Freescale DDR3 controllers.
|
||||
|
||||
- Intel Monahans options:
|
||||
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
|
||||
|
||||
|
@ -1979,6 +2013,21 @@ CBFS (Coreboot Filesystem) support
|
|||
kernel). Defining CONFIG_STATUS_LED enables this
|
||||
feature in U-Boot.
|
||||
|
||||
Additional options:
|
||||
|
||||
CONFIG_GPIO_LED
|
||||
The status LED can be connected to a GPIO pin.
|
||||
In such cases, the gpio_led driver can be used as a
|
||||
status LED backend implementation. Define CONFIG_GPIO_LED
|
||||
to include the gpio_led driver in the U-Boot binary.
|
||||
|
||||
CONFIG_GPIO_LED_INVERTED_TABLE
|
||||
Some GPIO connected LEDs may have inverted polarity in which
|
||||
case the GPIO high value corresponds to LED off state and
|
||||
GPIO low value corresponds to LED on state.
|
||||
In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
|
||||
with a list of GPIO LEDs that have inverted polarity.
|
||||
|
||||
- CAN Support: CONFIG_CAN_DRIVER
|
||||
|
||||
Defining CONFIG_CAN_DRIVER enables CAN driver support
|
||||
|
@ -2056,6 +2105,42 @@ CBFS (Coreboot Filesystem) support
|
|||
- CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
|
||||
- CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
|
||||
|
||||
- drivers/i2c/sh_i2c.c:
|
||||
- activate this driver with CONFIG_SYS_I2C_SH
|
||||
- This driver adds from 2 to 5 i2c buses
|
||||
|
||||
- CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
|
||||
- CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
|
||||
- CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
|
||||
- CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
|
||||
- CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
|
||||
- CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
|
||||
- CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
|
||||
- CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
|
||||
- CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
|
||||
- CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
|
||||
- CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
|
||||
- CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
|
||||
- CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
|
||||
|
||||
- drivers/i2c/omap24xx_i2c.c
|
||||
- activate this driver with CONFIG_SYS_I2C_OMAP24XX
|
||||
- CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
|
||||
- CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
|
||||
- CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
|
||||
- CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
|
||||
- CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
|
||||
- CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
|
||||
- CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
|
||||
- CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
|
||||
- CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
|
||||
- CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
|
||||
|
||||
- drivers/i2c/zynq_i2c.c
|
||||
- activate this driver with CONFIG_SYS_I2C_ZYNQ
|
||||
- set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
|
||||
- set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
|
||||
|
||||
additional defines:
|
||||
|
||||
CONFIG_SYS_NUM_I2C_BUSES
|
||||
|
@ -3162,7 +3247,7 @@ FIT uImage format:
|
|||
|
||||
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
|
||||
Set for the SPL on PPC mpc8xxx targets, support for
|
||||
arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
|
||||
drivers/ddr/fsl/libddr.o in SPL binary.
|
||||
|
||||
CONFIG_SPL_COMMON_INIT_DDR
|
||||
Set for common ddr init with serial presence detect in
|
||||
|
|
|
@ -4,5 +4,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \
|
||||
api_platform-$(ARCH).o
|
||||
obj-y += api.o api_display.o api_net.o api_storage.o
|
||||
obj-$(CONFIG_ARM) += api_platform-arm.o
|
||||
obj-$(CONFIG_PPC) += api_platform-powerpc.o
|
||||
|
|
|
@ -19,4 +19,3 @@ obj-y += ddr.o
|
|||
obj-y += emif4.o
|
||||
obj-y += board.o
|
||||
obj-y += mux.o
|
||||
obj-$(CONFIG_NAND_OMAP_GPMC) += elm.o
|
||||
|
|
|
@ -22,17 +22,6 @@
|
|||
|
||||
struct gpmc *gpmc_cfg;
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
|
||||
M_NAND_GPMC_CONFIG1,
|
||||
M_NAND_GPMC_CONFIG2,
|
||||
M_NAND_GPMC_CONFIG3,
|
||||
M_NAND_GPMC_CONFIG4,
|
||||
M_NAND_GPMC_CONFIG5,
|
||||
M_NAND_GPMC_CONFIG6, 0
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
|
||||
u32 size)
|
||||
|
@ -61,11 +50,34 @@ void gpmc_init(void)
|
|||
{
|
||||
/* putting a blanket check on GPMC based on ZeBu for now */
|
||||
gpmc_cfg = (struct gpmc *)GPMC_BASE;
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
const u32 *gpmc_config = NULL;
|
||||
u32 base = 0;
|
||||
#if defined(CONFIG_NOR)
|
||||
/* configure GPMC for NOR */
|
||||
const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
|
||||
STNOR_GPMC_CONFIG2,
|
||||
STNOR_GPMC_CONFIG3,
|
||||
STNOR_GPMC_CONFIG4,
|
||||
STNOR_GPMC_CONFIG5,
|
||||
STNOR_GPMC_CONFIG6,
|
||||
STNOR_GPMC_CONFIG7
|
||||
};
|
||||
u32 size = GPMC_SIZE_16M;
|
||||
u32 base = CONFIG_SYS_FLASH_BASE;
|
||||
#elif defined(CONFIG_NAND)
|
||||
/* configure GPMC for NAND */
|
||||
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
|
||||
M_NAND_GPMC_CONFIG2,
|
||||
M_NAND_GPMC_CONFIG3,
|
||||
M_NAND_GPMC_CONFIG4,
|
||||
M_NAND_GPMC_CONFIG5,
|
||||
M_NAND_GPMC_CONFIG6,
|
||||
0
|
||||
};
|
||||
u32 size = GPMC_SIZE_256M;
|
||||
u32 base = CONFIG_SYS_NAND_BASE;
|
||||
#else
|
||||
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
|
||||
u32 size = 0;
|
||||
u32 base = 0;
|
||||
#endif
|
||||
/* global settings */
|
||||
writel(0x00000008, &gpmc_cfg->sysconfig);
|
||||
|
@ -81,12 +93,6 @@ void gpmc_init(void)
|
|||
*/
|
||||
writel(0, &gpmc_cfg->cs[0].config7);
|
||||
sdelay(1000);
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
gpmc_config = gpmc_m_nand;
|
||||
|
||||
base = PISMO1_NAND_BASE;
|
||||
size = PISMO1_NAND_SIZE;
|
||||
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
|
||||
#endif
|
||||
/* enable chip-select specific configurations */
|
||||
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
|
||||
}
|
||||
|
|
|
@ -18,7 +18,7 @@ obj-y += abb.o
|
|||
endif
|
||||
|
||||
ifneq ($(CONFIG_OMAP54XX),)
|
||||
COBJS += pipe3-phy.o
|
||||
obj-y += pipe3-phy.o
|
||||
obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
|
||||
endif
|
||||
|
||||
|
|
|
@ -779,7 +779,8 @@ void gpi2c_init(void)
|
|||
static int gpi2c = 1;
|
||||
|
||||
if (gpi2c) {
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
|
||||
CONFIG_SYS_OMAP24_I2C_SLAVE);
|
||||
gpi2c = 0;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -32,6 +32,11 @@ SECTIONS
|
|||
. = ALIGN(4);
|
||||
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*_i2c_*)));
|
||||
} >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
__image_copy_end = .;
|
||||
_end = .;
|
||||
|
|
|
@ -98,7 +98,7 @@ void spl_board_init(void)
|
|||
gpmc_init();
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_I2C_SUPPORT
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
|
|
@ -708,7 +708,7 @@ void per_clocks_enable(void)
|
|||
sr32(&prcm_base->iclken_per, 17, 1, 1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
||||
#ifdef CONFIG_SYS_I2C_OMAP34XX
|
||||
/* Turn on all 3 I2C clocks */
|
||||
sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
|
||||
sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
|
||||
|
|
|
@ -14,10 +14,4 @@ obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
|
|||
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
|
||||
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
|
||||
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
|
||||
obj-$(CONFIG_TMU_TIMER) += sh_timer.o
|
||||
|
||||
SRCS += $(obj)sh_timer.c
|
||||
# from arch/sh/lib/ directory
|
||||
$(obj)sh_timer.c:
|
||||
@rm -f $(obj)sh_timer.c
|
||||
ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c
|
||||
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
|
||||
|
|
|
@ -4,8 +4,8 @@
|
|||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef _I2C_H_
|
||||
#define _I2C_H_
|
||||
#ifndef _I2C_AM33XX_H_
|
||||
#define _I2C_AM33XX_H_
|
||||
|
||||
#define I2C_BASE1 0x44E0B000
|
||||
#define I2C_BASE2 0x4802A000
|
||||
|
@ -62,4 +62,4 @@ struct i2c {
|
|||
#define I2C_IP_CLK 48000000
|
||||
#define I2C_INTERNAL_SAMPLING_CLK 12000000
|
||||
|
||||
#endif /* _I2C_H_ */
|
||||
#endif /* _I2C_AM33XX_H_ */
|
||||
|
|
|
@ -68,9 +68,4 @@
|
|||
#define PISMO2_NAND_CS0 7
|
||||
#define PISMO2_NAND_CS1 8
|
||||
|
||||
/* make it readable for the gpmc_init */
|
||||
#define PISMO1_NOR_BASE FLASH_BASE
|
||||
#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE
|
||||
#define PISMO1_NAND_SIZE GPMC_SIZE_256M
|
||||
|
||||
#endif /* endif _MEM_H_ */
|
||||
|
|
|
@ -350,6 +350,7 @@ struct bcm2835_mbox_tag_overscan {
|
|||
u32 top;
|
||||
u32 bottom;
|
||||
u32 left;
|
||||
u32 right;
|
||||
} resp;
|
||||
} body;
|
||||
};
|
||||
|
|
|
@ -178,10 +178,11 @@ struct venc_regs {
|
|||
#define LCD_INTERFACE_24_BIT 3
|
||||
|
||||
/* Polarity */
|
||||
#define DSS_IVS (1 << 12)
|
||||
#define DSS_IHS (1 << 13)
|
||||
#define DSS_IPC (1 << 14)
|
||||
#define DSS_IEO (1 << 15)
|
||||
#define DSS_IVS (1 << 12)
|
||||
#define DSS_IHS (1 << 13)
|
||||
#define DSS_IPC (1 << 14)
|
||||
#define DSS_IEO (1 << 15)
|
||||
#define DSS_ONOFF (1 << 17)
|
||||
|
||||
/* GFX format */
|
||||
#define GFXFORMAT_BITMAP1 (0x0 << 1)
|
||||
|
|
|
@ -68,4 +68,20 @@
|
|||
}
|
||||
#endif
|
||||
|
||||
enum omap_ecc {
|
||||
/* 1-bit ECC calculation by Software, Error detection by Software */
|
||||
OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
|
||||
/* 1-bit ECC calculation by GPMC, Error detection by Software */
|
||||
/* ECC layout compatible to legacy ROMCODE. */
|
||||
OMAP_ECC_HAM1_CODE_HW,
|
||||
/* 4-bit ECC calculation by GPMC, Error detection by Software */
|
||||
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
|
||||
/* 4-bit ECC calculation by GPMC, Error detection by ELM */
|
||||
OMAP_ECC_BCH4_CODE_HW,
|
||||
/* 8-bit ECC calculation by GPMC, Error detection by Software */
|
||||
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
|
||||
/* 8-bit ECC calculation by GPMC, Error detection by ELM */
|
||||
OMAP_ECC_BCH8_CODE_HW,
|
||||
};
|
||||
|
||||
#endif /* __ASM_OMAP_GPMC_H */
|
||||
|
|
0
arch/blackfin/cpu/bootrom-asm-offsets.awk
Executable file → Normal file
0
arch/blackfin/cpu/bootrom-asm-offsets.awk
Executable file → Normal file
|
@ -12,12 +12,12 @@
|
|||
#define OS_LOG_MAGIC_ADDR ((unsigned long *)0x4f0)
|
||||
#define OS_LOG_PTR_ADDR ((char **)0x4f4)
|
||||
|
||||
bool bfin_os_log_check(void)
|
||||
int bfin_os_log_check(void)
|
||||
{
|
||||
if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC)
|
||||
return false;
|
||||
return 0;
|
||||
*OS_LOG_MAGIC_ADDR = 0;
|
||||
return true;
|
||||
return 1;
|
||||
}
|
||||
|
||||
void bfin_os_log_dump(void)
|
||||
|
|
|
@ -51,7 +51,7 @@ extern u_long get_dclk(void);
|
|||
|
||||
# define bfin_revid() (bfin_read_CHIPID() >> 28)
|
||||
|
||||
extern bool bfin_os_log_check(void);
|
||||
extern int bfin_os_log_check(void);
|
||||
extern void bfin_os_log_dump(void);
|
||||
|
||||
extern void blackfin_icache_flush_range(const void *, const void *);
|
||||
|
|
|
@ -30,7 +30,7 @@ SECTIONS
|
|||
{
|
||||
__data_start = .;
|
||||
#ifdef CONFIG_OF_EMBED
|
||||
dts/libdts.o (.data)
|
||||
dts/built-in.o (.data)
|
||||
#endif
|
||||
*(.data)
|
||||
__data_end = .;
|
||||
|
|
|
@ -20,15 +20,6 @@
|
|||
|
||||
#define RA t9
|
||||
|
||||
/*
|
||||
* 16kB is the maximum size of instruction and data caches on MIPS 4K,
|
||||
* 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
|
||||
*
|
||||
* Note that the above size is the maximum size of primary cache. U-Boot
|
||||
* doesn't have L2 cache support for now.
|
||||
*/
|
||||
#define MIPS_MAX_CACHE_SIZE 0x10000
|
||||
|
||||
#define INDEX_BASE CKSEG0
|
||||
|
||||
.macro cache_op op addr
|
||||
|
@ -126,12 +117,85 @@ LEAF(mips_init_dcache)
|
|||
*/
|
||||
NESTED(mips_cache_reset, 0, ra)
|
||||
move RA, ra
|
||||
li t2, CONFIG_SYS_ICACHE_SIZE
|
||||
li t3, CONFIG_SYS_DCACHE_SIZE
|
||||
|
||||
#if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \
|
||||
!defined(CONFIG_SYS_CACHELINE_SIZE)
|
||||
/* read Config1 for use below */
|
||||
mfc0 t5, CP0_CONFIG, 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_CACHELINE_SIZE
|
||||
li t7, CONFIG_SYS_CACHELINE_SIZE
|
||||
li t8, CONFIG_SYS_CACHELINE_SIZE
|
||||
#else
|
||||
/* Detect I-cache line size. */
|
||||
srl t8, t5, MIPS_CONF1_IL_SHIFT
|
||||
andi t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT)
|
||||
beqz t8, 1f
|
||||
li t6, 2
|
||||
sllv t8, t6, t8
|
||||
|
||||
li v0, MIPS_MAX_CACHE_SIZE
|
||||
1: /* Detect D-cache line size. */
|
||||
srl t7, t5, MIPS_CONF1_DL_SHIFT
|
||||
andi t7, t7, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
|
||||
beqz t7, 1f
|
||||
li t6, 2
|
||||
sllv t7, t6, t7
|
||||
1:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_ICACHE_SIZE
|
||||
li t2, CONFIG_SYS_ICACHE_SIZE
|
||||
#else
|
||||
/* Detect I-cache size. */
|
||||
srl t6, t5, MIPS_CONF1_IS_SHIFT
|
||||
andi t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT)
|
||||
li t4, 32
|
||||
xori t2, t6, 0x7
|
||||
beqz t2, 1f
|
||||
addi t6, t6, 1
|
||||
sllv t4, t4, t6
|
||||
1: /* At this point t4 == I-cache sets. */
|
||||
mul t2, t4, t8
|
||||
srl t6, t5, MIPS_CONF1_IA_SHIFT
|
||||
andi t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT)
|
||||
addi t6, t6, 1
|
||||
/* At this point t6 == I-cache ways. */
|
||||
mul t2, t2, t6
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_DCACHE_SIZE
|
||||
li t3, CONFIG_SYS_DCACHE_SIZE
|
||||
#else
|
||||
/* Detect D-cache size. */
|
||||
srl t6, t5, MIPS_CONF1_DS_SHIFT
|
||||
andi t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
|
||||
li t4, 32
|
||||
xori t3, t6, 0x7
|
||||
beqz t3, 1f
|
||||
addi t6, t6, 1
|
||||
sllv t4, t4, t6
|
||||
1: /* At this point t4 == I-cache sets. */
|
||||
mul t3, t4, t7
|
||||
srl t6, t5, MIPS_CONF1_DA_SHIFT
|
||||
andi t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
|
||||
addi t6, t6, 1
|
||||
/* At this point t6 == I-cache ways. */
|
||||
mul t3, t3, t6
|
||||
#endif
|
||||
|
||||
/* Determine the largest L1 cache size */
|
||||
#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
|
||||
#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
|
||||
li v0, CONFIG_SYS_ICACHE_SIZE
|
||||
#else
|
||||
li v0, CONFIG_SYS_DCACHE_SIZE
|
||||
#endif
|
||||
#else
|
||||
move v0, t2
|
||||
sltu t1, t2, t3
|
||||
movn v0, t3, t1
|
||||
#endif
|
||||
/*
|
||||
* Now clear that much memory starting from zero.
|
||||
*/
|
||||
|
@ -163,7 +227,7 @@ NESTED(mips_cache_reset, 0, ra)
|
|||
* then initialize D-cache.
|
||||
*/
|
||||
move a1, t3
|
||||
move a2, t8
|
||||
move a2, t7
|
||||
PTR_LA v1, mips_init_dcache
|
||||
jalr v1
|
||||
|
||||
|
|
|
@ -34,28 +34,89 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_CACHELINE_SIZE
|
||||
|
||||
static inline unsigned long icache_line_size(void)
|
||||
{
|
||||
return CONFIG_SYS_CACHELINE_SIZE;
|
||||
}
|
||||
|
||||
static inline unsigned long dcache_line_size(void)
|
||||
{
|
||||
return CONFIG_SYS_CACHELINE_SIZE;
|
||||
}
|
||||
|
||||
#else /* !CONFIG_SYS_CACHELINE_SIZE */
|
||||
|
||||
static inline unsigned long icache_line_size(void)
|
||||
{
|
||||
unsigned long conf1, il;
|
||||
conf1 = read_c0_config1();
|
||||
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
|
||||
if (!il)
|
||||
return 0;
|
||||
return 2 << il;
|
||||
}
|
||||
|
||||
static inline unsigned long dcache_line_size(void)
|
||||
{
|
||||
unsigned long conf1, dl;
|
||||
conf1 = read_c0_config1();
|
||||
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
|
||||
if (!dl)
|
||||
return 0;
|
||||
return 2 << dl;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_SYS_CACHELINE_SIZE */
|
||||
|
||||
void flush_cache(ulong start_addr, ulong size)
|
||||
{
|
||||
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
|
||||
unsigned long addr = start_addr & ~(lsize - 1);
|
||||
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
|
||||
unsigned long ilsize = icache_line_size();
|
||||
unsigned long dlsize = dcache_line_size();
|
||||
unsigned long addr, aend;
|
||||
|
||||
/* aend will be miscalculated when size is zero, so we return here */
|
||||
if (size == 0)
|
||||
return;
|
||||
|
||||
addr = start_addr & ~(dlsize - 1);
|
||||
aend = (start_addr + size - 1) & ~(dlsize - 1);
|
||||
|
||||
if (ilsize == dlsize) {
|
||||
/* flush I-cache & D-cache simultaneously */
|
||||
while (1) {
|
||||
cache_op(HIT_WRITEBACK_INV_D, addr);
|
||||
cache_op(HIT_INVALIDATE_I, addr);
|
||||
if (addr == aend)
|
||||
break;
|
||||
addr += dlsize;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* flush D-cache */
|
||||
while (1) {
|
||||
cache_op(HIT_WRITEBACK_INV_D, addr);
|
||||
if (addr == aend)
|
||||
break;
|
||||
addr += dlsize;
|
||||
}
|
||||
|
||||
/* flush I-cache */
|
||||
addr = start_addr & ~(ilsize - 1);
|
||||
aend = (start_addr + size - 1) & ~(ilsize - 1);
|
||||
while (1) {
|
||||
cache_op(HIT_INVALIDATE_I, addr);
|
||||
if (addr == aend)
|
||||
break;
|
||||
addr += lsize;
|
||||
addr += ilsize;
|
||||
}
|
||||
}
|
||||
|
||||
void flush_dcache_range(ulong start_addr, ulong stop)
|
||||
{
|
||||
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
|
||||
unsigned long lsize = dcache_line_size();
|
||||
unsigned long addr = start_addr & ~(lsize - 1);
|
||||
unsigned long aend = (stop - 1) & ~(lsize - 1);
|
||||
|
||||
|
@ -69,7 +130,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
|
|||
|
||||
void invalidate_dcache_range(ulong start_addr, ulong stop)
|
||||
{
|
||||
unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
|
||||
unsigned long lsize = dcache_line_size();
|
||||
unsigned long addr = start_addr & ~(lsize - 1);
|
||||
unsigned long aend = (stop - 1) & ~(lsize - 1);
|
||||
|
||||
|
|
|
@ -51,7 +51,7 @@ _start:
|
|||
*/
|
||||
.word CONFIG_SYS_XWAY_EBU_BOOTCFG
|
||||
.word 0x0
|
||||
#elif defined(CONFIG_QEMU_MALTA)
|
||||
#elif defined(CONFIG_MALTA)
|
||||
/*
|
||||
* Linux expects the Board ID here.
|
||||
*/
|
||||
|
|
|
@ -1,23 +1,67 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
|
||||
* Copyright (C) 2013 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef _MIPS_ASM_MALTA_H
|
||||
#define _MIPS_ASM_MALTA_H
|
||||
|
||||
#define MALTA_IO_PORT_BASE 0x18000000
|
||||
#define MALTA_GT_BASE 0x1be00000
|
||||
#define MALTA_GT_PCIIO_BASE 0x18000000
|
||||
#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
|
||||
|
||||
#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8)
|
||||
#define MALTA_MSC01_BIU_BASE 0x1bc80000
|
||||
#define MALTA_MSC01_PCI_BASE 0x1bd00000
|
||||
#define MALTA_MSC01_PBC_BASE 0x1bd40000
|
||||
#define MALTA_MSC01_IP1_BASE 0x1bc00000
|
||||
#define MALTA_MSC01_IP1_SIZE 0x00400000
|
||||
#define MALTA_MSC01_IP2_BASE1 0x10000000
|
||||
#define MALTA_MSC01_IP2_SIZE1 0x08000000
|
||||
#define MALTA_MSC01_IP2_BASE2 0x18000000
|
||||
#define MALTA_MSC01_IP2_SIZE2 0x04000000
|
||||
#define MALTA_MSC01_IP3_BASE 0x1c000000
|
||||
#define MALTA_MSC01_IP3_SIZE 0x04000000
|
||||
#define MALTA_MSC01_PCIMEM_BASE 0x10000000
|
||||
#define MALTA_MSC01_PCIMEM_SIZE 0x10000000
|
||||
#define MALTA_MSC01_PCIMEM_MAP 0x10000000
|
||||
#define MALTA_MSC01_PCIIO_BASE 0x1b000000
|
||||
#define MALTA_MSC01_PCIIO_SIZE 0x00800000
|
||||
#define MALTA_MSC01_PCIIO_MAP 0x00000000
|
||||
#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8)
|
||||
|
||||
#define MALTA_GT_BASE 0x1be00000
|
||||
#define MALTA_ASCIIWORD 0x1f000410
|
||||
#define MALTA_ASCIIPOS0 0x1f000418
|
||||
#define MALTA_ASCIIPOS1 0x1f000420
|
||||
#define MALTA_ASCIIPOS2 0x1f000428
|
||||
#define MALTA_ASCIIPOS3 0x1f000430
|
||||
#define MALTA_ASCIIPOS4 0x1f000438
|
||||
#define MALTA_ASCIIPOS5 0x1f000440
|
||||
#define MALTA_ASCIIPOS6 0x1f000448
|
||||
#define MALTA_ASCIIPOS7 0x1f000450
|
||||
|
||||
#define MALTA_RESET_BASE 0x1f000500
|
||||
#define GORESET 0x42
|
||||
#define MALTA_RESET_BASE 0x1f000500
|
||||
#define GORESET 0x42
|
||||
|
||||
#define MALTA_FLASH_BASE 0x1fc00000
|
||||
#define MALTA_FLASH_BASE 0x1e000000
|
||||
|
||||
#define MALTA_REVISION 0x1fc00010
|
||||
#define MALTA_REVISION_CORID_SHF 10
|
||||
#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF)
|
||||
#define MALTA_REVISION_CORID_CORE_LV 1
|
||||
#define MALTA_REVISION_CORID_CORE_FPGA6 14
|
||||
|
||||
#define PCI_CFG_PIIX4_PIRQRCA 0x60
|
||||
#define PCI_CFG_PIIX4_PIRQRCB 0x61
|
||||
#define PCI_CFG_PIIX4_PIRQRCC 0x62
|
||||
#define PCI_CFG_PIIX4_PIRQRCD 0x63
|
||||
#define PCI_CFG_PIIX4_SERIRQC 0x64
|
||||
#define PCI_CFG_PIIX4_GENCFG 0xb0
|
||||
|
||||
#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7)
|
||||
#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6)
|
||||
|
||||
#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
|
||||
|
||||
#endif /* _MIPS_ASM_MALTA_H */
|
||||
|
|
|
@ -494,11 +494,17 @@
|
|||
#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
|
||||
#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
|
||||
#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
|
||||
#define MIPS_CONF1_DA_SHIFT 7
|
||||
#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
|
||||
#define MIPS_CONF1_DL_SHIFT 10
|
||||
#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
|
||||
#define MIPS_CONF1_DS_SHIFT 13
|
||||
#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
|
||||
#define MIPS_CONF1_IA_SHIFT 16
|
||||
#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
|
||||
#define MIPS_CONF1_IL_SHIFT 19
|
||||
#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
|
||||
#define MIPS_CONF1_IS_SHIFT 22
|
||||
#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
|
||||
#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
|
||||
|
||||
|
|
|
@ -17,10 +17,10 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define LINUX_MAX_ENVS 256
|
||||
#define LINUX_MAX_ARGS 256
|
||||
|
||||
#if defined(CONFIG_QEMU_MALTA)
|
||||
#define mips_boot_qemu_malta 1
|
||||
#if defined(CONFIG_MALTA)
|
||||
#define mips_boot_malta 1
|
||||
#else
|
||||
#define mips_boot_qemu_malta 0
|
||||
#define mips_boot_malta 0
|
||||
#endif
|
||||
|
||||
static int linux_argc;
|
||||
|
@ -139,7 +139,7 @@ static void linux_env_set(const char *env_name, const char *env_val)
|
|||
strcpy(linux_env_p, env_name);
|
||||
linux_env_p += strlen(env_name);
|
||||
|
||||
if (mips_boot_qemu_malta) {
|
||||
if (mips_boot_malta) {
|
||||
linux_env_p++;
|
||||
linux_env[++linux_env_idx] = linux_env_p;
|
||||
} else {
|
||||
|
@ -196,8 +196,10 @@ static void boot_prep_linux(bootm_headers_t *images)
|
|||
if (cp)
|
||||
linux_env_set("eth1addr", cp);
|
||||
|
||||
if (mips_boot_qemu_malta)
|
||||
linux_env_set("modetty0", "38400n8r");
|
||||
if (mips_boot_malta) {
|
||||
sprintf(env_buf, "%un8r", gd->baudrate);
|
||||
linux_env_set("modetty0", env_buf);
|
||||
}
|
||||
}
|
||||
|
||||
static void boot_jump_linux(bootm_headers_t *images)
|
||||
|
@ -210,7 +212,7 @@ static void boot_jump_linux(bootm_headers_t *images)
|
|||
|
||||
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
|
||||
|
||||
if (mips_boot_qemu_malta)
|
||||
if (mips_boot_malta)
|
||||
linux_extra = gd->ram_size;
|
||||
|
||||
/* we assume that the kernel is in place */
|
||||
|
|
3
arch/powerpc/cpu/Makefile
Normal file
3
arch/powerpc/cpu/Makefile
Normal file
|
@ -0,0 +1,3 @@
|
|||
ifneq ($(filter mpc83xx mpc85xx mpc86xx,$(CPU)),)
|
||||
obj-y += mpc8xxx/
|
||||
endif
|
|
@ -4,8 +4,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
$(shell mkdir -p $(OBJTREE)/board/freescale/common)
|
||||
|
||||
extra-y = start.o
|
||||
obj-y := cpu.o
|
||||
obj-y += traps.o
|
||||
|
|
1
arch/powerpc/cpu/mpc824x/.gitignore
vendored
1
arch/powerpc/cpu/mpc824x/.gitignore
vendored
|
@ -1 +0,0 @@
|
|||
/bedbug_603e.c
|
|
@ -5,15 +5,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)drivers/epic $(obj)drivers/i2c)
|
||||
endif
|
||||
|
||||
extra-y = start.o
|
||||
obj-y = traps.o cpu.o cpu_init.o interrupts.o speed.o \
|
||||
drivers/epic/epic1.o drivers/i2c/i2c.o pci.o
|
||||
obj-y += bedbug_603e.o
|
||||
|
||||
SRCS += $(obj)bedbug_603e.c
|
||||
$(obj)bedbug_603e.c:
|
||||
ln -sf $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c
|
||||
obj-y += ../mpc8260/bedbug_603e.o
|
||||
|
|
|
@ -52,7 +52,7 @@ cpu_init_f (void)
|
|||
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
|
||||
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
|
||||
|
||||
#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
|
||||
#if defined(CONFIG_MUSENKI)
|
||||
/* Why is this here, you ask? Try, just try setting 0x8000
|
||||
* in PCIACR with CONFIG_WRITE_HALFWORD()
|
||||
* this one was a stumper, and we are annoyed
|
||||
|
@ -142,9 +142,7 @@ cpu_init_f (void)
|
|||
|
||||
CONFIG_READ_WORD(PICR2, val);
|
||||
val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
|
||||
#ifndef CONFIG_PN62
|
||||
val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
|
||||
#endif
|
||||
CONFIG_WRITE_WORD(PICR2, val);
|
||||
|
||||
CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
|
||||
|
@ -186,7 +184,7 @@ cpu_init_f (void)
|
|||
* should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
|
||||
* its not set, we define it to zero in this file
|
||||
*/
|
||||
#if defined(CONFIG_CU824) || defined(CONFIG_PN62)
|
||||
#if defined(CONFIG_CU824)
|
||||
CONFIG_WRITE_WORD(MCCR4,
|
||||
(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
|
||||
(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
|
||||
|
|
|
@ -38,21 +38,11 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
|||
# Stub implementations of cache management functions for USB
|
||||
obj-y += cache.o
|
||||
|
||||
ifdef CONFIG_FSL_DDR2
|
||||
obj-$(CONFIG_MPC8349) += ddr-gen2.o
|
||||
SRCS += $(obj)ddr-gen2.c
|
||||
ifdef CONFIG_SYS_FSL_DDR2
|
||||
obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o
|
||||
else
|
||||
obj-y += spd_sdram.o
|
||||
endif
|
||||
obj-$(CONFIG_FSL_DDR2) += law.o
|
||||
obj-$(CONFIG_SYS_FSL_DDR2) += law.o
|
||||
|
||||
endif # not minimal
|
||||
|
||||
$(obj)ddr-gen1.c:
|
||||
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
|
||||
|
||||
$(obj)ddr-gen2.c:
|
||||
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
|
||||
|
||||
$(obj)ddr-gen3.c:
|
||||
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c
|
||||
|
|
|
@ -15,8 +15,8 @@
|
|||
void ecc_print_status(void)
|
||||
{
|
||||
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
#ifdef CONFIG_FSL_DDR2
|
||||
ccsr_ddr_t *ddr = &immap->ddr;
|
||||
#ifdef CONFIG_SYS_FSL_DDR2
|
||||
struct ccsr_ddr __iomem *ddr = &immap->ddr;
|
||||
#else
|
||||
ddr83xx_t *ddr = &immap->ddr;
|
||||
#endif
|
||||
|
@ -99,8 +99,8 @@ void ecc_print_status(void)
|
|||
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
||||
#ifdef CONFIG_FSL_DDR2
|
||||
ccsr_ddr_t *ddr = &immap->ddr;
|
||||
#ifdef CONFIG_SYS_FSL_DDR2
|
||||
struct ccsr_ddr __iomem *ddr = &immap->ddr;
|
||||
#else
|
||||
ddr83xx_t *ddr = &immap->ddr;
|
||||
#endif
|
||||
|
|
|
@ -29,48 +29,6 @@ obj-$(CONFIG_MP) += release.o
|
|||
obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
|
||||
obj-$(CONFIG_CPM2) += commproc.o
|
||||
|
||||
# supports ddr1
|
||||
obj-$(CONFIG_MPC8540) += ddr-gen1.o
|
||||
obj-$(CONFIG_MPC8560) += ddr-gen1.o
|
||||
obj-$(CONFIG_MPC8541) += ddr-gen1.o
|
||||
obj-$(CONFIG_MPC8555) += ddr-gen1.o
|
||||
|
||||
# supports ddr1/2
|
||||
obj-$(CONFIG_MPC8548) += ddr-gen2.o
|
||||
obj-$(CONFIG_MPC8568) += ddr-gen2.o
|
||||
obj-$(CONFIG_MPC8544) += ddr-gen2.o
|
||||
|
||||
# supports ddr1/2/3
|
||||
obj-$(CONFIG_PPC_C29X) += ddr-gen3.o
|
||||
obj-$(CONFIG_MPC8572) += ddr-gen3.o
|
||||
obj-$(CONFIG_MPC8536) += ddr-gen3.o
|
||||
obj-$(CONFIG_MPC8569) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1010) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1011) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1012) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1013) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1014) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1020) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1021) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1022) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1023) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1024) += ddr-gen3.o
|
||||
obj-$(CONFIG_P1025) += ddr-gen3.o
|
||||
obj-$(CONFIG_P2010) += ddr-gen3.o
|
||||
obj-$(CONFIG_P2020) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_P2041) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_P3041) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_P4080) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_P5020) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_P5040) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_T4240) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_T4160) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_B4420) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_B4860) += ddr-gen3.o
|
||||
obj-$(CONFIG_BSC9131) += ddr-gen3.o
|
||||
obj-$(CONFIG_BSC9132) += ddr-gen3.o
|
||||
obj-$(CONFIG_PPC_T1040) += ddr-gen3.o
|
||||
|
||||
obj-$(CONFIG_CPM2) += ether_fcc.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
obj-$(CONFIG_FSL_CORENET) += liodn.o
|
||||
|
@ -89,6 +47,12 @@ obj-$(CONFIG_PPC_T4160) += t4240_ids.o
|
|||
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
|
||||
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
|
||||
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1042) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1020) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T1022) += t1040_ids.o
|
||||
obj-$(CONFIG_PPC_T2080) += t2080_ids.o
|
||||
obj-$(CONFIG_PPC_T2081) += t2080_ids.o
|
||||
|
||||
|
||||
obj-$(CONFIG_QE) += qe_io.o
|
||||
obj-$(CONFIG_CPM2) += serial_scc.o
|
||||
|
@ -128,6 +92,11 @@ obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
|
|||
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
|
||||
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
|
||||
obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
|
||||
obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
|
||||
obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += cpu_init.o
|
||||
|
|
|
@ -17,12 +17,12 @@
|
|||
#include <asm/cache.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/fsl_ifc.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_lbc.h>
|
||||
#include <post.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -416,7 +416,7 @@ static void dump_spd_ddr_reg(void)
|
|||
int i, j, k, m;
|
||||
u8 *p_8;
|
||||
u32 *p_32;
|
||||
ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
|
||||
struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
|
||||
generic_spd_eeprom_t
|
||||
spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
|
||||
|
||||
|
@ -453,21 +453,21 @@ static void dump_spd_ddr_reg(void)
|
|||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
|
||||
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
break;
|
||||
#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
||||
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
|
||||
case 1:
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
|
||||
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
||||
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
|
||||
case 2:
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
|
||||
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
||||
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
|
||||
case 3:
|
||||
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
|
||||
ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
|
@ -482,7 +482,7 @@ static void dump_spd_ddr_reg(void)
|
|||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
|
||||
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
|
||||
puts("\n");
|
||||
for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
|
||||
for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
|
||||
m = 0;
|
||||
printf("%6d (0x%04x)", k * 4, k * 4);
|
||||
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
|
||||
|
|
|
@ -586,6 +586,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
{
|
||||
int off;
|
||||
int val;
|
||||
int len;
|
||||
sys_info_t sysinfo;
|
||||
|
||||
/* delete crypto node if not on an E-processor */
|
||||
|
@ -615,8 +616,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
|
|||
get_sys_info(&sysinfo);
|
||||
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
|
||||
while (off != -FDT_ERR_NOTFOUND) {
|
||||
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
|
||||
val = cpu_to_fdt32(sysinfo.freq_processor[*reg]);
|
||||
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
|
||||
val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
|
||||
fdt_setprop(blob, off, "clock-frequency", &val, 4);
|
||||
off = fdt_node_offset_by_prop_value(blob, off, "device_type",
|
||||
"cpu", 4);
|
||||
|
|
|
@ -239,9 +239,9 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
|
|||
#endif
|
||||
|
||||
#define CONFIG_SYS_MAX_PCI_EPS 8
|
||||
#define CONFIG_SYS_PCI_EP_LIODN_START 256
|
||||
|
||||
static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
|
||||
static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
|
||||
int ep_liodn_start)
|
||||
{
|
||||
int off, pci_idx = 0, pci_cnt = 0, i, rc;
|
||||
const uint32_t *base_liodn;
|
||||
|
@ -271,7 +271,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
|
|||
continue;
|
||||
}
|
||||
for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
|
||||
liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
|
||||
liodn_offs[i + 1] = ep_liodn_start +
|
||||
i * pci_cnt + pci_idx - *base_liodn;
|
||||
rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
|
||||
liodn_offs, sizeof(liodn_offs));
|
||||
|
@ -338,5 +338,22 @@ void fdt_fixup_liodn(void *blob)
|
|||
fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
|
||||
#endif
|
||||
|
||||
fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
|
||||
ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR;
|
||||
int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0;
|
||||
|
||||
if (pci_ver >= 0x0204) {
|
||||
if (pci_ver >= 0x0300)
|
||||
liodn_base = 1024;
|
||||
else
|
||||
liodn_base = 256;
|
||||
}
|
||||
|
||||
if (liodn_base) {
|
||||
char compat[32];
|
||||
|
||||
sprintf(compat, "fsl,qoriq-pcie-v%d.%d",
|
||||
(pci_ver & 0xff00) >> 8, pci_ver & 0xff);
|
||||
fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base);
|
||||
fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include "mp.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
|
@ -122,7 +122,7 @@ void get_sys_info(sys_info_t *sys_info)
|
|||
sys_info->freq_processor[cpu] =
|
||||
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
|
||||
}
|
||||
#ifdef CONFIG_PPC_B4860
|
||||
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080)
|
||||
#define FM1_CLK_SEL 0xe0000000
|
||||
#define FM1_CLK_SHIFT 29
|
||||
#else
|
||||
|
|
|
@ -7,7 +7,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/fsl_ifc.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
142
arch/powerpc/cpu/mpc85xx/t2080_ids.c
Normal file
142
arch/powerpc/cpu/mpc85xx/t2080_ids.c
Normal file
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_portals.h>
|
||||
#include <asm/fsl_liodn.h>
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN
|
||||
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
|
||||
/* dqrr liodn, frame data liodn, liodn off, sdest */
|
||||
SET_QP_INFO(1, 27, 1, 0),
|
||||
SET_QP_INFO(2, 28, 1, 0),
|
||||
SET_QP_INFO(3, 29, 1, 1),
|
||||
SET_QP_INFO(4, 30, 1, 1),
|
||||
SET_QP_INFO(5, 31, 1, 2),
|
||||
SET_QP_INFO(6, 32, 1, 2),
|
||||
SET_QP_INFO(7, 33, 1, 3),
|
||||
SET_QP_INFO(8, 34, 1, 3),
|
||||
SET_QP_INFO(9, 35, 1, 0),
|
||||
SET_QP_INFO(10, 36, 1, 0),
|
||||
SET_QP_INFO(11, 37, 1, 1),
|
||||
SET_QP_INFO(12, 38, 1, 1),
|
||||
SET_QP_INFO(13, 39, 1, 2),
|
||||
SET_QP_INFO(14, 40, 1, 2),
|
||||
SET_QP_INFO(15, 41, 1, 3),
|
||||
SET_QP_INFO(16, 42, 1, 3),
|
||||
SET_QP_INFO(17, 43, 1, 0),
|
||||
SET_QP_INFO(18, 44, 1, 0),
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_SRIO
|
||||
struct srio_liodn_id_table srio_liodn_tbl[] = {
|
||||
SET_SRIO_LIODN_BASE(1, 307),
|
||||
SET_SRIO_LIODN_BASE(2, 387),
|
||||
};
|
||||
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
|
||||
#endif
|
||||
|
||||
struct liodn_id_table liodn_tbl[] = {
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN
|
||||
SET_QMAN_LIODN(62),
|
||||
SET_BMAN_LIODN(63),
|
||||
#endif
|
||||
|
||||
SET_SDHC_LIODN(1, 552),
|
||||
|
||||
SET_PME_LIODN(117),
|
||||
|
||||
SET_USB_LIODN(1, "fsl-usb2-mph", 553),
|
||||
SET_USB_LIODN(2, "fsl-usb2-dr", 554),
|
||||
|
||||
SET_SATA_LIODN(1, 555),
|
||||
SET_SATA_LIODN(2, 556),
|
||||
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
|
||||
|
||||
SET_DMA_LIODN(1, 147),
|
||||
SET_DMA_LIODN(2, 227),
|
||||
SET_DMA_LIODN(3, 226),
|
||||
|
||||
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
|
||||
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
|
||||
SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
|
||||
SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
|
||||
|
||||
#ifdef CONFIG_SYS_PMAN
|
||||
SET_PMAN_LIODN(1, 513),
|
||||
SET_PMAN_LIODN(2, 514),
|
||||
SET_PMAN_LIODN(3, 515),
|
||||
#endif
|
||||
|
||||
/* SET_NEXUS_LIODN(557), -- not yet implemented */
|
||||
};
|
||||
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
struct liodn_id_table fman1_liodn_tbl[] = {
|
||||
SET_FMAN_RX_1G_LIODN(1, 0, 88),
|
||||
SET_FMAN_RX_1G_LIODN(1, 1, 89),
|
||||
SET_FMAN_RX_1G_LIODN(1, 2, 90),
|
||||
SET_FMAN_RX_1G_LIODN(1, 3, 91),
|
||||
SET_FMAN_RX_1G_LIODN(1, 4, 92),
|
||||
SET_FMAN_RX_1G_LIODN(1, 5, 93),
|
||||
SET_FMAN_RX_10G_LIODN(1, 0, 94),
|
||||
SET_FMAN_RX_10G_LIODN(1, 1, 95),
|
||||
};
|
||||
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
|
||||
#endif
|
||||
|
||||
struct liodn_id_table sec_liodn_tbl[] = {
|
||||
SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
|
||||
SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
|
||||
SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
|
||||
SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
|
||||
SET_SEC_RTIC_LIODN_ENTRY(a, 453),
|
||||
SET_SEC_RTIC_LIODN_ENTRY(b, 549),
|
||||
SET_SEC_RTIC_LIODN_ENTRY(c, 550),
|
||||
SET_SEC_RTIC_LIODN_ENTRY(d, 551),
|
||||
SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
|
||||
SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
|
||||
SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
|
||||
SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
|
||||
SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
|
||||
SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
|
||||
SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
|
||||
SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
|
||||
};
|
||||
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_RMAN
|
||||
struct liodn_id_table rman_liodn_tbl[] = {
|
||||
/* Set RMan block 0-3 liodn offset */
|
||||
SET_RMAN_LIODN(0, 6),
|
||||
SET_RMAN_LIODN(1, 7),
|
||||
SET_RMAN_LIODN(2, 8),
|
||||
SET_RMAN_LIODN(3, 9),
|
||||
};
|
||||
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
|
||||
#endif
|
||||
|
||||
struct liodn_id_table liodn_bases[] = {
|
||||
#ifdef CONFIG_SYS_DPAA_DCE
|
||||
[FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694),
|
||||
#endif
|
||||
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DPAA_PME
|
||||
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DPAA_RMAN
|
||||
[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
|
||||
#endif
|
||||
};
|
208
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
Normal file
208
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
Normal file
|
@ -0,0 +1,208 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/processor.h>
|
||||
#include "fsl_corenet2_serdes.h"
|
||||
|
||||
struct serdes_config {
|
||||
u32 protocol;
|
||||
u8 lanes[SRDS_MAX_LANES];
|
||||
};
|
||||
|
||||
static const struct serdes_config serdes1_cfg_tbl[] = {
|
||||
/* SerDes 1 */
|
||||
{0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, PCIE4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, PCIE4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
|
||||
PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
|
||||
{0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
|
||||
PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
|
||||
{0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
|
||||
{0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, PCIE1,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
#if defined(CONFIG_PPC_T2080)
|
||||
{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
|
||||
XAUI_FM1_MAC9, XAUI_FM1_MAC9,
|
||||
PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
|
||||
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
|
||||
PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
|
||||
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
|
||||
PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
|
||||
XFI_FM1_MAC1, XFI_FM1_MAC2,
|
||||
PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
|
||||
SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
|
||||
PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
|
||||
PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
|
||||
PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
|
||||
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
|
||||
XFI_FM1_MAC1, XFI_FM1_MAC2,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
|
||||
PCIE3, PCIE3, PCIE3, PCIE3} },
|
||||
{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
|
||||
XFI_FM1_MAC1, XFI_FM1_MAC2,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
|
||||
#elif defined(CONFIG_PPC_T2081)
|
||||
{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
|
||||
PCIE4, PCIE4, PCIE4, PCIE4} },
|
||||
{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
|
||||
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
|
||||
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
|
||||
#endif
|
||||
{}
|
||||
};
|
||||
|
||||
#ifndef CONFIG_PPC_T2081
|
||||
static const struct serdes_config serdes2_cfg_tbl[] = {
|
||||
/* SerDes 2 */
|
||||
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
|
||||
{0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
|
||||
{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
|
||||
{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
|
||||
{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
|
||||
{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
|
||||
{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
|
||||
{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
|
||||
{}
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct serdes_config *serdes_cfg_tbl[] = {
|
||||
serdes1_cfg_tbl,
|
||||
#ifndef CONFIG_PPC_T2081
|
||||
serdes2_cfg_tbl,
|
||||
#endif
|
||||
};
|
||||
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
||||
{
|
||||
const struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
ptr = serdes_cfg_tbl[serdes];
|
||||
while (ptr->protocol) {
|
||||
if (ptr->protocol == cfg)
|
||||
return ptr->lanes[lane];
|
||||
ptr++;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
|
||||
{
|
||||
int i;
|
||||
const struct serdes_config *ptr;
|
||||
|
||||
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
ptr = serdes_cfg_tbl[serdes];
|
||||
while (ptr->protocol) {
|
||||
if (ptr->protocol == prtcl)
|
||||
break;
|
||||
ptr++;
|
||||
}
|
||||
|
||||
if (!ptr->protocol)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (ptr->lanes[i] != NONE)
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -86,10 +86,10 @@ struct liodn_id_table liodn_tbl[] = {
|
|||
SET_SATA_LIODN(1, 555),
|
||||
SET_SATA_LIODN(2, 556),
|
||||
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
|
||||
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
|
||||
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
|
||||
|
||||
SET_DMA_LIODN(1, 147),
|
||||
SET_DMA_LIODN(2, 227),
|
||||
|
|
|
@ -16,9 +16,6 @@ obj-$(CONFIG_MP) += release.o
|
|||
|
||||
obj-y += cpu.o
|
||||
obj-y += cpu_init.o
|
||||
# 8610 & 8641 are identical w/regards to DDR
|
||||
obj-$(CONFIG_MPC8610) += ddr-8641.o
|
||||
obj-$(CONFIG_MPC8641) += ddr-8641.o
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
obj-y += interrupts.o
|
||||
obj-$(CONFIG_MP) += mp.o
|
||||
|
|
|
@ -25,7 +25,6 @@ obj-y += cpu.o
|
|||
endif
|
||||
|
||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
||||
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
|
||||
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
|
||||
obj-$(CONFIG_SYS_SRIO) += srio.o
|
||||
obj-$(CONFIG_FSL_LAW) += law.o
|
||||
|
|
|
@ -75,6 +75,8 @@ static struct cpu_type cpu_type_list[] = {
|
|||
CPU_TYPE_ENTRY(T1020, T1020, 0),
|
||||
CPU_TYPE_ENTRY(T1021, T1021, 0),
|
||||
CPU_TYPE_ENTRY(T1022, T1022, 0),
|
||||
CPU_TYPE_ENTRY(T2080, T2080, 0),
|
||||
CPU_TYPE_ENTRY(T2081, T2081, 0),
|
||||
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
|
||||
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
|
||||
CPU_TYPE_ENTRY(BSC9132, 9132, 2),
|
||||
|
|
|
@ -1,29 +0,0 @@
|
|||
#
|
||||
# Copyright 2008-2011 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License
|
||||
# Version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
|
||||
lc_common_dimm_params.o
|
||||
|
||||
obj-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
|
||||
lc_common_dimm_params.o
|
||||
|
||||
obj-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
|
||||
lc_common_dimm_params.o
|
||||
ifdef CONFIG_DDR_SPD
|
||||
SPD := y
|
||||
endif
|
||||
ifdef CONFIG_SPD_EEPROM
|
||||
SPD := y
|
||||
endif
|
||||
ifdef SPD
|
||||
obj-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
|
||||
obj-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
|
||||
obj-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
|
|
@ -9,10 +9,16 @@
|
|||
|
||||
#ifdef CONFIG_MPC85xx
|
||||
#include <asm/config_mpc85xx.h>
|
||||
#define CONFIG_SYS_FSL_DDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MPC86xx
|
||||
#include <asm/config_mpc86xx.h>
|
||||
#define CONFIG_SYS_FSL_DDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MPC83xx
|
||||
#define CONFIG_SYS_FSL_DDR
|
||||
#endif
|
||||
|
||||
#ifndef HWCONFIG_BUFFER_SIZE
|
||||
|
|
|
@ -40,17 +40,20 @@
|
|||
#elif defined(CONFIG_MPC8540)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 8
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
||||
#elif defined(CONFIG_MPC8541)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 8
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
||||
#elif defined(CONFIG_MPC8544)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 10
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
@ -59,6 +62,7 @@
|
|||
#elif defined(CONFIG_MPC8548)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 10
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
@ -77,17 +81,20 @@
|
|||
#elif defined(CONFIG_MPC8555)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 8
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
||||
#elif defined(CONFIG_MPC8560)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 8
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN1
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
|
||||
|
||||
#elif defined(CONFIG_MPC8568)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 10
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN2
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 2
|
||||
#define QE_MURAM_SIZE 0x10000UL
|
||||
#define MAX_QE_RISC 2
|
||||
|
@ -674,7 +681,8 @@
|
|||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_PPC_T1040)
|
||||
#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
|
||||
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define CONFIG_E5500
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
||||
|
@ -710,6 +718,50 @@
|
|||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
|
||||
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#define CONFIG_E6500
|
||||
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
||||
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
|
||||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
|
||||
#define CONFIG_SYS_FSL_QMAN_V3
|
||||
#define CONFIG_MAX_CPUS 4
|
||||
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
||||
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
||||
#define CONFIG_SYS_NUM_FMAN 1
|
||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
#define CONFIG_SYS_FSL_PCI_VER_3_X
|
||||
#if defined(CONFIG_PPC_T2080)
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 4
|
||||
#define CONFIG_SYS_FSL_SRDS_2
|
||||
#define CONFIG_SYS_FSL_SRIO_LIODN
|
||||
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
||||
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
||||
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
||||
#elif defined(CONFIG_PPC_T2081)
|
||||
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
||||
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_PME_PLAT_CLK_DIV 1
|
||||
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
|
||||
#define CONFIG_SYS_FM1_CLK 0
|
||||
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_SYS_FMAN_V3
|
||||
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
|
||||
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
||||
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
|
||||
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
|
||||
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
||||
#define CONFIG_SYS_FSL_SFP_VER_3_0
|
||||
#define CONFIG_SYS_FSL_ISBC_VER 2
|
||||
|
||||
#elif defined(CONFIG_PPC_C29X)
|
||||
#define CONFIG_MAX_CPUS 1
|
||||
#define CONFIG_FSL_SDHC_V2_3
|
||||
|
@ -737,4 +789,10 @@
|
|||
#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
|
||||
!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
|
||||
!defined(CONFIG_SYS_FSL_DDRC_GEN3)
|
||||
#define CONFIG_SYS_FSL_DDRC_GEN3
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_MPC85xx_CONFIG_H_ */
|
||||
|
|
|
@ -7,6 +7,8 @@
|
|||
#ifndef _ASM_MPC86xx_CONFIG_H_
|
||||
#define _ASM_MPC86xx_CONFIG_H_
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_86XX
|
||||
|
||||
/* SoC specific defines for Freescale MPC86xx processors */
|
||||
|
||||
#if defined(CONFIG_MPC8610)
|
||||
|
|
|
@ -62,6 +62,8 @@ enum srds_prtcl {
|
|||
QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
|
||||
QSGMII_FM2_A,
|
||||
QSGMII_FM2_B,
|
||||
XFI_FM1_MAC1,
|
||||
XFI_FM1_MAC2,
|
||||
XFI_FM1_MAC9,
|
||||
XFI_FM1_MAC10,
|
||||
XFI_FM2_MAC9,
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#ifndef __IMMAP_83xx__
|
||||
#define __IMMAP_83xx__
|
||||
|
||||
#include <fsl_immap.h>
|
||||
#include <asm/types.h>
|
||||
#include <asm/fsl_i2c.h>
|
||||
#include <asm/mpc8xxx_spi.h>
|
||||
|
@ -277,107 +278,10 @@ typedef struct qesba83xx {
|
|||
} qesba83xx_t;
|
||||
|
||||
/*
|
||||
* DDR Memory Controller Memory Map
|
||||
* DDR Memory Controller Memory Map for DDR1
|
||||
* The structure of DDR2, or DDR3 is defined in fsl_immap.h
|
||||
*/
|
||||
#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
|
||||
typedef struct ccsr_ddr {
|
||||
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
|
||||
u8 res1[4];
|
||||
u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
|
||||
u8 res2[4];
|
||||
u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
|
||||
u8 res3[4];
|
||||
u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
|
||||
u8 res4[100];
|
||||
u32 cs0_config; /* Chip Select Configuration */
|
||||
u32 cs1_config; /* Chip Select Configuration */
|
||||
u32 cs2_config; /* Chip Select Configuration */
|
||||
u32 cs3_config; /* Chip Select Configuration */
|
||||
u8 res4a[48];
|
||||
u32 cs0_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs1_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs2_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs3_config_2; /* Chip Select Configuration 2 */
|
||||
u8 res5[48];
|
||||
u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
|
||||
u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
|
||||
u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
|
||||
u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
|
||||
u32 sdram_cfg; /* SDRAM Control Configuration */
|
||||
u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
|
||||
u32 sdram_mode; /* SDRAM Mode Configuration */
|
||||
u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
|
||||
u32 sdram_md_cntl; /* SDRAM Mode Control */
|
||||
u32 sdram_interval; /* SDRAM Interval Configuration */
|
||||
u32 sdram_data_init; /* SDRAM Data initialization */
|
||||
u8 res6[4];
|
||||
u32 sdram_clk_cntl; /* SDRAM Clock Control */
|
||||
u8 res7[20];
|
||||
u32 init_addr; /* training init addr */
|
||||
u32 init_ext_addr; /* training init extended addr */
|
||||
u8 res8_1[16];
|
||||
u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
|
||||
u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
|
||||
u8 reg8_1a[8];
|
||||
u32 ddr_zq_cntl; /* ZQ calibration control*/
|
||||
u32 ddr_wrlvl_cntl; /* write leveling control*/
|
||||
u8 reg8_1aa[4];
|
||||
u32 ddr_sr_cntr; /* self refresh counter */
|
||||
u32 ddr_sdram_rcw_1; /* Control Words 1 */
|
||||
u32 ddr_sdram_rcw_2; /* Control Words 2 */
|
||||
u8 reg_1ab[8];
|
||||
u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
|
||||
u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
|
||||
u8 res8_1b[104];
|
||||
u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
|
||||
u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
|
||||
u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
|
||||
u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
|
||||
u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
|
||||
u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
|
||||
u8 res8_1ba[0x908];
|
||||
u32 ddr_dsr1; /* Debug Status 1 */
|
||||
u32 ddr_dsr2; /* Debug Status 2 */
|
||||
u32 ddr_cdr1; /* Control Driver 1 */
|
||||
u32 ddr_cdr2; /* Control Driver 2 */
|
||||
u8 res8_1c[200];
|
||||
u32 ip_rev1; /* IP Block Revision 1 */
|
||||
u32 ip_rev2; /* IP Block Revision 2 */
|
||||
u32 eor; /* Enhanced Optimization Register */
|
||||
u8 res8_2[252];
|
||||
u32 mtcr; /* Memory Test Control Register */
|
||||
u8 res8_3[28];
|
||||
u32 mtp1; /* Memory Test Pattern 1 */
|
||||
u32 mtp2; /* Memory Test Pattern 2 */
|
||||
u32 mtp3; /* Memory Test Pattern 3 */
|
||||
u32 mtp4; /* Memory Test Pattern 4 */
|
||||
u32 mtp5; /* Memory Test Pattern 5 */
|
||||
u32 mtp6; /* Memory Test Pattern 6 */
|
||||
u32 mtp7; /* Memory Test Pattern 7 */
|
||||
u32 mtp8; /* Memory Test Pattern 8 */
|
||||
u32 mtp9; /* Memory Test Pattern 9 */
|
||||
u32 mtp10; /* Memory Test Pattern 10 */
|
||||
u8 res8_4[184];
|
||||
u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
|
||||
u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
|
||||
u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
|
||||
u8 res9[20];
|
||||
u32 capture_data_hi; /* Data Path Read Capture High */
|
||||
u32 capture_data_lo; /* Data Path Read Capture Low */
|
||||
u32 capture_ecc; /* Data Path Read Capture ECC */
|
||||
u8 res10[20];
|
||||
u32 err_detect; /* Error Detect */
|
||||
u32 err_disable; /* Error Disable */
|
||||
u32 err_int_en;
|
||||
u32 capture_attributes; /* Error Attrs Capture */
|
||||
u32 capture_address; /* Error Addr Capture */
|
||||
u32 capture_ext_address; /* Error Extended Addr Capture */
|
||||
u32 err_sbe; /* Single-Bit ECC Error Management */
|
||||
u8 res11[164];
|
||||
u32 debug[32]; /* debug_1 to debug_32 */
|
||||
u8 res12[128];
|
||||
} ccsr_ddr_t;
|
||||
#else
|
||||
#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
|
||||
typedef struct ddr_cs_bnds {
|
||||
u32 csbnds;
|
||||
u8 res0[4];
|
||||
|
@ -739,8 +643,8 @@ typedef struct immap {
|
|||
u8 dll_ddr[0x100];
|
||||
u8 dll_lbc[0x100];
|
||||
u8 res1[0xE00];
|
||||
#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
|
||||
ccsr_ddr_t ddr; /* DDR Memory Controller Memory */
|
||||
#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
|
||||
struct ccsr_ddr ddr; /* DDR Memory Controller Memory */
|
||||
#else
|
||||
ddr83xx_t ddr; /* DDR Memory Controller Memory */
|
||||
#endif
|
||||
|
@ -763,6 +667,7 @@ typedef struct immap {
|
|||
u8 res7[0xC0000];
|
||||
} immap_t;
|
||||
|
||||
#ifndef CONFIG_MPC834x
|
||||
#ifdef CONFIG_HAS_FSL_MPH_USB
|
||||
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */
|
||||
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0
|
||||
|
@ -770,6 +675,10 @@ typedef struct immap {
|
|||
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0
|
||||
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000
|
||||
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_MPC8313)
|
||||
typedef struct immap {
|
||||
|
@ -1024,7 +933,7 @@ typedef struct immap {
|
|||
#endif
|
||||
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
|
||||
#define CONFIG_SYS_MPC83xx_DMA_ADDR \
|
||||
|
|
|
@ -15,9 +15,10 @@
|
|||
#include <asm/types.h>
|
||||
#include <asm/fsl_dma.h>
|
||||
#include <asm/fsl_i2c.h>
|
||||
#include <asm/fsl_ifc.h>
|
||||
#include <fsl_ifc.h>
|
||||
#include <asm/fsl_lbc.h>
|
||||
#include <asm/fsl_fman.h>
|
||||
#include <fsl_immap.h>
|
||||
|
||||
typedef struct ccsr_local {
|
||||
u32 ccsrbarh; /* CCSR Base Addr High */
|
||||
|
@ -112,105 +113,6 @@ typedef struct ccsr_local_ecm {
|
|||
u8 res24[492];
|
||||
} ccsr_local_ecm_t;
|
||||
|
||||
/* DDR memory controller registers */
|
||||
typedef struct ccsr_ddr {
|
||||
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
|
||||
u8 res1[4];
|
||||
u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
|
||||
u8 res2[4];
|
||||
u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
|
||||
u8 res3[4];
|
||||
u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
|
||||
u8 res4[100];
|
||||
u32 cs0_config; /* Chip Select Configuration */
|
||||
u32 cs1_config; /* Chip Select Configuration */
|
||||
u32 cs2_config; /* Chip Select Configuration */
|
||||
u32 cs3_config; /* Chip Select Configuration */
|
||||
u8 res4a[48];
|
||||
u32 cs0_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs1_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs2_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs3_config_2; /* Chip Select Configuration 2 */
|
||||
u8 res5[48];
|
||||
u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
|
||||
u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
|
||||
u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
|
||||
u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
|
||||
u32 sdram_cfg; /* SDRAM Control Configuration */
|
||||
u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
|
||||
u32 sdram_mode; /* SDRAM Mode Configuration */
|
||||
u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
|
||||
u32 sdram_md_cntl; /* SDRAM Mode Control */
|
||||
u32 sdram_interval; /* SDRAM Interval Configuration */
|
||||
u32 sdram_data_init; /* SDRAM Data initialization */
|
||||
u8 res6[4];
|
||||
u32 sdram_clk_cntl; /* SDRAM Clock Control */
|
||||
u8 res7[20];
|
||||
u32 init_addr; /* training init addr */
|
||||
u32 init_ext_addr; /* training init extended addr */
|
||||
u8 res8_1[16];
|
||||
u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
|
||||
u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
|
||||
u8 reg8_1a[8];
|
||||
u32 ddr_zq_cntl; /* ZQ calibration control*/
|
||||
u32 ddr_wrlvl_cntl; /* write leveling control*/
|
||||
u8 reg8_1aa[4];
|
||||
u32 ddr_sr_cntr; /* self refresh counter */
|
||||
u32 ddr_sdram_rcw_1; /* Control Words 1 */
|
||||
u32 ddr_sdram_rcw_2; /* Control Words 2 */
|
||||
u8 reg_1ab[8];
|
||||
u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
|
||||
u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
|
||||
u8 res8_1b[104];
|
||||
u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
|
||||
u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
|
||||
u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
|
||||
u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
|
||||
u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
|
||||
u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
|
||||
u8 res8_1ba[0x908];
|
||||
u32 ddr_dsr1; /* Debug Status 1 */
|
||||
u32 ddr_dsr2; /* Debug Status 2 */
|
||||
u32 ddr_cdr1; /* Control Driver 1 */
|
||||
u32 ddr_cdr2; /* Control Driver 2 */
|
||||
u8 res8_1c[200];
|
||||
u32 ip_rev1; /* IP Block Revision 1 */
|
||||
u32 ip_rev2; /* IP Block Revision 2 */
|
||||
u32 eor; /* Enhanced Optimization Register */
|
||||
u8 res8_2[252];
|
||||
u32 mtcr; /* Memory Test Control Register */
|
||||
u8 res8_3[28];
|
||||
u32 mtp1; /* Memory Test Pattern 1 */
|
||||
u32 mtp2; /* Memory Test Pattern 2 */
|
||||
u32 mtp3; /* Memory Test Pattern 3 */
|
||||
u32 mtp4; /* Memory Test Pattern 4 */
|
||||
u32 mtp5; /* Memory Test Pattern 5 */
|
||||
u32 mtp6; /* Memory Test Pattern 6 */
|
||||
u32 mtp7; /* Memory Test Pattern 7 */
|
||||
u32 mtp8; /* Memory Test Pattern 8 */
|
||||
u32 mtp9; /* Memory Test Pattern 9 */
|
||||
u32 mtp10; /* Memory Test Pattern 10 */
|
||||
u8 res8_4[184];
|
||||
u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
|
||||
u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
|
||||
u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
|
||||
u8 res9[20];
|
||||
u32 capture_data_hi; /* Data Path Read Capture High */
|
||||
u32 capture_data_lo; /* Data Path Read Capture Low */
|
||||
u32 capture_ecc; /* Data Path Read Capture ECC */
|
||||
u8 res10[20];
|
||||
u32 err_detect; /* Error Detect */
|
||||
u32 err_disable; /* Error Disable */
|
||||
u32 err_int_en;
|
||||
u32 capture_attributes; /* Error Attrs Capture */
|
||||
u32 capture_address; /* Error Addr Capture */
|
||||
u32 capture_ext_address; /* Error Extended Addr Capture */
|
||||
u32 err_sbe; /* Single-Bit ECC Error Management */
|
||||
u8 res11[164];
|
||||
u32 debug[32]; /* debug_1 to debug_32 */
|
||||
u8 res12[128];
|
||||
} ccsr_ddr_t;
|
||||
|
||||
#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
|
||||
#define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
|
||||
|
||||
|
@ -282,7 +184,9 @@ typedef struct ccsr_pcix {
|
|||
u32 int_ack; /* PCIX IRQ Acknowledge */
|
||||
u8 res000c[52];
|
||||
u32 liodn_base; /* PCIX LIODN base register */
|
||||
u8 res0044[3004];
|
||||
u8 res0044[2996];
|
||||
u32 ipver1; /* PCIX IP block revision register 1 */
|
||||
u32 ipver2; /* PCIX IP block revision register 2 */
|
||||
u32 potar0; /* PCIX Outbound Transaction Addr 0 */
|
||||
u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
|
||||
u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
|
||||
|
@ -1717,6 +1621,8 @@ typedef struct ccsr_gur {
|
|||
#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
|
||||
#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
|
||||
#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
|
||||
#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
|
||||
#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
|
||||
#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
|
||||
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
|
||||
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
|
||||
|
@ -1847,11 +1753,18 @@ typedef struct ccsr_gur {
|
|||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
|
||||
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
|
||||
#elif defined(CONFIG_PPC_T1040)
|
||||
#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
|
||||
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
|
||||
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
|
||||
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
|
||||
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
|
||||
#endif
|
||||
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
|
||||
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
|
||||
|
@ -1914,6 +1827,15 @@ typedef struct ccsr_gur {
|
|||
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
|
||||
#endif
|
||||
#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
|
||||
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
|
||||
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
|
||||
#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
|
||||
#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
|
||||
#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
|
||||
#endif
|
||||
u8 res18[192];
|
||||
u32 scratchrw[4]; /* Scratch Read/Write */
|
||||
|
@ -2911,6 +2833,7 @@ struct ccsr_pman {
|
|||
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
|
||||
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
|
||||
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
|
||||
#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
|
||||
#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
|
||||
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
|
||||
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
|
||||
|
@ -3045,11 +2968,11 @@ struct ccsr_pman {
|
|||
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
|
||||
#define CONFIG_SYS_MPC85xx_ECM_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
|
||||
#define CONFIG_SYS_FSL_DDR3_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
|
||||
#define CONFIG_SYS_LBC_ADDR \
|
||||
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
#ifndef __IMMAP_86xx__
|
||||
#define __IMMAP_86xx__
|
||||
|
||||
#include <fsl_immap.h>
|
||||
#include <asm/types.h>
|
||||
#include <asm/fsl_dma.h>
|
||||
#include <asm/fsl_lbc.h>
|
||||
|
@ -89,75 +90,6 @@ typedef struct ccsr_local_mcm {
|
|||
char res31[488];
|
||||
} ccsr_local_mcm_t;
|
||||
|
||||
/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */
|
||||
|
||||
typedef struct ccsr_ddr {
|
||||
uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
|
||||
char res1[4];
|
||||
uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
|
||||
char res2[4];
|
||||
uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
|
||||
char res3[4];
|
||||
uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
|
||||
char res4[4];
|
||||
uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */
|
||||
char res5[4];
|
||||
uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */
|
||||
char res6[84];
|
||||
uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
|
||||
uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
|
||||
uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
|
||||
uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
|
||||
uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */
|
||||
uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */
|
||||
char res7[104];
|
||||
uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
|
||||
uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
|
||||
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
|
||||
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
|
||||
uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */
|
||||
uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
|
||||
uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */
|
||||
uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */
|
||||
uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */
|
||||
uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
|
||||
uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */
|
||||
char res8[4];
|
||||
uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
|
||||
char res9[12];
|
||||
uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */
|
||||
uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */
|
||||
uint init_addr; /* 0x2148 - DDR training initialzation address */
|
||||
uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */
|
||||
char res10[2728];
|
||||
uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
|
||||
uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
|
||||
char res11[512];
|
||||
uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
|
||||
uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
|
||||
uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
|
||||
char res12[20];
|
||||
uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
|
||||
uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
|
||||
uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
|
||||
char res13[20];
|
||||
uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
|
||||
uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
|
||||
uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */
|
||||
uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
|
||||
uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
|
||||
uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
|
||||
uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
|
||||
char res14[164];
|
||||
uint debug_1; /* 0x2f00 */
|
||||
uint debug_2;
|
||||
uint debug_3;
|
||||
uint debug_4;
|
||||
uint debug_5;
|
||||
char res15[236];
|
||||
} ccsr_ddr_t;
|
||||
|
||||
|
||||
/* Daul I2C Registers(0x3000-0x4000) */
|
||||
typedef struct ccsr_i2c {
|
||||
struct fsl_i2c i2c[2];
|
||||
|
@ -1225,11 +1157,11 @@ typedef struct ccsr_wdt {
|
|||
|
||||
typedef struct immap {
|
||||
ccsr_local_mcm_t im_local_mcm;
|
||||
ccsr_ddr_t im_ddr1;
|
||||
struct ccsr_ddr im_ddr1;
|
||||
ccsr_i2c_t im_i2c;
|
||||
ccsr_duart_t im_duart;
|
||||
fsl_lbc_t im_lbc;
|
||||
ccsr_ddr_t im_ddr2;
|
||||
struct ccsr_ddr im_ddr2;
|
||||
char res1[4096];
|
||||
ccsr_pex_t im_pex1;
|
||||
ccsr_pex_t im_pex2;
|
||||
|
@ -1253,9 +1185,9 @@ typedef struct immap {
|
|||
extern immap_t *immr;
|
||||
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
|
||||
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
|
||||
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
|
||||
#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
|
||||
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
|
||||
#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
static inline void mpc85xx_gpio_set(unsigned int mask,
|
||||
unsigned int dir, unsigned int val)
|
||||
{
|
||||
ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
|
||||
ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
|
||||
|
||||
/* First mask off the unwanted parts of "dir" and "val" */
|
||||
dir &= mask;
|
||||
|
@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
|
|||
|
||||
static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
|
||||
{
|
||||
ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00);
|
||||
ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
|
||||
|
||||
/* Read the requested values */
|
||||
return in_be32(&gpio->gpdat) & mask;
|
||||
|
|
|
@ -1127,6 +1127,8 @@
|
|||
#define SVR_T1020 0x852100
|
||||
#define SVR_T1021 0x852101
|
||||
#define SVR_T1022 0x852102
|
||||
#define SVR_T2080 0x853000
|
||||
#define SVR_T2081 0x853100
|
||||
|
||||
#define SVR_8610 0x80A000
|
||||
#define SVR_8641 0x809000
|
||||
|
|
|
@ -10,5 +10,7 @@
|
|||
obj-y := cpu.o os.o start.o state.o
|
||||
|
||||
# os.c is build in the system environment, so needs standard includes
|
||||
$(obj)os.o: ALL_CFLAGS := $(filter-out -nostdinc,$(ALL_CFLAGS))
|
||||
$(obj).depend.os: CPPFLAGS := $(filter-out -nostdinc,$(CPPFLAGS))
|
||||
$(obj)os.o: ALL_CFLAGS := $(BASE_CPPFLAGS) \
|
||||
$(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS))
|
||||
$(obj).depend.os: CPPFLAGS := $(BASE_CPPFLAGS) \
|
||||
$(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS))
|
||||
|
|
|
@ -8,6 +8,7 @@
|
|||
#include <fcntl.h>
|
||||
#include <getopt.h>
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <termios.h>
|
||||
|
@ -136,7 +137,7 @@ void os_usleep(unsigned long usec)
|
|||
usleep(usec);
|
||||
}
|
||||
|
||||
u64 __attribute__((no_instrument_function)) os_get_nsec(void)
|
||||
uint64_t __attribute__((no_instrument_function)) os_get_nsec(void)
|
||||
{
|
||||
#if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK)
|
||||
struct timespec tp;
|
||||
|
|
|
@ -38,6 +38,6 @@ static inline void unmap_sysmem(const void *vaddr)
|
|||
}
|
||||
|
||||
/* Map from a pointer to our RAM buffer */
|
||||
phys_addr_t map_to_sysmem(void *ptr);
|
||||
phys_addr_t map_to_sysmem(const void *ptr);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -48,8 +48,8 @@ typedef unsigned long long u64;
|
|||
#define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG
|
||||
|
||||
typedef unsigned long dma_addr_t;
|
||||
typedef unsigned long phys_addr_t;
|
||||
typedef unsigned long phys_size_t;
|
||||
typedef u32 phys_addr_t;
|
||||
typedef u32 phys_size_t;
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
|
|
|
@ -1,33 +1,41 @@
|
|||
/* This is where the SPARC/LEON3 starts
|
||||
* Copyright (C) 2007,
|
||||
* Daniel Hellstrom, daniel@gaisler.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm-offsets.h>
|
||||
#include <config.h>
|
||||
#include <asm/asmmacro.h>
|
||||
#include <asm/winmacro.h>
|
||||
#include <asm/psr.h>
|
||||
#include <asm/stack.h>
|
||||
#include <asm/leon.h>
|
||||
#include <version.h>
|
||||
|
||||
TRAP ta 0; nop; nop; nop;
|
||||
/* Entry for traps which jump to a programmer-specified trap handler. */
|
||||
#define TRAPR(H) \
|
||||
wr %g0, 0xfe0, %psr; \
|
||||
mov %g0, %tbr; \
|
||||
ba (H); \
|
||||
mov %g0, %wim;
|
||||
|
||||
/* Software trap. Treat as BAD_TRAP for the time being... */
|
||||
#define SOFT_TRAP TRAP(_hwerr)
|
||||
#define TRAP(H) \
|
||||
mov %psr, %l0; \
|
||||
ba (H); \
|
||||
nop; nop;
|
||||
|
||||
#define PSR_INIT 0x1FC0 /* Disable traps, set s and ps */
|
||||
#define WIM_INIT 2
|
||||
#define TRAPI(ilevel) \
|
||||
mov ilevel, %l7; \
|
||||
mov %psr, %l0; \
|
||||
b _irq_entry; \
|
||||
mov %wim, %l3
|
||||
|
||||
/* All traps low-level code here must end with this macro. */
|
||||
#define RESTORE_ALL b ret_trap_entry; clr %l6;
|
||||
|
||||
#define WRITE_PAUSE nop;nop;nop
|
||||
|
||||
WINDOWSIZE = (16 * 4)
|
||||
ARGPUSHSIZE = (6 * 4)
|
||||
ARGPUSH = (WINDOWSIZE + 4)
|
||||
MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4)
|
||||
|
||||
/* Number of register windows */
|
||||
#ifndef CONFIG_SYS_SPARC_NWINDOWS
|
||||
#error Must define number of SPARC register windows, default is 8
|
||||
#endif
|
||||
|
||||
#define STACK_ALIGN 8
|
||||
#define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1))
|
||||
|
||||
.section ".start", "ax"
|
||||
.globl _starttate */
|
||||
/* Unexcpected trap will halt the processor by forcing it to error state */
|
||||
#undef BAD_TRAP
|
||||
#define BAD_TRAP ta 0; nop; nop; nop;
|
||||
|
||||
|
|
|
@ -30,10 +30,10 @@ SECTIONS
|
|||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
common/libcommon.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
|
||||
board/LEOX/elpt860/libelpt860.o (.text*)
|
||||
arch/powerpc/lib/libpowerpc.o (.text*)
|
||||
common/built-in.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
|
||||
board/LEOX/elpt860/built-in.o (.text*)
|
||||
arch/powerpc/lib/built-in.o (.text*)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o (.text*)
|
||||
|
|
|
@ -9,8 +9,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y := edminiv2.o ../common/common.o
|
||||
|
|
|
@ -9,10 +9,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y := net2big_v2.o ../common/common.o
|
||||
ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
|
||||
obj-y += ../common/cpld-gpio-bus.o
|
||||
|
|
|
@ -9,8 +9,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y := netspace_v2.o ../common/common.o
|
||||
|
|
|
@ -9,8 +9,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y := wireless_space.o ../common/common.o
|
||||
|
|
|
@ -8,10 +8,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y = db64360.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
|
||||
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
|
||||
sdram_init.o ../common/intel_flash.o ../common/misc.o
|
||||
|
|
|
@ -8,10 +8,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y += db64460.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
|
||||
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
|
||||
sdram_init.o ../common/intel_flash.o ../common/misc.o
|
||||
|
|
|
@ -16,10 +16,10 @@ SECTIONS
|
|||
.text : {
|
||||
*(.__image_copy_start)
|
||||
arch/arm/cpu/ixp/start.o(.text*)
|
||||
net/libnet.o(.text*)
|
||||
board/actux1/libactux1.o(.text*)
|
||||
arch/arm/cpu/ixp/libixp.o(.text*)
|
||||
drivers/input/libinput.o(.text*)
|
||||
net/built-in.o(.text*)
|
||||
board/actux1/built-in.o(.text*)
|
||||
arch/arm/cpu/ixp/built-in.o(.text*)
|
||||
drivers/input/built-in.o(.text*)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o(.ppcenv)
|
||||
|
|
|
@ -16,10 +16,10 @@ SECTIONS
|
|||
.text : {
|
||||
*(.__image_copy_start)
|
||||
arch/arm/cpu/ixp/start.o(.text*)
|
||||
net/libnet.o(.text*)
|
||||
board/actux2/libactux2.o(.text*)
|
||||
arch/arm/cpu/ixp/libixp.o(.text*)
|
||||
drivers/input/libinput.o(.text*)
|
||||
net/built-in.o(.text*)
|
||||
board/actux2/built-in.o(.text*)
|
||||
arch/arm/cpu/ixp/built-in.o(.text*)
|
||||
drivers/input/built-in.o(.text*)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o(.ppcenv)
|
||||
|
|
|
@ -16,10 +16,10 @@ SECTIONS
|
|||
.text : {
|
||||
*(.__image_copy_start)
|
||||
arch/arm/cpu/ixp/start.o(.text*)
|
||||
net/libnet.o(.text*)
|
||||
board/actux3/libactux3.o(.text*)
|
||||
arch/arm/cpu/ixp/libixp.o(.text*)
|
||||
drivers/input/libinput.o(.text*)
|
||||
net/built-in.o(.text*)
|
||||
board/actux3/built-in.o(.text*)
|
||||
arch/arm/cpu/ixp/built-in.o(.text*)
|
||||
drivers/input/built-in.o(.text*)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o(.ppcenv)
|
||||
|
|
|
@ -6,10 +6,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y := nios2-generic.o
|
||||
obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
|
||||
obj-$(CONFIG_EPLED) += ../common/epled.o
|
||||
|
|
|
@ -5,11 +5,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
# we get text_base from board config header, so do not use this
|
||||
#CONFIG_SYS_TEXT_BASE = do-not-use-me
|
||||
|
||||
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
|
||||
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
|
|
|
@ -134,7 +134,8 @@ static void sama5d3xek_lcd_hw_init(void)
|
|||
|
||||
void lcd_show_board_info(void)
|
||||
{
|
||||
ulong dram_size, nand_size;
|
||||
ulong dram_size;
|
||||
uint64_t nand_size;
|
||||
int i;
|
||||
char temp[32];
|
||||
|
||||
|
@ -153,7 +154,7 @@ void lcd_show_board_info(void)
|
|||
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
|
||||
nand_size += nand_info[i].size;
|
||||
#endif
|
||||
lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
|
||||
lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
|
||||
dram_size >> 20, nand_size >> 20);
|
||||
}
|
||||
#endif /* CONFIG_LCD_INFO */
|
||||
|
|
|
@ -7,8 +7,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
|
||||
|
||||
obj-y := ../common/tamonten.o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
|
|
@ -7,8 +7,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
|
||||
|
||||
obj-y := ../common/tamonten.o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
|
|
@ -7,8 +7,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
|
||||
|
||||
obj-y := ../common/tamonten.o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
|
|
@ -1,12 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
#
|
||||
# Cogent Modular Architecture
|
||||
#
|
||||
|
||||
PLATFORM_CPPFLAGS += -I$(TOPDIR)
|
|
@ -1,5 +1,5 @@
|
|||
#include <common.h>
|
||||
#include <board/cogent/dipsw.h>
|
||||
#include "dipsw.h"
|
||||
|
||||
unsigned char
|
||||
dipsw_raw(void)
|
||||
|
|
|
@ -6,7 +6,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <board/cogent/flash.h>
|
||||
#include "flash.h"
|
||||
#include <linux/compiler.h>
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
|
|
@ -48,7 +48,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <stdarg.h>
|
||||
#include <board/cogent/lcd.h>
|
||||
#include "lcd.h"
|
||||
|
||||
static char lines[2][LCD_LINE_LENGTH+1];
|
||||
static int curline;
|
||||
|
|
|
@ -6,11 +6,11 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <board/cogent/dipsw.h>
|
||||
#include <board/cogent/lcd.h>
|
||||
#include <board/cogent/rtc.h>
|
||||
#include <board/cogent/par.h>
|
||||
#include <board/cogent/pci.h>
|
||||
#include "dipsw.h"
|
||||
#include "lcd.h"
|
||||
#include "rtc.h"
|
||||
#include "par.h"
|
||||
#include "pci.h"
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
|
|
@ -4,7 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <board/cogent/serial.h>
|
||||
#include "serial.h"
|
||||
#include <serial.h>
|
||||
#include <linux/compiler.h>
|
||||
|
||||
|
|
|
@ -14,8 +14,6 @@
|
|||
# more details.
|
||||
#
|
||||
|
||||
$(shell mkdir -p $(obj)../../nvidia/common)
|
||||
|
||||
obj-y := paz00.o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
|
|
@ -19,7 +19,7 @@ SECTIONS
|
|||
{
|
||||
*(.__image_copy_start)
|
||||
CPUDIR/start.o (.text*)
|
||||
board/compulab/cm_t335/libcm_t335.o (.text*)
|
||||
board/compulab/cm_t335/built-in.o (.text*)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
|
|
|
@ -268,6 +268,9 @@ static void cm_t3x_set_common_muxconf(void)
|
|||
/* DVI enable */
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
|
||||
|
||||
/* DataImage backlight */
|
||||
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
|
||||
|
||||
/* CM-T3x Ethernet */
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
|
||||
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
|
||||
|
@ -374,6 +377,15 @@ static void cm_t3x_set_common_muxconf(void)
|
|||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
|
||||
|
||||
/* SPI */
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
|
||||
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
|
||||
|
||||
/* display controls */
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
|
||||
}
|
||||
|
||||
static void cm_t35_set_muxconf(void)
|
||||
|
@ -470,7 +482,7 @@ static void setup_net_chip_gmpc(void)
|
|||
&ctrl_base->gpmc_nadv_ale);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
||||
#ifdef CONFIG_SYS_I2C_OMAP34XX
|
||||
/*
|
||||
* Routine: reset_net_chip
|
||||
* Description: reset the Ethernet controller via TPS65930 GPIO
|
||||
|
|
|
@ -6,5 +6,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
|
||||
obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o
|
||||
obj-$(CONFIG_LCD) += omap3_display.o
|
||||
|
|
|
@ -10,7 +10,7 @@
|
|||
#ifndef _EEPROM_
|
||||
#define _EEPROM_
|
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
|
||||
#ifdef CONFIG_SYS_I2C_OMAP34XX
|
||||
int cl_eeprom_read_mac_addr(uchar *buf);
|
||||
u32 cl_eeprom_get_board_rev(void);
|
||||
#else
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <stdio_dev.h>
|
||||
#include <asm/arch/dss.h>
|
||||
#include <lcd.h>
|
||||
#include <scf0403_lcd.h>
|
||||
#include <asm/arch-omap3/dss.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
@ -22,6 +23,7 @@ enum display_type {
|
|||
NONE,
|
||||
DVI,
|
||||
DVI_CUSTOM,
|
||||
DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
|
||||
};
|
||||
|
||||
#define CMAP_ADDR 0x80100000
|
||||
|
@ -119,6 +121,18 @@ static const struct panel_config preset_dvi_1280X1024 = {
|
|||
.gfx_format = GFXFORMAT_RGB16,
|
||||
};
|
||||
|
||||
static const struct panel_config preset_dataimage_480X800 = {
|
||||
.lcd_size = PANEL_LCD_SIZE(480, 800),
|
||||
.timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2),
|
||||
.timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3),
|
||||
.pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF,
|
||||
.divisor = 10 | (1 << 10),
|
||||
.data_lines = LCD_INTERFACE_18_BIT,
|
||||
.panel_type = ACTIVE_DISPLAY,
|
||||
.load_mode = 2,
|
||||
.gfx_format = GFXFORMAT_RGB16,
|
||||
};
|
||||
|
||||
/*
|
||||
* set_resolution_params()
|
||||
*
|
||||
|
@ -146,6 +160,13 @@ static enum display_type set_dvi_preset(const struct panel_config preset,
|
|||
return DVI;
|
||||
}
|
||||
|
||||
static enum display_type set_dataimage_preset(const struct panel_config preset,
|
||||
int x_res, int y_res)
|
||||
{
|
||||
set_preset(preset, x_res, y_res);
|
||||
return DATA_IMAGE;
|
||||
}
|
||||
|
||||
/*
|
||||
* parse_mode() - parse the mode parameter of custom lcd settings
|
||||
*
|
||||
|
@ -369,6 +390,8 @@ static enum display_type env_parse_displaytype(char *displaytype)
|
|||
return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
|
||||
else if (!strncmp(displaytype, "dvi1280x1024", 12))
|
||||
return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
|
||||
else if (!strncmp(displaytype, "dataimage480x800", 16))
|
||||
return set_dataimage_preset(preset_dataimage_480X800, 480, 800);
|
||||
|
||||
return NONE;
|
||||
}
|
||||
|
@ -401,12 +424,31 @@ void lcd_ctrl_init(void *lcdbase)
|
|||
clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SCF0403_LCD
|
||||
static void scf0403_enable(void)
|
||||
{
|
||||
gpio_direction_output(58, 1);
|
||||
scf0403_init(157);
|
||||
}
|
||||
#else
|
||||
static inline void scf0403_enable(void) {}
|
||||
#endif
|
||||
|
||||
void lcd_enable(void)
|
||||
{
|
||||
if (lcd_def == DVI || lcd_def == DVI_CUSTOM) {
|
||||
switch (lcd_def) {
|
||||
case NONE:
|
||||
return;
|
||||
case DVI:
|
||||
case DVI_CUSTOM:
|
||||
gpio_direction_output(54, 0); /* Turn on DVI */
|
||||
omap3_dss_enable();
|
||||
break;
|
||||
case DATA_IMAGE:
|
||||
scf0403_enable();
|
||||
break;
|
||||
}
|
||||
|
||||
omap3_dss_enable();
|
||||
}
|
||||
|
||||
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
|
||||
|
|
|
@ -5,8 +5,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
$(shell mkdir -p $(obj)../../nvidia/common)
|
||||
|
||||
obj-y := trimslice.o
|
||||
|
||||
include ../../nvidia/common/common.mk
|
||||
|
|
|
@ -19,8 +19,8 @@ SECTIONS
|
|||
.text :
|
||||
{
|
||||
arch/arm/cpu/arm926ejs/start.o (.text*)
|
||||
arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*)
|
||||
drivers/mtd/nand/libnand.o (.text*)
|
||||
arch/arm/cpu/arm926ejs/davinci/built-in.o (.text*)
|
||||
drivers/mtd/nand/built-in.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
|
|
|
@ -16,10 +16,10 @@ SECTIONS
|
|||
.text : {
|
||||
*(.__image_copy_start)
|
||||
arch/arm/cpu/ixp/start.o(.text*)
|
||||
net/libnet.o(.text*)
|
||||
board/dvlhost/libdvlhost.o(.text*)
|
||||
arch/arm/cpu/ixp/libixp.o(.text*)
|
||||
drivers/serial/libserial.o(.text*)
|
||||
net/built-in.o(.text*)
|
||||
board/dvlhost/built-in.o(.text*)
|
||||
arch/arm/cpu/ixp/built-in.o(.text*)
|
||||
drivers/serial/built-in.o(.text*)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o(.ppcenv)
|
||||
|
|
|
@ -5,8 +5,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y := top5200.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
|
||||
|
|
|
@ -5,7 +5,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
obj-y = top860.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
|
||||
|
|
|
@ -5,8 +5,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y = adciop.o flash.o ../common/misc.o ../common/pci.o
|
||||
|
|
|
@ -5,10 +5,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y = apc405.o \
|
||||
../common/misc.o \
|
||||
../common/auto_update.o
|
||||
|
|
|
@ -5,8 +5,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
obj-y = ar405.o flash.o ../common/misc.o
|
||||
|
|
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Add table
Reference in a new issue