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clk: stm32mp1: Add VREF clock gating
Add VREF clock gating, that may be used by STM32 VREFBUF regulator. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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@ -100,6 +100,7 @@
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#define RCC_USBCKSELR 0x91C
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#define RCC_MP_APB1ENSETR 0xA00
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#define RCC_MP_APB2ENSETR 0XA08
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#define RCC_MP_APB3ENSETR 0xA10
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#define RCC_MP_AHB2ENSETR 0xA18
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#define RCC_MP_AHB4ENSETR 0xA28
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@ -508,6 +509,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
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STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
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STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
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STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
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STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
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STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
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