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SPEAr: Correct SoC ID offset in misc configuration space
SoC Core ID offset is 0x30 in miscellaneous configuration address space. It was wrongly mentioned as periph2 clk enable. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
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@ -37,7 +37,7 @@ struct misc_regs {
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u32 amba_clk_cfg; /* 0x24 */
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u32 amba_clk_cfg; /* 0x24 */
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u32 periph_clk_cfg; /* 0x28 */
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u32 periph_clk_cfg; /* 0x28 */
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u32 periph1_clken; /* 0x2C */
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u32 periph1_clken; /* 0x2C */
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u32 periph2_clken; /* 0x30 */
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u32 soc_core_id; /* 0x30 */
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u32 ras_clken; /* 0x34 */
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u32 ras_clken; /* 0x34 */
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u32 periph1_rst; /* 0x38 */
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u32 periph1_rst; /* 0x38 */
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u32 periph2_rst; /* 0x3C */
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u32 periph2_rst; /* 0x3C */
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