From 93557bd260506c9965ad592d05b610268ab59a3f Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 6 May 2019 11:21:12 +0800 Subject: [PATCH 01/50] rockchip: add common header boot0.h and gpio.h for soc boot0.h and gpio.h will be used by system and include by 'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'. Signed-off-by: Kever Yang Reviewed-by: Tom Rini --- arch/arm/include/asm/arch-rk3036/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3036/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3128/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3128/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3188/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3188/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk322x/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk322x/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3288/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3288/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3328/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3328/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3368/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3368/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3399/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rk3399/gpio.h | 11 +++++++++++ arch/arm/include/asm/arch-rv1108/boot0.h | 11 +++++++++++ arch/arm/include/asm/arch-rv1108/gpio.h | 11 +++++++++++ 18 files changed, 198 insertions(+) create mode 100644 arch/arm/include/asm/arch-rk3036/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3036/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3128/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3128/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3188/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3188/gpio.h create mode 100644 arch/arm/include/asm/arch-rk322x/boot0.h create mode 100644 arch/arm/include/asm/arch-rk322x/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3288/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3288/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3328/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3328/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3368/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3368/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3399/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3399/gpio.h create mode 100644 arch/arm/include/asm/arch-rv1108/boot0.h create mode 100644 arch/arm/include/asm/arch-rv1108/gpio.h diff --git a/arch/arm/include/asm/arch-rk3036/boot0.h b/arch/arm/include/asm/arch-rk3036/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3036/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3036/gpio.h b/arch/arm/include/asm/arch-rk3036/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3036/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3128/boot0.h b/arch/arm/include/asm/arch-rk3128/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3128/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3128/gpio.h b/arch/arm/include/asm/arch-rk3128/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3128/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3188/boot0.h b/arch/arm/include/asm/arch-rk3188/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3188/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3188/gpio.h b/arch/arm/include/asm/arch-rk3188/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3188/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk322x/boot0.h b/arch/arm/include/asm/arch-rk322x/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk322x/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk322x/gpio.h b/arch/arm/include/asm/arch-rk322x/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk322x/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3288/boot0.h b/arch/arm/include/asm/arch-rk3288/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3288/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3288/gpio.h b/arch/arm/include/asm/arch-rk3288/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3288/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3328/boot0.h b/arch/arm/include/asm/arch-rk3328/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3328/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3328/gpio.h b/arch/arm/include/asm/arch-rk3328/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3328/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3368/boot0.h b/arch/arm/include/asm/arch-rk3368/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3368/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3368/gpio.h b/arch/arm/include/asm/arch-rk3368/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3368/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3399/boot0.h b/arch/arm/include/asm/arch-rk3399/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rk3399/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3399/gpio.h b/arch/arm/include/asm/arch-rk3399/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3399/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rv1108/boot0.h b/arch/arm/include/asm/arch-rv1108/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rv1108/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rv1108/gpio.h b/arch/arm/include/asm/arch-rv1108/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rv1108/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif From dc23c27aa5ac7672bc8206e0f46e9aceab1f0bb7 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 6 May 2019 11:21:13 +0800 Subject: [PATCH 02/50] arm: remove ARCH_ROCKCHIP macro in common code This is fix to: e2a12f590d rockchip: use 'arch-rockchip' as header file path The V2 of origin patch set has fix this, but we merge V1 by mistake, so lets correct it. Signed-off-by: Kever Yang --- arch/arm/cpu/armv8/start.S | 4 ---- arch/arm/lib/vectors.S | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index ecee9e37a5..fe52166e28 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -26,11 +26,7 @@ _start: * order to boot, allow them to set that in their boot0.h file and then * use it here. */ -#ifdef CONFIG_ARCH_ROCKCHIP -#include -#else #include -#endif #else b reset #endif diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 20f485142e..56f3681558 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -67,11 +67,7 @@ * (1) defines '_start:' as appropriate * (2) inserts the vector table using ARM_VECTORS as appropriate */ -#ifdef CONFIG_ARCH_ROCKCHIP -#include -#else #include -#endif #else /* From 2f52378736fe67eac5dd05548f3f473be70895d6 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:19 +0800 Subject: [PATCH 03/50] Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL" This reverts commit f338cca1d2bce906b049722d2fdbf527a4963b61. Signed-off-by: Kever Yang --- drivers/ram/rockchip/sdram_rk322x.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index c596523d4f..e96ac54c39 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -49,7 +49,7 @@ struct rk322x_sdram_params { struct regmap *map; }; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_TPL_BUILD /* * [7:6] bank(n:n bit bank) * [5:4] row(13+n) @@ -750,7 +750,7 @@ static int rk322x_dmc_ofdata_to_platdata(struct udevice *dev) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_TPL_BUILD */ #if CONFIG_IS_ENABLED(OF_PLATDATA) static int conv_of_platdata(struct udevice *dev) @@ -778,7 +778,7 @@ static int conv_of_platdata(struct udevice *dev) static int rk322x_dmc_probe(struct udevice *dev) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_TPL_BUILD struct rk322x_sdram_params *plat = dev_get_platdata(dev); int ret; struct udevice *dev_clk; @@ -786,7 +786,7 @@ static int rk322x_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_TPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = conv_of_platdata(dev); if (ret) @@ -842,12 +842,12 @@ U_BOOT_DRIVER(dmc_rk322x) = { .id = UCLASS_RAM, .of_match = rk322x_dmc_ids, .ops = &rk322x_dmc_ops, -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_TPL_BUILD .ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata, #endif .probe = rk322x_dmc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_TPL_BUILD .platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params), #endif }; From 1e32c5194fabebd6f1b4742e56b1660c9d9b1a57 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:20 +0800 Subject: [PATCH 04/50] arm: add option for TPL support in arm 32bit Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm. Signed-off-by: Kever Yang --- arch/arm/Kconfig | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f91c590f6d..a3d67e43f0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -338,6 +338,17 @@ config SPL_SYS_THUMB_BUILD density. For ARM architectures that support Thumb2 this flag will result in Thumb2 code generated by GCC. +config TPL_SYS_THUMB_BUILD + bool "Build TPL using the Thumb instruction set" + default y if SYS_THUMB_BUILD + depends on TPL && !ARM64 + help + Use this flag to build SPL using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. + + config SYS_L2CACHE_OFF bool "L2cache off" help @@ -373,6 +384,15 @@ config SPL_USE_ARCH_MEMCPY Such implementation may be faster under some conditions but may increase the binary size. +config TPL_USE_ARCH_MEMCPY + bool "Use an assembly optimized implementation of memcpy for TPL" + default y if USE_ARCH_MEMCPY + depends on !ARM64 + help + Enable the generation of an optimized version of memcpy. + Such implementation may be faster under some conditions + but may increase the binary size. + config USE_ARCH_MEMSET bool "Use an assembly optimized implementation of memset" default y @@ -391,6 +411,15 @@ config SPL_USE_ARCH_MEMSET Such implementation may be faster under some conditions but may increase the binary size. +config TPL_USE_ARCH_MEMSET + bool "Use an assembly optimized implementation of memset for TPL" + default y if USE_ARCH_MEMSET + depends on !ARM64 + help + Enable the generation of an optimized version of memset. + Such implementation may be faster under some conditions + but may increase the binary size. + config ARM64_SUPPORT_AARCH32 bool "ARM64 system support AArch32 execution state" default y if ARM64 && !TARGET_THUNDERX_88XX From a0a0d04f3218507aaa29b4fdd45f37d819fb0a32 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:21 +0800 Subject: [PATCH 05/50] arm: add a separate stack for TPL TPL stack may different from SPL and sys stack, add support for separate one when the board defines it. Signed-off-by: Kever Yang --- arch/arm/lib/crt0.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index fe312db690..30fba20e1b 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -67,7 +67,9 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) + ldr r0, =(CONFIG_TPL_STACK) +#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) From e4d0d61275ac1b14375be8f62585398e05b19f3f Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:22 +0800 Subject: [PATCH 06/50] rockchip: rk322x: add CLK_EMMC_SAMPLE clock support Signed-off-by: Kever Yang --- drivers/clk/rockchip/clk_rk322x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 48ed14b2af..4b599fbb24 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -217,6 +217,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, switch (periph) { case HCLK_EMMC: case SCLK_EMMC: + case SCLK_EMMC_SAMPLE: con = readl(&cru->cru_clksel_con[11]); mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; con = readl(&cru->cru_clksel_con[12]); @@ -293,6 +294,7 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, switch (periph) { case HCLK_EMMC: case SCLK_EMMC: + case SCLK_EMMC_SAMPLE: rk_clrsetreg(&cru->cru_clksel_con[11], EMMC_PLL_MASK, mux << EMMC_PLL_SHIFT); From 5793e8c271f73da2ca50fa3d57d3fea7e3d2796c Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:23 +0800 Subject: [PATCH 07/50] rockchip: clk: rk322x: fix assert clock value BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang --- drivers/clk/rockchip/clk_rk322x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4b599fbb24..f09730c91b 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -121,10 +121,10 @@ static void rkclk_init(struct rk322x_cru *cru) assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; - assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); + assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7); hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; - assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); + assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3); rk_clrsetreg(&cru->cru_clksel_con[0], BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, From c34643e0db40bbcfaea8a0df8b6f4d0be7b0f71f Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:24 +0800 Subject: [PATCH 08/50] rockchip: rk322x: add tpl support Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 26 +++++++++++ arch/arm/mach-rockchip/Makefile | 3 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 46 ++++++++------------ arch/arm/mach-rockchip/rk322x-board-tpl.c | 53 +++++++++++++++++++++++ arch/arm/mach-rockchip/u-boot-tpl.lds | 12 +++++ include/configs/rk322x_common.h | 6 +-- 6 files changed, 113 insertions(+), 33 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c create mode 100644 arch/arm/mach-rockchip/u-boot-tpl.lds diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 282d728b82..48e364e127 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -47,14 +47,40 @@ config ROCKCHIP_RK322X bool "Support Rockchip RK3228/RK3229" select CPU_V7A select SUPPORT_SPL + select SUPPORT_TPL select SPL + select SPL_DM + select SPL_OF_LIBFDT + select TPL + select TPL_DM + select TPL_OF_LIBFDT + select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL + select TPL_NEEDS_SEPARATE_STACK if TPL + select SPL_DRIVERS_MISC_SUPPORT + imply SPL_SERIAL_SUPPORT + imply TPL_SERIAL_SUPPORT select ROCKCHIP_BROM_HELPER + select TPL_LIBCOMMON_SUPPORT + select TPL_LIBGENERIC_SUPPORT help The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +if ROCKCHIP_RK322X + +config TPL_TEXT_BASE + default 0x10081000 + +config TPL_MAX_SIZE + default 28672 + +config TPL_STACK + default 0x10088000 + +endif + config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7A diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 368302e1da..fd62a693fe 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -11,10 +11,11 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 888310efbe..c9b41c62c0 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -4,55 +4,43 @@ */ #include -#include #include -#include #include #include -#include #include -#include u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; } +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + #define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { - struct udevice *dev; int ret; -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("SPL Init"); -#endif ret = spl_early_init(); if (ret) { - debug("spl_early_init() failed: %d\n", ret); + printf("spl_early_init() failed: %d\n", ret); hang(); } - - rockchip_timer_init(); - printf("timer init done\n"); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - printf("DRAM init failed: %d\n", ret); - return; - } + preloader_console_init(); /* Disable the ddr secure region setting to make it non-secure */ rk_clrreg(SGRF_DDR_CON0, 0x4000); -#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif } + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c b/arch/arm/mach-rockchip/rk322x-board-tpl.c new file mode 100644 index 0000000000..92d40ee43a --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x-board-tpl.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("TPL Init"); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + printf("timer init done\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } + +#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT) + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +#endif +} diff --git a/arch/arm/mach-rockchip/u-boot-tpl.lds b/arch/arm/mach-rockchip/u-boot-tpl.lds new file mode 100644 index 0000000000..f5a89721ce --- /dev/null +++ b/arch/arm/mach-rockchip/u-boot-tpl.lds @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Rockchip Electronic Co.,Ltd + */ + +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE + +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE + +#include "../cpu/u-boot-spl.lds" diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 3a96748f6b..15bb8d63b8 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -17,9 +17,9 @@ #define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */ #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 -#define CONFIG_SPL_STACK 0x10088000 +#define CONFIG_SYS_INIT_SP_ADDR 0x61100000 +#define CONFIG_SYS_LOAD_ADDR 0x61800800 +#define CONFIG_SPL_MAX_SIZE 0x100000 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) #define CONFIG_ROCKCHIP_CHIP_TAG "RK32" From 09259fce1e8b4ac34a47d4590f42878a38b42826 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:25 +0800 Subject: [PATCH 09/50] sysreset: enable driver support in SPL/TPL SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by: Kever Yang --- arch/Kconfig | 1 + arch/arm/Kconfig | 1 + configs/am65x_evm_a53_defconfig | 1 + configs/am65x_evm_r5_defconfig | 1 + configs/am65x_hs_evm_a53_defconfig | 1 + configs/am65x_hs_evm_r5_defconfig | 1 + configs/mt7629_rfb_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/sysreset/Kconfig | 18 ++++++++++++++++++ drivers/sysreset/Makefile | 2 +- 10 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index 760023b19a..03277dd2c1 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -158,6 +158,7 @@ config X86 imply DM_USB imply DM_VIDEO imply SYSRESET + imply SPL_SYSRESET imply SYSRESET_X86 imply USB_ETHER_ASIX imply USB_ETHER_SMSC95XX diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a3d67e43f0..3c4af1f299 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1436,6 +1436,7 @@ config ARCH_STM32MP select SYSCON select SYSRESET select SYS_THUMB_BUILD + imply SPL_SYSRESET imply CMD_DM imply CMD_POWEROFF imply ENV_VARS_UBOOT_RUNTIME_CONFIG diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 101fae1456..41cf0100fa 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -72,4 +72,5 @@ CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_TI=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 8dce577cf7..3814872ec7 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -83,6 +83,7 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig index 7af0046ee3..9c55cd37f6 100644 --- a/configs/am65x_hs_evm_a53_defconfig +++ b/configs/am65x_hs_evm_a53_defconfig @@ -75,4 +75,5 @@ CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_TI=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig index 8d5d3590b2..0b12f15782 100644 --- a/configs/am65x_hs_evm_r5_defconfig +++ b/configs/am65x_hs_evm_r5_defconfig @@ -85,6 +85,7 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 01b952fc15..0dceafdaa6 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -65,6 +65,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MTK_QSPI=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index a46edee634..e2826a6a95 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -174,6 +174,7 @@ CONFIG_SANDBOX_SPI=y CONFIG_SPMI=y CONFIG_SPMI_SANDBOX=y CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y CONFIG_TIMER=y CONFIG_TIMER_EARLY=y CONFIG_SANDBOX_TIMER=y diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 8ce3e2e207..d456f0ce36 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -13,6 +13,24 @@ config SYSRESET to effect a reset. The uclass will try all available drivers when reset_walk() is called. +config SPL_SYSRESET + bool "Enable support for system reset drivers in SPL mode" + depends on SYSRESET && SPL_DM + help + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when + reset_walk() is called. + +config TPL_SYSRESET + bool "Enable support for system reset drivers in TPL mode" + depends on SYSRESET && TPL_DM + help + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when + reset_walk() is called. + if SYSRESET config SYSRESET_GPIO diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index b3728ac17f..8e1c845dfe 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -2,7 +2,7 @@ # # (C) Copyright 2016 Cadence Design Systems Inc. -obj-$(CONFIG_SYSRESET) += sysreset-uclass.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o obj-$(CONFIG_ARCH_STI) += sysreset_sti.o From d55dbfed1677dc35bc29e1a297695e63eaf37a13 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:26 +0800 Subject: [PATCH 10/50] rockchip: rk322x: dts: enable uart2 for SPL/TPL When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console. Signed-off-by: Kever Yang --- arch/arm/dts/rk3229-evb.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index bfb367ac99..632cdc9bc3 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -82,6 +82,7 @@ }; &uart2 { + u-boot,dm-pre-reloc; status = "okay"; }; From 26f3814e02de8bea7518f9b3c6ec9d9c6f225397 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:27 +0800 Subject: [PATCH 11/50] rockchip: evb-rk3229: remove unnecessary defines Prefer to use default setting like other SoCs. Signed-off-by: Kever Yang --- include/configs/evb_rk3229.h | 44 +----------------------------------- 1 file changed, 1 insertion(+), 43 deletions(-) diff --git a/include/configs/evb_rk3229.h b/include/configs/evb_rk3229.h index 369b0bc68a..6a91a82ceb 100644 --- a/include/configs/evb_rk3229.h +++ b/include/configs/evb_rk3229.h @@ -8,48 +8,6 @@ #include - -/* Store env in emmc */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#ifndef CONFIG_SPL_BUILD -/* Enable gpt partition table */ -#undef PARTS_DEFAULT -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=loader_a,start=4M,size=4M,uuid=${uuid_gpt_loader};" \ - "name=loader_b,size=4M,uuid=${uuid_gpt_reserved};" \ - "name=trust_a,size=4M,uuid=${uuid_gpt_reserved};" \ - "name=trust_b,size=4M,uuid=${uuid_gpt_reserved};" \ - "name=misc,size=4M,uuid=${uuid_gpt_misc};" \ - "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \ - "name=boot_a,size=32M,uuid=${uuid_gpt_boot_a};" \ - "name=boot_b,size=32M,uuid=${uuid_gpt_boot_b};" \ - "name=system_a,size=818M,uuid=${uuid_gpt_system_a};" \ - "name=system_b,size=818M,uuid=${uuid_gpt_system_b};" \ - "name=vendor_a,size=50M,uuid=${uuid_gpt_vendor_a};" \ - "name=vendor_b,size=50M,uuid=${uuid_gpt_vendor_b};" \ - "name=cache,size=100M,uuid=${uuid_gpt_cache};" \ - "name=persist,size=4M,uuid=${uuid_gpt_persist};" \ - "name=userdata,size=-,uuid=${uuid_gpt_userdata};\0" \ - -#define CONFIG_PREBOOT - -#define CONFIG_SYS_BOOT_RAMDISK_HIGH - -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND \ - "mmc read 0x61000000 0x8000 0x5000;" \ - "bootm 0x61000000" \ - -/* Enable atags */ -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) -#define CONFIG_INITRD_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG - -#endif +#define CONFIG_SYS_MMC_ENV_DEV 0 #endif From 7c2a7542350ec8807f87417759f404f4865d6cdf Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 2 Apr 2019 20:41:28 +0800 Subject: [PATCH 12/50] rockchip: evb-rk3229: add README file for OP-TEE support Detail of step by step to bring up the board with OP-TEE support. Signed-off-by: Kever Yang --- board/rockchip/evb_rk3229/README | 72 ++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 board/rockchip/evb_rk3229/README diff --git a/board/rockchip/evb_rk3229/README b/board/rockchip/evb_rk3229/README new file mode 100644 index 0000000000..93328c75b2 --- /dev/null +++ b/board/rockchip/evb_rk3229/README @@ -0,0 +1,72 @@ +Get the Source and prebuild binary +================================== + + > mkdir ~/evb_rk3229 + > cd ~/evb_rk3229 + > git clone git://git.denx.de/u-boot.git + > git clone https://github.com/OP-TEE/optee_os.git + > git clone https://github.com/rockchip-linux/rkbin.git + > git clone https://github.com/rockchip-linux/rkdeveloptool.git + +Compile the OP-TEE +=============== + + > cd optee_os + > make clean + > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x + Get tee.bin in this step, copy it to U-Boot root dir: + > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin + +Compile the U-Boot +================== + + > cd ../u-boot + > export CROSS_COMPILE=arm-linux-gnueabihf- + > export ARCH=arm + > make evb-rk3229_defconfig + > make + > make u-boot.itb + + Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step. + +Compile the rkdeveloptool +======================= + Follow instructions in latest README + > cd ../rkflashtool + > autoreconf -i + > ./configure + > make + > sudo make install + + Get rkdeveloptool in you Host in this step. + +Both origin binaries and Tool are ready now, choose either option 1 or +option 2 to deploy U-Boot. + +Package the image +================= + + > cd ../u-boot + > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img + > cat spl/u-boot-spl.bin >> idbloader.img + + Get idbloader.img in this step. + +Flash the image to eMMC +======================= +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > cd .. + > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin + > rkdeveloptool wl 64 u-boot/idbloader.img + > rkdeveloptool wl 0x4000 u-boot/u-boot.itb + > rkdeveloptool rd + +Flash the image to SD card +========================== + > dd if=u-boot/idbloader.img of=/dev/sdb seek=64 + > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384 + +You should be able to get U-Boot log message with OP-TEE boot info. + +For more detail, please reference to: +http://opensource.rock-chips.com/wiki_Boot_option From a5fd9a7e1e7bb3d0061009f53f9557d03311edb6 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 6 Sep 2017 09:33:22 +0800 Subject: [PATCH 13/50] rockchip: evb-rk322x: update defconfig with tpl and optee support Enable all the options for TPL/SPL and OPTEE. Signed-off-by: Kever Yang --- configs/evb-rk3229_defconfig | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index c2ed11dfc1..9ee9daa3af 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -1,38 +1,52 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y -CONFIG_SYS_TEXT_BASE=0x60000000 +CONFIG_SYS_TEXT_BASE=0x61000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_ROCKCHIP_RK322X=y -CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_TPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 CONFIG_TARGET_EVB_RK3229=y CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_SPL_STACK_R_ADDR=0x60600000 CONFIG_DEBUG_UART_BASE=0x11030000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="arch/arm/mach-rockchip/fit_spl_optee.its" CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_TEXT_BASE=0x10081000 +CONFIG_SPL_TEXT_BASE=0x60000000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_OPTEE=y +CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds" CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y CONFIG_CLK=y CONFIG_SPL_CLK=y +CONFIG_TPL_CLK=y +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y @@ -47,6 +61,7 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y @@ -57,4 +72,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x2207 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_FUNCTION_MASS_STORAGE=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y From 579a1684663c6c7d440aead9b16525ae72fca8c8 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:24 +0800 Subject: [PATCH 14/50] rockchip: rk3368: support UART2/4 in board_debug_uart_init() evb-rk3368 is using UART2 and PX5 evb is using UART4 Signed-off-by: Kever Yang Tested-by: Andy Yan --- arch/arm/mach-rockchip/rk3368/rk3368.c | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 1ed06c5352..f06d27717d 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -124,6 +124,46 @@ void board_debug_uart_init(void) GPIO2D0_MASK, GPIO2D0_UART0_SIN); rk_clrsetreg(&grf->gpio2d_iomux, GPIO2D1_MASK, GPIO2D1_UART0_SOUT); +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000) + struct rk3368_pmu_grf * const pmugrf __maybe_unused = + (struct rk3368_pmu_grf * const)0xff738000; + + enum { + /* UART4 */ + GPIO0D2_MASK = GENMASK(5, 4), + GPIO0D2_GPIO = 0, + GPIO0D2_UART4_SOUT = (3 << 4), + + GPIO0D3_MASK = GENMASK(7, 6), + GPIO0D3_GPIO = 0, + GPIO0D3_UART4_SIN = (3 << 6), + }; + + /* Enable early UART4 on the PX5 */ + rk_clrsetreg(&pmugrf->gpio0d_iomux, + GPIO0D2_MASK | GPIO0D3_MASK, + GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN); +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000) + struct rk3368_grf * const grf = + (struct rk3368_grf * const)0xff770000; + + enum { + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = GENMASK(13, 12), + GPIO2A6_GPIO = 0, + GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT), + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = GENMASK(11, 10), + GPIO2A5_GPIO = 0, + GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT), + }; + + /* Enable early UART2 on the RK3368 */ + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A6_MASK, GPIO2A6_UART2_SIN); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A5_MASK, GPIO2A5_UART2_SOUT); #endif } #endif From 4d9dd40d68e4d1fbe170ade90e36753ff259ffca Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:25 +0800 Subject: [PATCH 15/50] rockchip: px5 update dts for spl/tpl TPL need dmc to init ddr sdram, and emmc, boot-order. Signed-off-by: Kever Yang Tested-by: Andy Yan --- arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi index 7495781454..18b841864c 100644 --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -2,6 +2,27 @@ /* * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH */ +/ { + chosen { + u-boot,spl-boot-order = &emmc; + }; +}; + +&dmc { + u-boot,dm-pre-reloc; + + /* + * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct + * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for + * details on the 'rockchip,memory-schedule' property and how it + * affects the physical-address to device-address mapping. + */ + rockchip,memory-schedule = ; + rockchip,ddr-frequency = <800000000>; + rockchip,ddr-speed-bin = ; + + status = "okay"; +}; &pinctrl { u-boot,dm-pre-reloc; @@ -20,6 +41,10 @@ u-boot,dm-pre-reloc; }; +&sgrf { + u-boot,dm-pre-reloc; +}; + &cru { u-boot,dm-pre-reloc; }; @@ -31,3 +56,7 @@ &uart4 { u-boot,dm-pre-reloc; }; + +&emmc { + u-boot,dm-pre-reloc; +}; From cd193462ee3ee5ea39a6d7b2c276b4e77531a472 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:26 +0800 Subject: [PATCH 16/50] rockchip: px5: update SPL size for spl/tpl Use larger space for load bl31 in SPL Signed-off-by: Kever Yang Tested-by: Andy Yan --- include/configs/evb_px5.h | 1 + include/configs/rk3368_common.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h index e67bee1721..e9304206bb 100644 --- a/include/configs/evb_px5.h +++ b/include/configs/evb_px5.h @@ -9,5 +9,6 @@ #include #define CONFIG_CONSOLE_SCROLL_LINES 10 +#define CONFIG_SYS_MMC_ENV_DEV 0 #endif diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index bb2e96ba05..13630ba386 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -27,9 +27,10 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00280000 -#define CONFIG_SPL_MAX_SIZE 0x40000 +#define CONFIG_SPL_MAX_SIZE 0x60000 #define CONFIG_SPL_BSS_START_ADDR 0x400000 #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 +#define CONFIG_SPL_STACK 0x00188000 #ifndef CONFIG_SPL_BUILD #define ENV_MEM_LAYOUT_SETTINGS \ From 259afb16922e3db0a4c6d87862eac53affb64f03 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 12 Feb 2019 15:19:07 +0800 Subject: [PATCH 17/50] rockchip: px5: update defconfig for TPL/SPL Add options to support TPL. Signed-off-by: Kever Yang --- configs/evb-px5_defconfig | 56 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index 0f73d0b608..fc4b09423c 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -1,30 +1,82 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00200000 -CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3368=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_TPL_LIBCOMMON_SUPPORT=y +CONFIG_TPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_TARGET_EVB_PX5=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xFF1c0000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_BOOTSTAGE=y +CONFIG_SPL_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_BOOTSTAGE_FDT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_TPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds" +CONFIG_TPL_BOOTROM_SUPPORT=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_TPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_DEFAULT_DEVICE_TREE="rk3368-px5-evb" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent" +CONFIG_TPL_OF_PLATDATA=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TPL_DM=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_TPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_TPL_SYSCON=y CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_TPL_CLK=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_SYSRESET=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_TPL_TIMER=y +CONFIG_ROCKCHIP_TIMER=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y From 6b780e441b807f7340e6b2f250f40c9f19e02355 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:28 +0800 Subject: [PATCH 18/50] rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add condition to limit it not affect TPL. Signed-off-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/boot0.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 9ea4708ada..0c375e543a 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -54,6 +54,7 @@ _start: ARM_VECTORS #endif -#if defined(CONFIG_SPL_BUILD) && (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) +#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \ + (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ #endif From 99a1a5b195c00190eb115b09008d3a3828556053 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:29 +0800 Subject: [PATCH 19/50] rockchip: dmc: rk3368: update rank number for evb-px5 evb-px5 has only 1 CS, update for it. Signed-off-by: Kever Yang Tested-by: Andy Yan --- drivers/ram/rockchip/dmc-rk3368.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 92f584fadc..e52fc3baad 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -842,7 +842,11 @@ static int setup_sdram(struct udevice *dev) move_to_access_state(pctl); /* TODO(prt): could detect rank in training... */ +#ifdef CONFIG_TARGET_EVB_PX5 + params->chan.rank = 1; +#else params->chan.rank = 2; +#endif /* TODO(prt): bus width is not auto-detected (yet)... */ params->chan.bw = 2; /* 32bit wide bus */ params->chan.dbw = params->chan.dbw; /* 32bit wide bus */ From 6459e7f5880f48f38b64989b166bde44f150e465 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:30 +0800 Subject: [PATCH 20/50] rockchip: rk3368: remove uart iomux init in SPL The iomux should have been set in board_debug_uart_init(), do not set in board_init_f(), remove it. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3368-board-spl.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index b055ed4aee..c651193712 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -10,11 +10,9 @@ #include #include #include -#include void board_init_f(ulong dummy) { - struct udevice *pinctrl; struct udevice *dev; int ret; @@ -24,19 +22,6 @@ void board_init_f(ulong dummy) hang(); } - /* Set up our preloader console */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - pr_err("%s: pinctrl init failed: %d\n", __func__, ret); - hang(); - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0); - if (ret) { - pr_err("%s: failed to set up console UART\n", __func__); - hang(); - } - preloader_console_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); From 615e9b3ccef450cb03a2346a4e505bf6dd2944e5 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 29 Mar 2019 22:48:31 +0800 Subject: [PATCH 21/50] rockchip: px5: add timer0 dts node as tick timer Let's use rockchip timer before stimer patches can be merged. Signed-off-by: Kever Yang --- arch/arm/dts/rk3368-px5-evb-u-boot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi index 18b841864c..f5406d4c7e 100644 --- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -5,6 +5,7 @@ / { chosen { u-boot,spl-boot-order = &emmc; + tick-timer = "/timer@ff810000"; }; }; @@ -60,3 +61,9 @@ &emmc { u-boot,dm-pre-reloc; }; + +&timer0 { + u-boot,dm-pre-reloc; + clock-frequency = <24000000>; + status = "okay"; +}; From 3cbec0ad090f11006415b191f4a25367f82255c3 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 1 Apr 2019 17:15:53 +0800 Subject: [PATCH 22/50] rockchip: add u-boot-tpl-v8.lds We don't have both sram and sdram in TPL, so update from: arch/arm/cpu/armv8/u-boot-spl.lds Signed-off-by: Kever Yang Reviewed-by: Simon Glass --- arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 94 ++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 arch/arm/mach-rockchip/u-boot-tpl-v8.lds diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds new file mode 100644 index 0000000000..9869972e22 --- /dev/null +++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 + * Rockchip Electronics Co., Ltd + * Kever Yang + * + * (C) Copyright 2013 + * David Feng + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + */ + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + .text : { + . = ALIGN(8); + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + .rodata : { + . = ALIGN(8); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + .data : { + . = ALIGN(8); + *(.data*) + } + + .u_boot_list : { + . = ALIGN(8); + KEEP(*(SORT(.u_boot_list*))); + } + + .image_copy_end : { + . = ALIGN(8); + *(.__image_copy_end) + } + + .end : { + . = ALIGN(8); + *(.__end) + } + + _image_binary_end = .; + + .bss_start (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.__bss_start)); + } + + .bss (NOLOAD) : { + *(.bss*) + . = ALIGN(8); + } + + .bss_end (NOLOAD) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} + +#if defined(CONFIG_TPL_MAX_SIZE) +ASSERT(__image_copy_end - __image_copy_start < (CONFIG_TPL_MAX_SIZE), \ + "TPL image too big"); +#endif + +#if defined(CONFIG_TPL_BSS_MAX_SIZE) +ASSERT(__bss_end - __bss_start < (CONFIG_TPL_BSS_MAX_SIZE), \ + "TPL image BSS too big"); +#endif + +#if defined(CONFIG_TPL_MAX_FOOTPRINT) +ASSERT(__bss_end - _start < (CONFIG_TPL_MAX_FOOTPRINT), \ + "TPL image plus BSS too big"); +#endif From 6bbf5e1a9480004139f543c4717bf95f22b1b5b3 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 9 Nov 2018 11:18:15 +0800 Subject: [PATCH 23/50] rockchip: rk3399: add tpl support Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 34 ++++++++- arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3399-board-tpl.c | 84 +++++++++++++++++++++++ include/configs/rk3399_common.h | 8 +++ 4 files changed, 126 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3399-board-tpl.c diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 48e364e127..f5c3329750 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -154,12 +154,28 @@ config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" select ARM64 select SUPPORT_SPL + select SUPPORT_TPL select SPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL + select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER + imply TPL_SERIAL_SUPPORT + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT + imply TPL_SYS_MALLOC_SIMPLE + imply TPL_BOOTROM_SUPPORT + imply TPL_DRIVERS_MISC_SUPPORT + imply TPL_OF_CONTROL + imply TPL_DM + imply TPL_REGMAP + imply TPL_SYSCON + imply TPL_RAM + imply TPL_CLK + imply TPL_TINY_MEMSET help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. @@ -168,6 +184,22 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +if ROCKCHIP_RK3399 + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" + +config TPL_TEXT_BASE + default 0xff8c2000 + +config TPL_MAX_SIZE + default 188416 + +config TPL_STACK + default 0xff8effff + +endif + config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A @@ -195,7 +227,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" - default y if ROCKCHIP_RK3368 + default y select ROCKCHIP_BROM_HELPER depends on TPL help diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index fd62a693fe..846c82d70a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -12,6 +12,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c new file mode 100644 index 0000000000..86d3ffe97c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_CHN10_BASE 0xff8680a0 +#define TIMER_END_COUNT_L 0x00 +#define TIMER_END_COUNT_H 0x04 +#define TIMER_INIT_COUNT_L 0x10 +#define TIMER_INIT_COUNT_H 0x14 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) + +void secure_timer_init(void) +{ + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); + writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); + writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); + writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + printascii("U-Boot TPL board init\n"); +#endif + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + secure_timer_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + pr_err("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index e7ae2c4640..f31f2658bb 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -18,11 +18,19 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x00400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 +#else #define CONFIG_SPL_STACK 0xff8effff #define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000 /* BSS setup */ #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 +#endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ From 82763349a25e45fe6978d3d6a058980d870936f5 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Mon, 1 Apr 2019 17:20:53 +0800 Subject: [PATCH 24/50] rockchip: ram: rk3399: update for TPL Init the ddr sdram in TPL instead of SPL, update the code. Signed-off-by: Kever Yang Tested-by: Andy Yan --- drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 05ec5fc28d..52518656c4 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -30,7 +30,8 @@ struct chan_info { }; struct dram_info { -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) struct chan_info chan[2]; struct clk ddr_clk; struct rk3399_cru *cru; @@ -55,7 +56,8 @@ struct dram_info { #define PHY_DRV_ODT_40 0xe #define PHY_DRV_ODT_34_3 0xf -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) struct rockchip_dmc_plat { #if CONFIG_IS_ENABLED(OF_PLATDATA) @@ -1187,7 +1189,8 @@ static int rk3399_dmc_init(struct udevice *dev) static int rk3399_dmc_probe(struct udevice *dev) { -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) if (rk3399_dmc_init(dev)) return 0; #else @@ -1226,12 +1229,14 @@ U_BOOT_DRIVER(dmc_rk3399) = { .id = UCLASS_RAM, .of_match = rk3399_dmc_ids, .ops = &rk3399_dmc_ops, -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata, #endif .probe = rk3399_dmc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_TPL_BUILD) || \ + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), #endif }; From bdc00080111f6dc1e48586239e71e22665004aca Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 9 Nov 2018 11:21:38 +0800 Subject: [PATCH 25/50] rockchip: rk3399: update defconfig for TPL The SPL is now running at SDRAM, and 0x10000 is used by BL31, and the ARM SPL do not support relocate now, we need reserved 0x50000 so that it won't overwrite the code when we load the bl31 to target space. We should remove this after we enable the relocate feature. The SPL need malloc 0x9000 for MMC as buffer used for transfer data to IRAM(The EMMC DMA can not transfer data to IRAM directly). Signed-off-by: Kever Yang --- configs/evb-rk3399_defconfig | 7 ++++--- configs/firefly-rk3399_defconfig | 7 ++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 8d57bdf335..5bb910e8d4 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -17,11 +17,11 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -79,4 +79,5 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 CONFIG_DISPLAY_ROCKCHIP_MIPI=y CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 0be2eb6bd0..301b27e3a4 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -5,7 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y -CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 @@ -17,11 +17,11 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -74,4 +74,5 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y From ec107f04b6198933287e85041ff804dd00c11fa3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 26 Apr 2019 19:03:39 -0600 Subject: [PATCH 26/50] rockchip: chromebook_minnie: Enable sound Enable sound for this board, which has the same codec as jerry. Signed-off-by: Simon Glass Signed-off-by: Kever Yang --- arch/arm/dts/rk3288-veyron-minnie.dts | 12 ++++++++++++ configs/chromebook_minnie_defconfig | 5 +++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts index 0a2915fba0..646f6ae742 100644 --- a/arch/arm/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/dts/rk3288-veyron-minnie.dts @@ -85,6 +85,18 @@ regulator-boot-on; vin-supply = <&vcc18_wl>; }; + + sound { + compatible = "rockchip,audio-max98090-jerry"; + + cpu { + sound-dai = <&i2s 0>; + }; + + codec { + sound-dai = <&max98090 0>; + }; + }; }; &backlight { diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 216f5dcf90..17c1ea6453 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -74,6 +75,10 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SOUND=y +CONFIG_I2S=y +CONFIG_I2S_ROCKCHIP=y +CONFIG_SOUND_MAX98090=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y From cc325e4bb65a0c6f6414c10dd2c47801c6871bb4 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Tue, 7 May 2019 09:36:32 +0800 Subject: [PATCH 27/50] Revert "pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl" This reverts commit 502980914b2d6f9ee85a823aa3ef9ead76c0b7f2. This is a superseded version, revert this to apply new patch set. Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 17 ++------ .../pinctrl/rockchip/pinctrl-rockchip-core.c | 39 +++++-------------- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 33 ---------------- 3 files changed, 13 insertions(+), 76 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 8b6ce11a63..60585f3208 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -92,19 +92,10 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } static struct rockchip_pin_bank rk3288_pin_banks[] = { - PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0", - IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, - IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, - IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, - IOMUX_UNROUTED, - DRV_TYPE_WRITABLE_32BIT, - DRV_TYPE_WRITABLE_32BIT, - DRV_TYPE_WRITABLE_32BIT, - 0, - PULL_TYPE_WRITABLE_32BIT, - PULL_TYPE_WRITABLE_32BIT, - PULL_TYPE_WRITABLE_32BIT, - 0 + PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_SOURCE_PMU, + IOMUX_UNROUTED ), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, IOMUX_UNROUTED, diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index ce935656f0..b84b079064 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -228,13 +228,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) } } - if (mux_type & IOMUX_WRITABLE_32BIT) { - regmap_read(regmap, reg, &data); - data &= ~(mask << bit); - } else { - data = (mask << (bit + 16)); - } - + data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); @@ -258,8 +252,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, int reg, ret, i; u32 data, rmask_bits, temp; u8 bit; - /* Where need to clean the special mask for rockchip_perpin_drv_list */ - int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK); + int drv_type = bank->drv[pin_num / 8].drv_type; debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, pin_num, strength); @@ -331,15 +324,10 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, return -EINVAL; } - if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) { - regmap_read(regmap, reg, &data); - data &= ~(((1 << rmask_bits) - 1) << bit); - } else { - /* enable the write to the equivalent lower bits */ - data = ((1 << rmask_bits) - 1) << (bit + 16); - } - + /* enable the write to the equivalent lower bits */ + data = ((1 << rmask_bits) - 1) << (bit + 16); data |= (ret << bit); + ret = regmap_write(regmap, reg, data); return ret; } @@ -387,11 +375,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3288: case RK3368: case RK3399: - /* - * Where need to clean the special mask for - * rockchip_pull_list. - */ - pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK); + pull_type = bank->pull_type[pin_num / 8]; ret = -EINVAL; for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); i++) { @@ -406,15 +390,10 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, return ret; } - if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) { - regmap_read(regmap, reg, &data); - data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit); - } else { - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); - } - + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); data |= (ret << bit); + ret = regmap_write(regmap, reg, data); break; default: diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index 5a6849c996..bc809630c1 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -26,7 +26,6 @@ enum rockchip_pinctrl_type { #define IOMUX_SOURCE_PMU BIT(2) #define IOMUX_UNROUTED BIT(3) #define IOMUX_WIDTH_3BIT BIT(4) -#define IOMUX_WRITABLE_32BIT BIT(5) /** * Defined some common pins constants @@ -50,9 +49,6 @@ struct rockchip_iomux { int offset; }; -#define DRV_TYPE_IO_MASK GENMASK(31, 16) -#define DRV_TYPE_WRITABLE_32BIT BIT(31) - /** * enum type index corresponding to rockchip_perpin_drv_list arrays index. */ @@ -65,9 +61,6 @@ enum rockchip_pin_drv_type { DRV_TYPE_MAX }; -#define PULL_TYPE_IO_MASK GENMASK(31, 16) -#define PULL_TYPE_WRITABLE_32BIT BIT(31) - /** * enum type index corresponding to rockchip_pull_list arrays index. */ @@ -207,32 +200,6 @@ struct rockchip_pin_bank { }, \ } -#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \ - iom2, iom3, drv0, drv1, drv2, \ - drv3, pull0, pull1, pull2, \ - pull3) \ - { \ - .bank_num = id, \ - .nr_pins = pins, \ - .name = label, \ - .iomux = { \ - { .type = iom0, .offset = -1 }, \ - { .type = iom1, .offset = -1 }, \ - { .type = iom2, .offset = -1 }, \ - { .type = iom3, .offset = -1 }, \ - }, \ - .drv = { \ - { .drv_type = drv0, .offset = -1 }, \ - { .drv_type = drv1, .offset = -1 }, \ - { .drv_type = drv2, .offset = -1 }, \ - { .drv_type = drv3, .offset = -1 }, \ - }, \ - .pull_type[0] = pull0, \ - .pull_type[1] = pull1, \ - .pull_type[2] = pull2, \ - .pull_type[3] = pull3, \ - } - #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ label, iom0, iom1, iom2, \ iom3, drv0, drv1, drv2, \ From 0a5cc3cac96dcbb1f31c9c2a3954dad702a543c1 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:50:53 +0800 Subject: [PATCH 28/50] pinctrl: rockchip: Add pull-pin-default param and remove unused param Some Socs use the pull-pin-default config param, need to add it. And input-enable/disable config params are not necessary, remove it. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rockchip-core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index b84b079064..77ac981c40 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -509,9 +509,8 @@ static const struct pinconf_param rockchip_conf_params[] = { { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, - { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, - { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, }; From 8541beb86daf3ce7e4be9ca67859aab3dd0daefb Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:50:54 +0800 Subject: [PATCH 29/50] pinctrl: rockchip: Remove redundant spaces Some files have the redundant spaces, remove them. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 12 ++++++------ drivers/pinctrl/rockchip/pinctrl-rk3188.c | 12 ++++++------ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 18 ++++++++--------- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 20 +++++++++---------- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 24 +++++++++++------------ drivers/pinctrl/rockchip/pinctrl-rk3368.c | 16 +++++++-------- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 24 +++++++++++------------ 7 files changed, 63 insertions(+), 63 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 2729b03443..2a651cd9b8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -36,12 +36,12 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3036_pin_ctrl = { - .pin_banks = rk3036_pin_banks, - .nr_banks = ARRAY_SIZE(rk3036_pin_banks), - .label = "RK3036-GPIO", - .type = RK3036, - .grf_mux_offset = 0xa8, - .pull_calc_reg = rk3036_calc_pull_reg_and_bit, + .pin_banks = rk3036_pin_banks, + .nr_banks = ARRAY_SIZE(rk3036_pin_banks), + .label = "RK3036-GPIO", + .type = RK3036, + .grf_mux_offset = 0xa8, + .pull_calc_reg = rk3036_calc_pull_reg_and_bit, }; static const struct udevice_id rk3036_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 5ed9aec938..7cc52c0075 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -55,12 +55,12 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3188_pin_ctrl = { - .pin_banks = rk3188_pin_banks, - .nr_banks = ARRAY_SIZE(rk3188_pin_banks), - .label = "RK3188-GPIO", - .type = RK3188, - .grf_mux_offset = 0x60, - .pull_calc_reg = rk3188_calc_pull_reg_and_bit, + .pin_banks = rk3188_pin_banks, + .nr_banks = ARRAY_SIZE(rk3188_pin_banks), + .label = "RK3188-GPIO", + .type = RK3188, + .grf_mux_offset = 0x60, + .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; static const struct udevice_id rk3188_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index d2a6cd7055..d67b48a06a 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -183,15 +183,15 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3228_pin_ctrl = { - .pin_banks = rk3228_pin_banks, - .nr_banks = ARRAY_SIZE(rk3228_pin_banks), - .label = "RK3228-GPIO", - .type = RK3288, - .grf_mux_offset = 0x0, - .iomux_routes = rk3228_mux_route_data, - .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), - .pull_calc_reg = rk3228_calc_pull_reg_and_bit, - .drv_calc_reg = rk3228_calc_drv_reg_and_bit, + .pin_banks = rk3228_pin_banks, + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), + .label = "RK3228-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .iomux_routes = rk3228_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, }; static const struct udevice_id rk3228_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 60585f3208..3648f37207 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -124,16 +124,16 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3288_pin_ctrl = { - .pin_banks = rk3288_pin_banks, - .nr_banks = ARRAY_SIZE(rk3288_pin_banks), - .label = "RK3288-GPIO", - .type = RK3288, - .grf_mux_offset = 0x0, - .pmu_mux_offset = 0x84, - .iomux_routes = rk3288_mux_route_data, - .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), - .pull_calc_reg = rk3288_calc_pull_reg_and_bit, - .drv_calc_reg = rk3288_calc_drv_reg_and_bit, + .pin_banks = rk3288_pin_banks, + .nr_banks = ARRAY_SIZE(rk3288_pin_banks), + .label = "RK3288-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x84, + .iomux_routes = rk3288_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), + .pull_calc_reg = rk3288_calc_pull_reg_and_bit, + .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; static const struct udevice_id rk3288_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index f1b3d10dbe..ab634c1123 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -192,18 +192,18 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3328_pin_ctrl = { - .pin_banks = rk3328_pin_banks, - .nr_banks = ARRAY_SIZE(rk3328_pin_banks), - .label = "RK3328-GPIO", - .type = RK3288, - .grf_mux_offset = 0x0, - .iomux_recalced = rk3328_mux_recalced_data, - .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), - .iomux_routes = rk3328_mux_route_data, - .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), - .pull_calc_reg = rk3328_calc_pull_reg_and_bit, - .drv_calc_reg = rk3328_calc_drv_reg_and_bit, - .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, + .pin_banks = rk3328_pin_banks, + .nr_banks = ARRAY_SIZE(rk3328_pin_banks), + .label = "RK3328-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .iomux_recalced = rk3328_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), + .iomux_routes = rk3328_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), + .pull_calc_reg = rk3328_calc_pull_reg_and_bit, + .drv_calc_reg = rk3328_calc_drv_reg_and_bit, + .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, }; static const struct udevice_id rk3328_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index f5cd6ff24e..8bdaf5e4d2 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -85,14 +85,14 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3368_pin_ctrl = { - .pin_banks = rk3368_pin_banks, - .nr_banks = ARRAY_SIZE(rk3368_pin_banks), - .label = "RK3368-GPIO", - .type = RK3368, - .grf_mux_offset = 0x0, - .pmu_mux_offset = 0x0, - .pull_calc_reg = rk3368_calc_pull_reg_and_bit, - .drv_calc_reg = rk3368_calc_drv_reg_and_bit, + .pin_banks = rk3368_pin_banks, + .nr_banks = ARRAY_SIZE(rk3368_pin_banks), + .label = "RK3368-GPIO", + .type = RK3368, + .grf_mux_offset = 0x0, + .pmu_mux_offset = 0x0, + .pull_calc_reg = rk3368_calc_pull_reg_and_bit, + .drv_calc_reg = rk3368_calc_drv_reg_and_bit, }; static const struct udevice_id rk3368_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index c5aab647a5..06276b14ef 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -158,18 +158,18 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { }; static struct rockchip_pin_ctrl rk3399_pin_ctrl = { - .pin_banks = rk3399_pin_banks, - .nr_banks = ARRAY_SIZE(rk3399_pin_banks), - .label = "RK3399-GPIO", - .type = RK3399, - .grf_mux_offset = 0xe000, - .pmu_mux_offset = 0x0, - .grf_drv_offset = 0xe100, - .pmu_drv_offset = 0x80, - .iomux_routes = rk3399_mux_route_data, - .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), - .pull_calc_reg = rk3399_calc_pull_reg_and_bit, - .drv_calc_reg = rk3399_calc_drv_reg_and_bit, + .pin_banks = rk3399_pin_banks, + .nr_banks = ARRAY_SIZE(rk3399_pin_banks), + .label = "RK3399-GPIO", + .type = RK3399, + .grf_mux_offset = 0xe000, + .pmu_mux_offset = 0x0, + .grf_drv_offset = 0xe100, + .pmu_drv_offset = 0x80, + .iomux_routes = rk3399_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), + .pull_calc_reg = rk3399_calc_pull_reg_and_bit, + .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; static const struct udevice_id rk3399_pinctrl_ids[] = { From 54e75702c48a9757e82cbe71176c0b5ddcf6a092 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:50:55 +0800 Subject: [PATCH 30/50] pinctrl: rockchip: Split the common set_mux() into per Soc Such as rk3288's pins of pmu_gpio0 are a special feature, which have no higher 16 writing corresponding bits, use common set_mux() func would introduce more code, so implement their set_mux() in each Soc's own file to reduce the size of code. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 25 +++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3128.c | 37 +++++++++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3188.c | 25 +++++++++++ drivers/pinctrl/rockchip/pinctrl-rk322x.c | 34 +++++++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3288.c | 35 +++++++++++++++- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 37 +++++++++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3368.c | 25 +++++++++++ drivers/pinctrl/rockchip/pinctrl-rk3399.c | 34 +++++++++++++++ .../pinctrl/rockchip/pinctrl-rockchip-core.c | 41 +++++-------------- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 8 ++++ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 28 +++++++++++++ 11 files changed, 297 insertions(+), 32 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 2a651cd9b8..8969aea2e3 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -11,6 +11,30 @@ #include "pinctrl-rockchip.h" +static int rk3036_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3036_PULL_OFFSET 0x118 #define RK3036_PULL_PINS_PER_REG 16 #define RK3036_PULL_BANK_STRIDE 8 @@ -41,6 +65,7 @@ static struct rockchip_pin_ctrl rk3036_pin_ctrl = { .label = "RK3036-GPIO", .type = RK3036, .grf_mux_offset = 0xa8, + .set_mux = rk3036_set_mux, .pull_calc_reg = rk3036_calc_pull_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index 43a6c173a0..de203334c7 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -98,6 +98,42 @@ static struct rockchip_mux_route_data rk3128_mux_route_data[] = { }, }; +static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3128_PULL_OFFSET 0x118 #define RK3128_PULL_PINS_PER_REG 16 #define RK3128_PULL_BANK_STRIDE 8 @@ -133,6 +169,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = { .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), .iomux_routes = rk3128_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), + .set_mux = rk3128_set_mux, .pull_calc_reg = rk3128_calc_pull_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 7cc52c0075..617ae28ac8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -11,6 +11,30 @@ #include "pinctrl-rockchip.h" +static int rk3188_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3188_PULL_OFFSET 0x164 #define RK3188_PULL_PMU_OFFSET 0x64 @@ -60,6 +84,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .label = "RK3188-GPIO", .type = RK3188, .grf_mux_offset = 0x60, + .set_mux = rk3188_set_mux, .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index d67b48a06a..442c40ce0b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -141,6 +141,39 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = { }, }; +static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3228_PULL_OFFSET 0x100 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, @@ -190,6 +223,7 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .grf_mux_offset = 0x0, .iomux_routes = rk3228_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), + .set_mux = rk3228_set_mux, .pull_calc_reg = rk3228_calc_pull_reg_and_bit, .drv_calc_reg = rk3228_calc_drv_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 3648f37207..1fa601d954 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "pinctrl-rockchip.h" @@ -29,6 +28,39 @@ static struct rockchip_mux_route_data rk3288_mux_route_data[] = { }, }; +static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3288_PULL_OFFSET 0x140 #define RK3288_PULL_PMU_OFFSET 0x64 @@ -132,6 +164,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pmu_mux_offset = 0x84, .iomux_routes = rk3288_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), + .set_mux = rk3288_set_mux, .pull_calc_reg = rk3288_calc_pull_reg_and_bit, .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index ab634c1123..de21fba69c 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -121,6 +121,42 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = { }, }; +static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3328_PULL_OFFSET 0x100 static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, @@ -201,6 +237,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), .iomux_routes = rk3328_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), + .set_mux = rk3328_set_mux, .pull_calc_reg = rk3328_calc_pull_reg_and_bit, .drv_calc_reg = rk3328_calc_drv_reg_and_bit, .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 8bdaf5e4d2..c1f692a1cf 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -11,6 +11,30 @@ #include "pinctrl-rockchip.h" +static int rk3368_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3368_PULL_GRF_OFFSET 0x100 #define RK3368_PULL_PMU_OFFSET 0x10 @@ -91,6 +115,7 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .type = RK3368, .grf_mux_offset = 0x0, .pmu_mux_offset = 0x0, + .set_mux = rk3368_set_mux, .pull_calc_reg = rk3368_calc_pull_reg_and_bit, .drv_calc_reg = rk3368_calc_drv_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 06276b14ef..9e8dc2ef82 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -50,6 +50,39 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = { }, }; +static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data, route_reg, route_val; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3399_PULL_GRF_OFFSET 0xe040 #define RK3399_PULL_PMU_OFFSET 0x40 @@ -168,6 +201,7 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pmu_drv_offset = 0x80, .iomux_routes = rk3399_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), + .set_mux = rk3399_set_mux, .pull_calc_reg = rk3399_calc_pull_reg_and_bit, .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 77ac981c40..355fa6c8ad 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -35,8 +35,8 @@ static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) return 0; } -static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, - int *reg, u8 *bit, int *mask) +void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, + int *reg, u8 *bit, int *mask) { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; @@ -58,8 +58,8 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, *bit = data->bit; } -static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, - int mux, u32 *reg, u32 *value) +bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, + int mux, u32 *reg, u32 *value) { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; @@ -82,7 +82,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, return true; } -static int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) +int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) { int offset = 0; @@ -193,11 +193,9 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank, static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) { struct rockchip_pinctrl_priv *priv = bank->priv; + struct rockchip_pin_ctrl *ctrl = priv->ctrl; int iomux_num = (pin / 8); - struct regmap *regmap; - int reg, ret, mask, mux_type; - u8 bit; - u32 data, route_reg, route_val; + int ret; ret = rockchip_verify_mux(bank, pin, mux); if (ret < 0) @@ -208,29 +206,10 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); - regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) - ? priv->regmap_pmu : priv->regmap_base; + if (!ctrl->set_mux) + return -ENOTSUPP; - /* get basic quadrupel of mux registers and the correct reg inside */ - mux_type = bank->iomux[iomux_num].type; - reg = bank->iomux[iomux_num].offset; - reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); - - if (bank->recalced_mask & BIT(pin)) - rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); - - if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - - data = (mask << (bit + 16)); - data |= (mux & mask) << bit; - ret = regmap_write(regmap, reg, data); + ret = ctrl->set_mux(bank, pin, mux); return ret; } diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index bc809630c1..db89b49238 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -277,6 +277,9 @@ struct rockchip_pin_ctrl { struct rockchip_mux_route_data *iomux_routes; u32 niomux_routes; + int (*set_mux)(struct rockchip_pin_bank *bank, + int pin, int mux); + void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); @@ -298,5 +301,10 @@ struct rockchip_pinctrl_priv { extern const struct pinctrl_ops rockchip_pinctrl_ops; int rockchip_pinctrl_probe(struct udevice *dev); +void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, + int *reg, u8 *bit, int *mask); +bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, + int mux, u32 *reg, u32 *value); +int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */ diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index f4a09a6824..c28b504634 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -75,6 +75,33 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { }, }; +static int rv1108_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + ? priv->regmap_pmu : priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RV1108_PULL_PMU_OFFSET 0x10 #define RV1108_PULL_OFFSET 0x110 @@ -177,6 +204,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pmu_mux_offset = 0x0, .iomux_recalced = rv1108_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), + .set_mux = rv1108_set_mux, .pull_calc_reg = rv1108_calc_pull_reg_and_bit, .drv_calc_reg = rv1108_calc_drv_reg_and_bit, .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, From cd8f00ce08102d2dbb350c76bbb53f7b0f804b7d Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:50:56 +0800 Subject: [PATCH 31/50] pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' iomux RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 1fa601d954..5040cd8f48 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -54,7 +54,15 @@ static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) } } - data = (mask << (bit + 16)); + /* bank0 is special, there are no higher 16 bit writing bits. */ + if (bank->bank_num == 0) { + regmap_read(regmap, reg, &data); + data &= ~(mask << bit); + } else { + /* enable the write to the equivalent lower bits */ + data = (mask << (bit + 16)); + } + data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); From 625ab11fdae3daf346647aaba59abee804e34589 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:55:26 +0800 Subject: [PATCH 32/50] pinctrl: rockchip: Split the common set_drive() func into per Soc As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk322x.c | 25 ++++- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 37 +++++-- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 26 ++++- drivers/pinctrl/rockchip/pinctrl-rk3368.c | 38 +++++-- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 75 ++++++++++++- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 101 ++++-------------- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 6 +- drivers/pinctrl/rockchip/pinctrl-rv1108.c | 26 ++++- 8 files changed, 229 insertions(+), 105 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index 442c40ce0b..10200ff3c8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -208,6 +208,29 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } +static int rk3228_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rk3228_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + return ret; +} + static struct rockchip_pin_bank rk3228_pin_banks[] = { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -225,7 +248,7 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), .set_mux = rk3228_set_mux, .pull_calc_reg = rk3228_calc_pull_reg_and_bit, - .drv_calc_reg = rk3228_calc_drv_reg_and_bit, + .set_drive = rk3228_set_drive, }; static const struct udevice_id rk3228_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 5040cd8f48..6ae9f1c76e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -113,10 +113,6 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, if (bank->bank_num == 0) { *regmap = priv->regmap_pmu; *reg = RK3288_DRV_PMU_OFFSET; - - *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; - *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3288_DRV_GRF_OFFSET; @@ -124,11 +120,34 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); - - *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); - *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } + + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; +} + +static int rk3288_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + return ret; } static struct rockchip_pin_bank rk3288_pin_banks[] = { @@ -174,7 +193,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), .set_mux = rk3288_set_mux, .pull_calc_reg = rk3288_calc_pull_reg_and_bit, - .drv_calc_reg = rk3288_calc_drv_reg_and_bit, + .set_drive = rk3288_set_drive, }; static const struct udevice_id rk3288_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index de21fba69c..0ad5669d26 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -191,6 +191,30 @@ static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } +static int rk3328_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rk3328_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3328_SCHMITT_BITS_PER_PIN 1 #define RK3328_SCHMITT_PINS_PER_REG 16 #define RK3328_SCHMITT_BANK_STRIDE 8 @@ -239,7 +263,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), .set_mux = rk3328_set_mux, .pull_calc_reg = rk3328_calc_pull_reg_and_bit, - .drv_calc_reg = rk3328_calc_drv_reg_and_bit, + .set_drive = rk3328_set_drive, .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index c1f692a1cf..40cc846fa8 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -79,10 +79,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, if (bank->bank_num == 0) { *regmap = priv->regmap_pmu; *reg = RK3368_DRV_PMU_OFFSET; - - *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; - *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3368_DRV_GRF_OFFSET; @@ -90,11 +86,35 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); - - *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); - *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } + + *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); + *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); + *bit *= ROCKCHIP_DRV_BITS_PER_PIN; +} + +static int rk3368_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rk3368_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; } static struct rockchip_pin_bank rk3368_pin_banks[] = { @@ -117,7 +137,7 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .pmu_mux_offset = 0x0, .set_mux = rk3368_set_mux, .pull_calc_reg = rk3368_calc_pull_reg_and_bit, - .drv_calc_reg = rk3368_calc_drv_reg_and_bit, + .set_drive = rk3368_set_drive, }; static const struct udevice_id rk3368_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 9e8dc2ef82..82c8feeb7b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -137,6 +137,79 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit = (pin_num % 8) * 2; } +static int rk3399_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data, rmask_bits, temp; + u8 bit; + int drv_type = bank->drv[pin_num / 8].drv_type; + + rk3399_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(drv_type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + switch (drv_type) { + case DRV_TYPE_IO_1V8_3V0_AUTO: + case DRV_TYPE_IO_3V3_ONLY: + rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN; + switch (bit) { + case 0 ... 12: + /* regular case, nothing to do */ + break; + case 15: + /* + * drive-strength offset is special, as it is spread + * over 2 registers, the bit data[15] contains bit 0 + * of the value while temp[1:0] contains bits 2 and 1 + */ + data = (ret & 0x1) << 15; + temp = (ret >> 0x1) & 0x3; + + data |= BIT(31); + ret = regmap_write(regmap, reg, data); + if (ret) + return ret; + + temp |= (0x3 << 16); + reg += 0x4; + ret = regmap_write(regmap, reg, temp); + + return ret; + case 18 ... 21: + /* setting fully enclosed in the second register */ + reg += 4; + bit -= 16; + break; + default: + debug("unsupported bit: %d for pinctrl drive type: %d\n", + bit, drv_type); + return -EINVAL; + } + break; + case DRV_TYPE_IO_DEFAULT: + case DRV_TYPE_IO_1V8_OR_3V0: + case DRV_TYPE_IO_1V8_ONLY: + rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN; + break; + default: + debug("unsupported pinctrl drive type: %d\n", + drv_type); + return -EINVAL; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << rmask_bits) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + static struct rockchip_pin_bank rk3399_pin_banks[] = { PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, @@ -203,7 +276,7 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), .set_mux = rk3399_set_mux, .pull_calc_reg = rk3399_calc_pull_reg_and_bit, - .drv_calc_reg = rk3399_calc_drv_reg_and_bit, + .set_drive = rk3399_set_drive, }; static const struct udevice_id rk3399_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 355fa6c8ad..439e8ba1b5 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -222,93 +222,37 @@ static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { { 4, 7, 10, 13, 16, 19, 22, 26 } }; +int rockchip_translate_drive_value(int type, int strength) +{ + int i, ret; + + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) { + if (rockchip_perpin_drv_list[type][i] == strength) { + ret = i; + break; + } else if (rockchip_perpin_drv_list[type][i] < 0) { + ret = rockchip_perpin_drv_list[type][i]; + break; + } + } + + return ret; +} + static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, int pin_num, int strength) { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; - struct regmap *regmap; - int reg, ret, i; - u32 data, rmask_bits, temp; - u8 bit; - int drv_type = bank->drv[pin_num / 8].drv_type; debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, pin_num, strength); - ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); + if (!ctrl->set_drive) + return -ENOTSUPP; - ret = -EINVAL; - for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { - if (rockchip_perpin_drv_list[drv_type][i] == strength) { - ret = i; - break; - } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { - ret = rockchip_perpin_drv_list[drv_type][i]; - break; - } - } - - if (ret < 0) { - debug("unsupported driver strength %d\n", strength); - return ret; - } - - switch (drv_type) { - case DRV_TYPE_IO_1V8_3V0_AUTO: - case DRV_TYPE_IO_3V3_ONLY: - rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN; - switch (bit) { - case 0 ... 12: - /* regular case, nothing to do */ - break; - case 15: - /* - * drive-strength offset is special, as it is spread - * over 2 registers, the bit data[15] contains bit 0 - * of the value while temp[1:0] contains bits 2 and 1 - */ - data = (ret & 0x1) << 15; - temp = (ret >> 0x1) & 0x3; - - data |= BIT(31); - ret = regmap_write(regmap, reg, data); - if (ret) - return ret; - - temp |= (0x3 << 16); - reg += 0x4; - ret = regmap_write(regmap, reg, temp); - - return ret; - case 18 ... 21: - /* setting fully enclosed in the second register */ - reg += 4; - bit -= 16; - break; - default: - debug("unsupported bit: %d for pinctrl drive type: %d\n", - bit, drv_type); - return -EINVAL; - } - break; - case DRV_TYPE_IO_DEFAULT: - case DRV_TYPE_IO_1V8_OR_3V0: - case DRV_TYPE_IO_1V8_ONLY: - rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN; - break; - default: - debug("unsupported pinctrl drive type: %d\n", - drv_type); - return -EINVAL; - } - - /* enable the write to the equivalent lower bits */ - data = ((1 << rmask_bits) - 1) << (bit + 16); - data |= (ret << bit); - - ret = regmap_write(regmap, reg, data); - return ret; + return ctrl->set_drive(bank, pin_num, strength); } static int rockchip_pull_list[PULL_TYPE_MAX][4] = { @@ -459,9 +403,6 @@ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, break; case PIN_CONFIG_DRIVE_STRENGTH: - if (!ctrl->drv_calc_reg) - return -ENOTSUPP; - rc = rockchip_set_drive_perpin(bank, pin, arg); if (rc < 0) return rc; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index db89b49238..2ef24dce6c 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -283,9 +283,8 @@ struct rockchip_pin_ctrl { void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); - void (*drv_calc_reg)(struct rockchip_pin_bank *bank, - int pin_num, struct regmap **regmap, - int *reg, u8 *bit); + int (*set_drive)(struct rockchip_pin_bank *bank, + int pin_num, int strength); int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit); @@ -306,5 +305,6 @@ void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, int mux, u32 *reg, u32 *value); int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); +int rockchip_translate_drive_value(int type, int strength); #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */ diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index c28b504634..1a150ff0f1 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -155,6 +155,30 @@ static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_DRV_BITS_PER_PIN; } +static int rv1108_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg, ret; + u32 data; + u8 bit; + int type = bank->drv[pin_num / 8].drv_type; + + rv1108_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + ret = rockchip_translate_drive_value(type, strength); + if (ret < 0) { + debug("unsupported driver strength %d\n", strength); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + return ret; +} + #define RV1108_SCHMITT_PMU_OFFSET 0x30 #define RV1108_SCHMITT_GRF_OFFSET 0x388 #define RV1108_SCHMITT_BANK_STRIDE 8 @@ -206,7 +230,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), .set_mux = rv1108_set_mux, .pull_calc_reg = rv1108_calc_pull_reg_and_bit, - .drv_calc_reg = rv1108_calc_drv_reg_and_bit, + .set_drive = rv1108_set_drive, .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, }; From 956362c84b0422ea99da947feca2878193c26ade Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:56:34 +0800 Subject: [PATCH 33/50] pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strength RK3288 pmu_gpio0 drive strength setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 6ae9f1c76e..d1b9aeb3d9 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -143,8 +143,15 @@ static int rk3288_set_drive(struct rockchip_pin_bank *bank, return ret; } - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + /* bank0 is special, there are no higher 16 bit writing bits. */ + if (bank->bank_num == 0) { + regmap_read(regmap, reg, &data); + data &= ~(((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << bit); + } else { + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + } + data |= (ret << bit); ret = regmap_write(regmap, reg, data); return ret; From 743a77373bfa22ca099b30d4ac88d95a2f98d1b6 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:57:05 +0800 Subject: [PATCH 34/50] pinctrl: rockchip: Split the common set_pull() func into per Soc As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 23 ++++- drivers/pinctrl/rockchip/pinctrl-rk3128.c | 23 ++++- drivers/pinctrl/rockchip/pinctrl-rk3188.c | 29 +++++- drivers/pinctrl/rockchip/pinctrl-rk322x.c | 29 +++++- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 42 ++++++-- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 29 +++++- drivers/pinctrl/rockchip/pinctrl-rk3368.c | 42 ++++++-- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 42 ++++++-- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 97 ++++--------------- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 7 +- drivers/pinctrl/rockchip/pinctrl-rv1108.c | 30 +++++- 11 files changed, 278 insertions(+), 115 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 8969aea2e3..498b633f22 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -53,6 +53,27 @@ static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit = pin_num % RK3036_PULL_PINS_PER_REG; }; +static int rk3036_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit; + u32 data; + + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && + pull != PIN_CONFIG_BIAS_DISABLE) + return -ENOTSUPP; + + rk3036_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + data = BIT(bit + 16); + if (pull == PIN_CONFIG_BIAS_DISABLE) + data |= BIT(bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + static struct rockchip_pin_bank rk3036_pin_banks[] = { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -66,7 +87,7 @@ static struct rockchip_pin_ctrl rk3036_pin_ctrl = { .type = RK3036, .grf_mux_offset = 0xa8, .set_mux = rk3036_set_mux, - .pull_calc_reg = rk3036_calc_pull_reg_and_bit, + .set_pull = rk3036_set_pull, }; static const struct udevice_id rk3036_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index de203334c7..104b76c19e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -152,6 +152,27 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit = pin_num % RK3128_PULL_PINS_PER_REG; } +static int rk3128_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit; + u32 data; + + if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && + pull != PIN_CONFIG_BIAS_DISABLE) + return -ENOTSUPP; + + rk3128_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + data = BIT(bit + 16); + if (pull == PIN_CONFIG_BIAS_DISABLE) + data |= BIT(bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + static struct rockchip_pin_bank rk3128_pin_banks[] = { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -170,7 +191,7 @@ static struct rockchip_pin_ctrl rk3128_pin_ctrl = { .iomux_routes = rk3128_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), .set_mux = rk3128_set_mux, - .pull_calc_reg = rk3128_calc_pull_reg_and_bit, + .set_pull = rk3128_set_pull, }; static const struct udevice_id rk3128_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 617ae28ac8..e09c799e72 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -71,6 +71,33 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, } } +static int rk3188_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3188_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + static struct rockchip_pin_bank rk3188_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), PIN_BANK(1, 32, "gpio1"), @@ -85,7 +112,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .type = RK3188, .grf_mux_offset = 0x60, .set_mux = rk3188_set_mux, - .pull_calc_reg = rk3188_calc_pull_reg_and_bit, + .set_pull = rk3188_set_pull, }; static const struct udevice_id rk3188_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index 10200ff3c8..b69d9795bb 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -191,6 +191,33 @@ static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } +static int rk3228_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3228_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3228_DRV_GRF_OFFSET 0x200 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, @@ -247,7 +274,7 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .iomux_routes = rk3228_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), .set_mux = rk3228_set_mux, - .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .set_pull = rk3228_set_pull, .set_drive = rk3228_set_drive, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index d1b9aeb3d9..9192aa3949 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -82,10 +82,6 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, if (bank->bank_num == 0) { *regmap = priv->regmap_pmu; *reg = RK3288_PULL_PMU_OFFSET; - - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3288_PULL_OFFSET; @@ -93,11 +89,39 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); - - *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; +} + +static int rk3288_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3288_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; } #define RK3288_DRV_PMU_OFFSET 0x70 @@ -199,7 +223,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .iomux_routes = rk3288_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), .set_mux = rk3288_set_mux, - .pull_calc_reg = rk3288_calc_pull_reg_and_bit, + .set_pull = rk3288_set_pull, .set_drive = rk3288_set_drive, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 0ad5669d26..7ac5c0226e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -174,6 +174,33 @@ static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } +static int rk3328_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3328_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RK3328_DRV_GRF_OFFSET 0x200 static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, @@ -262,7 +289,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .iomux_routes = rk3328_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), .set_mux = rk3328_set_mux, - .pull_calc_reg = rk3328_calc_pull_reg_and_bit, + .set_pull = rk3328_set_pull, .set_drive = rk3328_set_drive, .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 40cc846fa8..06de27aa30 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -48,10 +48,6 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, if (bank->bank_num == 0) { *regmap = priv->regmap_pmu; *reg = RK3368_PULL_PMU_OFFSET; - - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3368_PULL_GRF_OFFSET; @@ -59,11 +55,39 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 2nd bank */ *reg -= 0x10; *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); - - *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; +} + +static int rk3368_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3368_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; } #define RK3368_DRV_PMU_OFFSET 0x20 @@ -136,7 +160,7 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .grf_mux_offset = 0x0, .pmu_mux_offset = 0x0, .set_mux = rk3368_set_mux, - .pull_calc_reg = rk3368_calc_pull_reg_and_bit, + .set_pull = rk3368_set_pull, .set_drive = rk3368_set_drive, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 82c8feeb7b..68bb492a6b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -98,10 +98,6 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *reg = RK3399_PULL_PMU_OFFSET; *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; - - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); - *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } else { *regmap = priv->regmap_base; *reg = RK3399_PULL_GRF_OFFSET; @@ -109,11 +105,39 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, /* correct the offset, as we're starting with the 3rd bank */ *reg -= 0x20; *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; - *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); - - *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); - *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } + + *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); + *bit *= ROCKCHIP_PULL_BITS_PER_PIN; +} + +static int rk3399_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rk3399_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; } static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, @@ -275,7 +299,7 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .iomux_routes = rk3399_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), .set_mux = rk3399_set_mux, - .pull_calc_reg = rk3399_calc_pull_reg_and_bit, + .set_pull = rk3399_set_pull, .set_drive = rk3399_set_drive, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 439e8ba1b5..b3379a0d3f 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -270,61 +270,35 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = { }, }; +int rockchip_translate_pull_value(int type, int pull) +{ + int i, ret; + + ret = -EINVAL; + for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]); + i++) { + if (rockchip_pull_list[type][i] == pull) { + ret = i; + break; + } + } + + return ret; +} + static int rockchip_set_pull(struct rockchip_pin_bank *bank, int pin_num, int pull) { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; - struct regmap *regmap; - int reg, ret, i, pull_type; - u8 bit; - u32 data; debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); - ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); + if (!ctrl->set_pull) + return -ENOTSUPP; - switch (ctrl->type) { - case RK3036: - case RK3128: - data = BIT(bit + 16); - if (pull == PIN_CONFIG_BIAS_DISABLE) - data |= BIT(bit); - ret = regmap_write(regmap, reg, data); - break; - case RV1108: - case RK3188: - case RK3288: - case RK3368: - case RK3399: - pull_type = bank->pull_type[pin_num / 8]; - ret = -EINVAL; - for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); - i++) { - if (rockchip_pull_list[pull_type][i] == pull) { - ret = i; - break; - } - } - - if (ret < 0) { - debug("unsupported pull setting %d\n", pull); - return ret; - } - - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); - data |= (ret << bit); - - ret = regmap_write(regmap, reg, data); - break; - default: - debug("unsupported pinctrl type\n"); - return -EINVAL; - } - - return ret; + return ctrl->set_pull(bank, pin_num, pull); } static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, @@ -350,28 +324,6 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, return regmap_write(regmap, reg, data); } -/* - * Pinconf_ops handling - */ -static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, - unsigned int pull) -{ - switch (ctrl->type) { - case RK3036: - case RK3128: - return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || - pull == PIN_CONFIG_BIAS_DISABLE); - case RV1108: - case RK3188: - case RK3288: - case RK3368: - case RK3399: - return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); - } - - return false; -} - /* set the pin config settings for a specified pin */ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, u32 pin, u32 param, u32 arg) @@ -382,21 +334,10 @@ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - rc = rockchip_set_pull(bank, pin, param); - if (rc) - return rc; - break; - case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: case PIN_CONFIG_BIAS_BUS_HOLD: - if (!rockchip_pinconf_pull_valid(ctrl, param)) - return -ENOTSUPP; - - if (!arg) - return -EINVAL; - rc = rockchip_set_pull(bank, pin, param); if (rc) return rc; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index 2ef24dce6c..c21b79602c 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -279,10 +279,8 @@ struct rockchip_pin_ctrl { int (*set_mux)(struct rockchip_pin_bank *bank, int pin, int mux); - - void (*pull_calc_reg)(struct rockchip_pin_bank *bank, - int pin_num, struct regmap **regmap, - int *reg, u8 *bit); + int (*set_pull)(struct rockchip_pin_bank *bank, + int pin_num, int pull); int (*set_drive)(struct rockchip_pin_bank *bank, int pin_num, int strength); int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, @@ -306,5 +304,6 @@ bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, int mux, u32 *reg, u32 *value); int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); int rockchip_translate_drive_value(int type, int strength); +int rockchip_translate_pull_value(int type, int pull); #endif /* __DRIVERS_PINCTRL_ROCKCHIP_H */ diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index 1a150ff0f1..6456483e36 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -128,6 +128,34 @@ static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= ROCKCHIP_PULL_BITS_PER_PIN; } +static int rv1108_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -ENOTSUPP; + + rv1108_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + #define RV1108_DRV_PMU_OFFSET 0x20 #define RV1108_DRV_GRF_OFFSET 0x210 @@ -229,7 +257,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .iomux_recalced = rv1108_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), .set_mux = rv1108_set_mux, - .pull_calc_reg = rv1108_calc_pull_reg_and_bit, + .set_pull = rv1108_set_pull, .set_drive = rv1108_set_drive, .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, }; From 69a38f81bb55893a8555c899319305c539226a0a Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:57:28 +0800 Subject: [PATCH 35/50] pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' pull RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 9192aa3949..24af3597ec 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -116,8 +116,15 @@ static int rk3288_set_pull(struct rockchip_pin_bank *bank, return ret; } - /* enable the write to the equivalent lower bits */ - data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + /* bank0 is special, there are no higher 16 bit writing bits */ + if (bank->bank_num == 0) { + regmap_read(regmap, reg, &data); + data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit); + } else { + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + } + data |= (ret << bit); ret = regmap_write(regmap, reg, data); From 623aca88308b4f917f0465cd5dd1514ee781bee8 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:57:54 +0800 Subject: [PATCH 36/50] pinctrl: rockchip: Clean the unused type and label As the mux/pull/drive feature implement at own file, the type and label are not necessary. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3036.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3128.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3188.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk322x.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3368.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 2 -- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 12 ------------ drivers/pinctrl/rockchip/pinctrl-rv1108.c | 2 -- 10 files changed, 30 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 498b633f22..28c905129b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -83,8 +83,6 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = { static struct rockchip_pin_ctrl rk3036_pin_ctrl = { .pin_banks = rk3036_pin_banks, .nr_banks = ARRAY_SIZE(rk3036_pin_banks), - .label = "RK3036-GPIO", - .type = RK3036, .grf_mux_offset = 0xa8, .set_mux = rk3036_set_mux, .set_pull = rk3036_set_pull, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index 104b76c19e..3eb4d952bb 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -183,8 +183,6 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = { static struct rockchip_pin_ctrl rk3128_pin_ctrl = { .pin_banks = rk3128_pin_banks, .nr_banks = ARRAY_SIZE(rk3128_pin_banks), - .label = "RK3128-GPIO", - .type = RK3128, .grf_mux_offset = 0xa8, .iomux_recalced = rk3128_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index e09c799e72..043764fc92 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -108,8 +108,6 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = { static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pin_banks = rk3188_pin_banks, .nr_banks = ARRAY_SIZE(rk3188_pin_banks), - .label = "RK3188-GPIO", - .type = RK3188, .grf_mux_offset = 0x60, .set_mux = rk3188_set_mux, .set_pull = rk3188_set_pull, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index b69d9795bb..c5e4fe30a7 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -268,8 +268,6 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = { static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .pin_banks = rk3228_pin_banks, .nr_banks = ARRAY_SIZE(rk3228_pin_banks), - .label = "RK3228-GPIO", - .type = RK3288, .grf_mux_offset = 0x0, .iomux_routes = rk3228_mux_route_data, .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 24af3597ec..7ae147f304 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -223,8 +223,6 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = { static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pin_banks = rk3288_pin_banks, .nr_banks = ARRAY_SIZE(rk3288_pin_banks), - .label = "RK3288-GPIO", - .type = RK3288, .grf_mux_offset = 0x0, .pmu_mux_offset = 0x84, .iomux_routes = rk3288_mux_route_data, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 7ac5c0226e..d4d37af206 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -281,8 +281,6 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .pin_banks = rk3328_pin_banks, .nr_banks = ARRAY_SIZE(rk3328_pin_banks), - .label = "RK3328-GPIO", - .type = RK3288, .grf_mux_offset = 0x0, .iomux_recalced = rk3328_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 06de27aa30..6cb7bb45d9 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -155,8 +155,6 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = { static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .pin_banks = rk3368_pin_banks, .nr_banks = ARRAY_SIZE(rk3368_pin_banks), - .label = "RK3368-GPIO", - .type = RK3368, .grf_mux_offset = 0x0, .pmu_mux_offset = 0x0, .set_mux = rk3368_set_mux, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 68bb492a6b..75634e9f4d 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -290,8 +290,6 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pin_banks = rk3399_pin_banks, .nr_banks = ARRAY_SIZE(rk3399_pin_banks), - .label = "RK3399-GPIO", - .type = RK3399, .grf_mux_offset = 0xe000, .pmu_mux_offset = 0x0, .grf_drv_offset = 0xe100, diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index c21b79602c..1c6fc2c5b2 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -8,16 +8,6 @@ #include -enum rockchip_pinctrl_type { - RV1108, - RK3036, - RK3128, - RK3188, - RK3288, - RK3368, - RK3399, -}; - /** * Encode variants of iomux registers into a type variable */ @@ -266,8 +256,6 @@ struct rockchip_pin_ctrl { struct rockchip_pin_bank *pin_banks; u32 nr_banks; u32 nr_pins; - char *label; - enum rockchip_pinctrl_type type; int grf_mux_offset; int pmu_mux_offset; int grf_drv_offset; diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index 6456483e36..0bcf11bb41 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -250,8 +250,6 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = { static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pin_banks = rv1108_pin_banks, .nr_banks = ARRAY_SIZE(rv1108_pin_banks), - .label = "RV1108-GPIO", - .type = RV1108, .grf_mux_offset = 0x10, .pmu_mux_offset = 0x0, .iomux_recalced = rv1108_mux_recalced_data, From 79d16e45409f928c952b6935d695cd08f9db76b3 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 16 Apr 2019 21:58:13 +0800 Subject: [PATCH 37/50] pinctrl: rockchip: Also move common set_schmitter func into per Soc file Only some Soc need Schmitter feature, so move the implementation into their own files. Signed-off-by: David Wu Signed-off-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 17 ++++++++++++++++- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 19 +++---------------- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 5 ++--- drivers/pinctrl/rockchip/pinctrl-rv1108.c | 17 ++++++++++++++++- 4 files changed, 37 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index d4d37af206..8d37a6f945 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -264,6 +264,21 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +static int rk3328_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg; + u8 bit; + u32 data; + + rk3328_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + /* enable the write to the equivalent lower bits */ + data = BIT(bit + 16) | (enable << bit); + + return regmap_write(regmap, reg, data); +} + static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), @@ -289,7 +304,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .set_mux = rk3328_set_mux, .set_pull = rk3328_set_pull, .set_drive = rk3328_set_drive, - .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, + .set_schmitt = rk3328_set_schmitt, }; static const struct udevice_id rk3328_pinctrl_ids[] = { diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index b3379a0d3f..80dc431d20 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -306,30 +306,20 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; - struct regmap *regmap; - int reg, ret; - u8 bit; - u32 data; debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, pin_num, enable); - ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); - if (ret) - return ret; + if (!ctrl->set_schmitt) + return -ENOTSUPP; - /* enable the write to the equivalent lower bits */ - data = BIT(bit + 16) | (enable << bit); - - return regmap_write(regmap, reg, data); + return ctrl->set_schmitt(bank, pin_num, enable); } /* set the pin config settings for a specified pin */ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, u32 pin, u32 param, u32 arg) { - struct rockchip_pinctrl_priv *priv = bank->priv; - struct rockchip_pin_ctrl *ctrl = priv->ctrl; int rc; switch (param) { @@ -350,9 +340,6 @@ static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, break; case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - if (!ctrl->schmitt_calc_reg) - return -ENOTSUPP; - rc = rockchip_set_schmitt(bank, pin, arg); if (rc < 0) return rc; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index 1c6fc2c5b2..9651e9c7a6 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -271,9 +271,8 @@ struct rockchip_pin_ctrl { int pin_num, int pull); int (*set_drive)(struct rockchip_pin_bank *bank, int pin_num, int strength); - int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, - int pin_num, struct regmap **regmap, - int *reg, u8 *bit); + int (*set_schmitt)(struct rockchip_pin_bank *bank, + int pin_num, int enable); }; /** diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index 0bcf11bb41..54610a3e90 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -237,6 +237,21 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, return 0; } +static int rv1108_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg; + u8 bit; + u32 data; + + rv1108_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + /* enable the write to the equivalent lower bits */ + data = BIT(bit + 16) | (enable << bit); + + return regmap_write(regmap, reg, data); +} + static struct rockchip_pin_bank rv1108_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -257,7 +272,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .set_mux = rv1108_set_mux, .set_pull = rv1108_set_pull, .set_drive = rv1108_set_drive, - .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, + .set_schmitt = rv1108_set_schmitt, }; static const struct udevice_id rv1108_pinctrl_ids[] = { From 82d08de9c5dba1b5dd0689570c74698aae307599 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 May 2019 23:51:49 +0530 Subject: [PATCH 38/50] dts: Makefile: Build rockchip dtbs based on SoC types - Sometimes u-boot specific dtsi files are included automatically which would build for entire rockchip SoC, even-though the respective dtsi should used it for specific family of rockchip SoC. - Sometimes u-boot specific dts nodes or properties can use config macros from respective rockchip family include/configs files, example CONFIG_SPL_PAD_TO. So, it's better to compile the dtbs based on the respective rockchip family types rather than rockchip itself to avoid compilation issues. This patch organize the existing dtb's based on the rockchip family types. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a199f3f988..b76e0ba726 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -65,16 +65,23 @@ dtb-$(CONFIG_KIRKWOOD) += \ dtb-$(CONFIG_ARCH_OWL) += \ bubblegum_96.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rk3036-sdk.dtb \ - rk3128-evb.dtb \ - rk3188-radxarock.dtb \ - rk3229-evb.dtb \ +dtb-$(CONFIG_ROCKCHIP_RK3036) += \ + rk3036-sdk.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3128) += \ + rk3128-evb.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3188) += \ + rk3188-radxarock.dtb + +dtb-$(CONFIG_ROCKCHIP_RK322X) += \ + rk3229-evb.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-evb.dtb \ rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ - rk3399-orangepi.dtb \ rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ @@ -83,22 +90,32 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3288-veyron-speedy.dtb \ - rk3288-vyasa.dtb \ - rk3328-evb.dtb \ - rk3399-ficus.dtb \ + rk3288-vyasa.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-evb.dtb + +dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ rk3368-px5-evb.dtb \ + +dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-evb.dtb \ + rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ rk3399-rock960.dtb \ + +dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb + dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-nanopi-k2.dtb \ meson-gxbb-odroidc2.dtb \ From ddf49cbf35c97d043c46e9bc9c3029053720a812 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 May 2019 23:51:50 +0530 Subject: [PATCH 39/50] arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi files Devicetree files in RK3399 platform is synced from Linux, like other platforms does. Apart from these u-boot in rk3399 would also require some u-boot specific node like dmc. dmc node has big chunk of DDR timing parameters which are specific to specific board, and maintained with rk3399-sdram*.dtsi. So, create board specific -u-boot.dtsi files and move these sdram dtsi files accordingly. This would help of maintain u-boot specific changes separately without touching Linux dts(i) files which indeed easy for syncing from Linux between releases. These board specific -u-boot.dtsi can be extendible to add more u-boot specific nodes or properties in future. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-evb.dts | 1 - arch/arm/dts/rk3399-ficus-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-ficus.dts | 1 - arch/arm/dts/rk3399-firefly-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-firefly.dts | 1 - arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-gru-bob.dts | 1 - arch/arm/dts/rk3399-rock960-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-rock960.dts | 1 - 10 files changed, 30 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/rk3399-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-ficus-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-firefly-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-gru-bob-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock960-u-boot.dtsi diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi new file mode 100644 index 0000000000..7e2c57af22 --- /dev/null +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 9162f3dd50..a506e8da37 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -7,7 +7,6 @@ #include #include #include "rk3399.dtsi" -#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" / { model = "Rockchip RK3399 Evaluation Board"; diff --git a/arch/arm/dts/rk3399-ficus-u-boot.dtsi b/arch/arm/dts/rk3399-ficus-u-boot.dtsi new file mode 100644 index 0000000000..eab86bdb30 --- /dev/null +++ b/arch/arm/dts/rk3399-ficus-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-ddr3-1600.dtsi" diff --git a/arch/arm/dts/rk3399-ficus.dts b/arch/arm/dts/rk3399-ficus.dts index 4af0e4e383..4b2dd82b67 100644 --- a/arch/arm/dts/rk3399-ficus.dts +++ b/arch/arm/dts/rk3399-ficus.dts @@ -8,7 +8,6 @@ /dts-v1/; #include "rk3399-rock960.dtsi" -#include "rk3399-sdram-ddr3-1600.dtsi" / { model = "96boards RK3399 Ficus"; diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi new file mode 100644 index 0000000000..eab86bdb30 --- /dev/null +++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-ddr3-1600.dtsi" diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index 46f2ffaf8d..a4cb64f8bd 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -7,7 +7,6 @@ #include #include #include "rk3399.dtsi" -#include "rk3399-sdram-ddr3-1600.dtsi" / { model = "Firefly-RK3399 Board"; diff --git a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi new file mode 100644 index 0000000000..9edb8cf841 --- /dev/null +++ b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-gru-bob.dts b/arch/arm/dts/rk3399-gru-bob.dts index 0e3d91fc28..1ee0dc0d9f 100644 --- a/arch/arm/dts/rk3399-gru-bob.dts +++ b/arch/arm/dts/rk3399-gru-bob.dts @@ -7,7 +7,6 @@ /dts-v1/; #include "rk3399-gru-chromebook.dtsi" -#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" / { model = "Google Bob"; diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi new file mode 100644 index 0000000000..5256f6d3f2 --- /dev/null +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-sdram-lpddr3-2GB-1600.dtsi" diff --git a/arch/arm/dts/rk3399-rock960.dts b/arch/arm/dts/rk3399-rock960.dts index 25c58b4261..7e06bc97e5 100644 --- a/arch/arm/dts/rk3399-rock960.dts +++ b/arch/arm/dts/rk3399-rock960.dts @@ -5,7 +5,6 @@ /dts-v1/; #include "rk3399-rock960.dtsi" -#include "rk3399-sdram-lpddr3-2GB-1600.dtsi" / { model = "96boards Rock960"; From b5f88913a661a668ae6da1e7c82bc9e654347ce5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 May 2019 23:51:51 +0530 Subject: [PATCH 40/50] rockchip: dts: rk3399-u-boot: Add u-boot, dm-pre-reloc for spi1 Add u-boot,dm-pre-reloc property for spi1, so-that the subsequent rk3399 boards which boot from SPI. This help to separate the u-boot specific properties away from base dts files so-that the Linux sync become easy and meaningful. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index f533ed95eb..0786c1193a 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -6,3 +6,7 @@ &sdmmc { u-boot,dm-pre-reloc; }; + +&spi1 { + u-boot,dm-pre-reloc; +}; From 90430fa895a197206da93a601607809998dc5a74 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 May 2019 23:51:52 +0530 Subject: [PATCH 41/50] arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsi Now we have - board specific -u-boot.dtsi files for board specific u-boot dts changes. - soc specific rk3399-u-boot.dtsi for soc specific u-boot dts changes. So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi and drop the properties which are globally available in rk3399-u-boot.dtsi Right now rk3399-u-boot.dtsi has sdmmc, spi1 u-boot,dm-pre-reloc property and more properties and nodes can be move further based on the requirements. This would fix, the -u-boot.dtsi inclusion for evb, firefly, puma boards that was accidentally merged on below commit. "rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi" (sha1: e05b4a4fa84b65a0c8873e8f34721741fe2bc09d) Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-evb-u-boot.dtsi | 1 + arch/arm/dts/rk3399-firefly-u-boot.dtsi | 1 + arch/arm/dts/rk3399-gru-bob-u-boot.dtsi | 1 + arch/arm/dts/rk3399-gru-u-boot.dtsi | 6 ++++++ arch/arm/dts/rk3399-gru.dtsi | 1 - arch/arm/dts/rk3399-puma-ddr1600.dts | 1 + arch/arm/dts/rk3399-puma.dtsi | 2 -- 7 files changed, 10 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/rk3399-gru-u-boot.dtsi diff --git a/arch/arm/dts/rk3399-evb-u-boot.dtsi b/arch/arm/dts/rk3399-evb-u-boot.dtsi index 7e2c57af22..20910e744b 100644 --- a/arch/arm/dts/rk3399-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3399-evb-u-boot.dtsi @@ -3,4 +3,5 @@ * Copyright (C) 2019 Jagan Teki */ +#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr3-4GB-1600.dtsi" diff --git a/arch/arm/dts/rk3399-firefly-u-boot.dtsi b/arch/arm/dts/rk3399-firefly-u-boot.dtsi index eab86bdb30..67b63a8352 100644 --- a/arch/arm/dts/rk3399-firefly-u-boot.dtsi +++ b/arch/arm/dts/rk3399-firefly-u-boot.dtsi @@ -3,4 +3,5 @@ * Copyright (C) 2019 Jagan Teki */ +#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi" diff --git a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi index 9edb8cf841..726f396f32 100644 --- a/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-bob-u-boot.dtsi @@ -3,4 +3,5 @@ * Copyright (C) 2019 Jagan Teki */ +#include "rk3399-gru-u-boot.dtsi" #include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi new file mode 100644 index 0000000000..7bddc3acdb --- /dev/null +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index 4cdb4320b7..ca0fc391b2 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -545,7 +545,6 @@ ap_i2c_audio: &i2c8 { &spi1 { status = "okay"; - u-boot,dm-pre-reloc; pinctrl-names = "default", "sleep"; pinctrl-1 = <&spi1_sleep>; diff --git a/arch/arm/dts/rk3399-puma-ddr1600.dts b/arch/arm/dts/rk3399-puma-ddr1600.dts index 337e0eabb4..42763f82d0 100644 --- a/arch/arm/dts/rk3399-puma-ddr1600.dts +++ b/arch/arm/dts/rk3399-puma-ddr1600.dts @@ -6,5 +6,6 @@ /dts-v1/; #include "rk3399-puma.dtsi" +#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-ddr3-1600.dtsi" diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 319a610022..897e0bda85 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -647,8 +647,6 @@ &spi1 { - u-boot,dm-pre-reloc; - status = "okay"; #address-cells = <1>; From 0d31044eb6689bd8d240f1ccd0b9c80c52d1398a Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 7 May 2019 23:54:40 +0530 Subject: [PATCH 42/50] rockchip: rk3399: orangepi: Add SPL_TEXT_BASE CONFIG_SPL_TEXT_BASE was available in configs/rk3399_common.h when the OrangePI rk3399 board supported during first version patch. But, later below change which move this config into Kconfig and same has been merged in mainline tree. "configs: move CONFIG_SPL_TEXT_BASE to Kconfig" (sha1: f89d6133eef2e068f9c33853b6584d7fcbfa9d2e) Unfortunately, the maintainer applied the initial version patch, instead of looking for next version changes. Fix it by adding SPL_TEXT_BASE in orangepi-rk3399 defconfig. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- configs/orangepi-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index cdccf221b5..ba13976cc6 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_ATF=y From e0bca2821f63fc5566cc2d74710beaa51e7ccd33 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:41 +0530 Subject: [PATCH 43/50] rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2 To make successful build with dts(i) files syncing from Linux 5.1-rc2 the rk3399.dtsi would require pwm2_pin_pull_down. So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2. Since this node is strictly not part of any commit alone, I have mentioned Linux 5.1-rc2 tag for future reference of where would this sync coming from. Signed-off-by: Jagan Teki Reviewed-by: Paul Kocialkowski Reviewed-by: Kever Yang --- arch/arm/dts/rk3399.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index b53e41b4dc..b73442ee34 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -2495,6 +2495,11 @@ rockchip,pins = <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; }; + + pwm2_pin_pull_down: pwm2-pin-pull-down { + rockchip,pins = + <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; + }; }; pwm3a { From 695dca9a47a5e379b9543c7762f938b034519364 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:42 +0530 Subject: [PATCH 44/50] Kconfig: Add default SPL_FIT_GENERATOR for rockchip Add default SPL_FIT_GENERATOR py script for rockchip platforms if specific target enabled SPL_LOAD_FIT. So, this would help get rid of explicitly mentioning the default SPL FIT generator in defconfigs. however some targets, like puma_rk3399 still require their own FIT generator so in those cases the default will override with defconfig defined generator. Reviewed-by: Paul Kocialkowski Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- Kconfig | 1 + configs/chromebook_bob_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - 7 files changed, 1 insertion(+), 6 deletions(-) diff --git a/Kconfig b/Kconfig index 7a5491bd67..91c1082ace 100644 --- a/Kconfig +++ b/Kconfig @@ -435,6 +435,7 @@ config SPL_FIT_GENERATOR string ".its file generator script for U-Boot FIT image" depends on SPL_FIT default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI + default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP help Specifies a (platform specific) script file to generate the FIT source file used to build the U-Boot FIT image file. This gets diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index ce07a7f0ff..bd836acad5 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -19,7 +19,6 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 5bb910e8d4..94963e4280 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 79da86b32f..926d244fbe 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 301b27e3a4..5016fb8993 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index ba13976cc6..22ddd8dce3 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 8d490be18c..48d14ef7d8 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -13,7 +13,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y From 2666bd42c6ebac995dc65cf31512e26c26b59599 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:43 +0530 Subject: [PATCH 45/50] arm: rockchip: rk3399: Move common configs in Kconfig Few SPL and U-Boot proper configs are common to all rk3399 target defconfigs, move them and select it from platform kconfig. Moved configs: - SPL_ATF - SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF - SPL_LOAD_FIT - SPL_CLK if SPL - SPL_PINCTRL if SPL - SPL_RAM if SPL - SPL_REGMAP if SPL - SPL_SYSCON if SPL - CLK - FIT - PINCTRL - RAM - REGMAP - SYSCON - DM_PMIC - DM_REGULATOR_FIXED Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 16 ++++++++++++++++ configs/chromebook_bob_defconfig | 16 ---------------- configs/evb-rk3399_defconfig | 16 ---------------- configs/ficus-rk3399_defconfig | 16 ---------------- configs/firefly-rk3399_defconfig | 16 ---------------- configs/orangepi-rk3399_defconfig | 16 ---------------- configs/puma-rk3399_defconfig | 16 ---------------- configs/rock960-rk3399_defconfig | 16 ---------------- 8 files changed, 16 insertions(+), 112 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f5c3329750..c05e3c3f48 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -156,11 +156,27 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SUPPORT_TPL select SPL + select SPL_ATF + select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_LOAD_FIT + select SPL_CLK if SPL + select SPL_PINCTRL if SPL + select SPL_RAM if SPL + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT + select CLK + select FIT + select PINCTRL + select RAM + select REGMAP + select SYSCON + select DM_PMIC + select DM_REGULATOR_FIXED select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER imply TPL_SERIAL_SUPPORT diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index bd836acad5..e61e27c992 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -17,8 +17,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -26,8 +24,6 @@ CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -46,12 +42,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-bob" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -71,16 +61,10 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 94963e4280..f10502cb0e 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index 926d244fbe..6a1b279cc9 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -32,12 +28,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-ficus" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -49,17 +39,11 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 5016fb8993..61f05b784f 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -11,15 +11,11 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -32,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -48,16 +38,10 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 22ddd8dce3..3f02c89983 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -11,16 +11,12 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -32,12 +28,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -47,16 +37,10 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 964464ac0f..03f0bfdb59 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -15,8 +15,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y @@ -32,8 +30,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -52,12 +48,6 @@ CONFIG_OF_LIVE=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-ddr1600" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -76,20 +66,14 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_DM_PMIC_FAN53555=y CONFIG_PMIC_RK8XX=y CONFIG_SPL_DM_REGULATOR=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_DM_RTC=y CONFIG_RTC_ISL1208=y CONFIG_DEBUG_UART_SHIFT=2 diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 48d14ef7d8..1958b7e190 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -11,16 +11,12 @@ CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_SYS_PROMPT="rock960 => " CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y @@ -33,12 +29,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y @@ -46,16 +36,10 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_PMIC=y CONFIG_PMIC_RK8XX=y CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y From d364e6bdd7ca9eb94dd03cf54c5d8472cf1850dd Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:44 +0530 Subject: [PATCH 46/50] rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag. Linux commit details about the rk3399-nanopi4.dtsi sync: "arm64: dts: rockchip: Add nanopi4 bluetooth" (sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030) Signed-off-by: Jagan Teki Reviewed-by: Paul Kocialkowski Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-nanopi4.dtsi | 703 +++++++++++++++++++++++++++++++ 1 file changed, 703 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi4.dtsi diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi new file mode 100644 index 0000000000..d325e11728 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi4.dtsi @@ -0,0 +1,703 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RK3399-based FriendlyElec boards device tree source + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vdd_5v>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_s3"; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vbus_typec"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_gpio>; + + status { + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_s3>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c7>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu_b"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + clock-output-names = "xin32k", "rtc_clko_wifi"; + #clock-cells = <1>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_center"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_cpu_l"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_cam: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_cam"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_touch"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmupll"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <3000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sdio"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <200000>; + i2c-scl-rising-time-ns = <150>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vbus_typec>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc_1v8>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pcie_phy { + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + status = "okay"; +}; + +&pinctrl { + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + power_key: power-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + /* external pullup to VCC1V8_PMUPLL */ + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg_on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc0_det_l: sdmmc0-det-l { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; From adc91db0e6f83653da06066bc60633d7a437bcbd Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:45 +0530 Subject: [PATCH 47/50] rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1 Attaching GPIO functionality to SDMMC0_DET pin (which does in Linux base dts) make dwmmc driver "fail to detect the card". Card did not respond to voltage select! It may be because the existing driver can't support gpio card detection. So, change the pinctrl functionality from RK_FUNC_GPIO to RK_FUNC_1 like other rk3399 dts does via sdmmc_cd pin. Cc: Robin Murphy Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi4-u-boot.dtsi diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi new file mode 100644 index 0000000000..bb8bdf08c5 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +&sdmmc { + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; +}; From b2f5da9dd0689a718bf0c9dbfa48fedfce0bb336 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:46 +0530 Subject: [PATCH 48/50] rockchip: rk3399: Add Nanopi M4 board support Add initial support for Nanopi M4 board. Specification - Rockchip RK3399 - Dual-Channel 4GB LPDDR3-1866 - SD card slot - eMMC socket - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, DP, MIPI DSI/CSI - USB 3.0 x4 - USB Type C power and data - GPIO1, GPIO2 expansion ports - DC5V/3A Commit details of rk3399-nanopi-m4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: Refine nanopi4 differences" (sha1: c62ffaf5026d0b7633e62b2cea8450b5543c349a) Signed-off-by: Jagan Teki Reviewed-by: Kever Yang Reviewed-by: Philipp Tomsich --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi | 7 +++ arch/arm/dts/rk3399-nanopi-m4.dts | 66 +++++++++++++++++++++++ arch/arm/dts/rk3399-nanopi4-u-boot.dtsi | 2 + board/rockchip/evb_rk3399/MAINTAINERS | 6 +++ configs/nanopi-m4-rk3399_defconfig | 59 ++++++++++++++++++++ 6 files changed, 141 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopi-m4.dts create mode 100644 configs/nanopi-m4-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b76e0ba726..c77e7631d0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-nanopi-m4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ diff --git a/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi new file mode 100644 index 0000000000..17201bcf41 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopi-m4.dts b/arch/arm/dts/rk3399-nanopi-m4.dts new file mode 100644 index 0000000000..60358ab8c7 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopi-m4.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4"; + compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi index bb8bdf08c5..a126bbaf08 100644 --- a/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi4-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2019 Jagan Teki */ +#include "rk3399-u-boot.dtsi" + &sdmmc { pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; }; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 07ee8ce92c..ae43805a6a 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig +NANOPI-M4 +M: Jagan Teki +S: Maintained +F: configs/nanopi-m4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi + ORANGEPI-RK3399 M: Jagan Teki S: Maintained diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig new file mode 100644 index 0000000000..c2832788f0 --- /dev/null +++ b/configs/nanopi-m4-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y From 65cc7dcd77aef48ed20d73d17367e32f5cc4e8dd Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:47 +0530 Subject: [PATCH 49/50] rockchip: rk3399: Add Nanopc T4 board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for Nanopc T4 board. Specification - Rockchip RK3399 - Dual-Channel 4GB LPDDR3-1866 - SD card slot - 16GB eMMC - RTL8211E 1Gbps - AP6356S WiFI/BT - HDMI In/Out, DP, MIPI DSI/CSI, eDP - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - DC 12V/2A Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: Add NanoPC-T4 IR receiver" (sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3) Tested-by: Daniel Gröber Signed-off-by: Jagan Teki Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 7 ++ arch/arm/dts/rk3399-nanopc-t4.dts | 91 +++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 ++ configs/nanopc-t4-rk3399_defconfig | 59 +++++++++++++++ 5 files changed, 164 insertions(+) create mode 100644 arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-nanopc-t4.dts create mode 100644 configs/nanopc-t4-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c77e7631d0..75d4fda73e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ + rk3399-nanopc-t4.dtb \ rk3399-nanopi-m4.dtb \ rk3399-orangepi.dtb \ rk3399-puma-ddr1333.dtb \ diff --git a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi new file mode 100644 index 0000000000..17201bcf41 --- /dev/null +++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki + */ + +#include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" diff --git a/arch/arm/dts/rk3399-nanopc-t4.dts b/arch/arm/dts/rk3399-nanopc-t4.dts new file mode 100644 index 0000000000..84433cf02b --- /dev/null +++ b/arch/arm/dts/rk3399-nanopc-t4.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPC-T4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPC-T4"; + compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; + + vcc12v0_sys: vcc12v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "vcc12v0_sys"; + }; + + vcc5v0_host0: vcc5v0-host0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host0"; + vin-supply = <&vcc5v0_sys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx>; + }; +}; + +&pinctrl { + ir { + ir_rx: ir-rx { + /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ + rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host0>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host0>; +}; + +&vcc5v0_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vcc3v3_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vbus_typec { + enable-active-high; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index ae43805a6a..f55c92f80c 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig +NANOPC-T4 +M: Jagan Teki +S: Maintained +F: configs/nanopc-t4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi + NANOPI-M4 M: Jagan Teki S: Maintained diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig new file mode 100644 index 0000000000..d9f2137b4c --- /dev/null +++ b/configs/nanopc-t4-rk3399_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0xff8c2000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y From c661c059b9a507baa1704c03f29ff2f79bae2ce2 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Wed, 8 May 2019 11:11:51 +0530 Subject: [PATCH 50/50] doc: rockchip: Add global doc for rk3399 build/flash Since rockchip have an individual doc/README.rockchip, it would be better to update the same instead of maintaining it separately in board files. So, add the documentation for rk3399 - procedure to build for Rockchip miniloader and U-Boot SPL options - procedure to boot from SD for Rockchip miniloader and U-Boot SPL options - procedure to build ATF, PMU M0 firmware for puma boards - add boot logs of each option, so-that it would help for future boards porting Signed-off-by: Jagan Teki Reviewed-by: Philipp Tomsich Reviewed-by: Kever Yang --- doc/README.rockchip | 233 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 232 insertions(+), 1 deletion(-) diff --git a/doc/README.rockchip b/doc/README.rockchip index ec10ebbc26..ca4d6473b0 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -88,10 +88,92 @@ One RV3188 baord is supported: For example: +1. To build RK3288 board: + CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all -(or you can use another cross compiler if you prefer) + (or you can use another cross compiler if you prefer) +2. To build RK3399 board: + + Option 1: Package the image with Rockchip miniloader: + + - Compile U-Boot + + => cd /path/to/u-boot + => make nanopi-neo4-rk3399_defconfig + => make + => make u-boot.itb + + - Get the rkbin + + => git clone https://github.com/rockchip-linux/rkbin.git + + - Create trust.img + + => cd /path/to/rkbin + => ./tools/trust_merger RKTRUST/RK3399TRUST.ini + + - Create uboot.img + + => cd /path/to/rkbin + => ./tools/loaderimage --pack --uboot /path/to/u-boot/u-boot-dtb.bin uboot.img + + (Get trust.img and uboot.img) + + Option 2: Package the image with SPL: + + - We need the Python elftools.elf.elffile library for make_fit_atf.py to work + + => sudo apt-get install python-pyelftools + + - Export cross compiler path for aarch64 + + - Compile ATF + + For Puma board. + + => git clone git://git.theobroma-systems.com/arm-trusted-firmware.git + => cd arm-trusted-firmware + => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + + (copy bl31.bin into U-Boot root dir) + => cp build/rk3399/release/bl31/bl31.bin /path/to/u-boot/bl31-rk3399.bin + + For rest of rk3399 boards. + + => git clone https://github.com/ARM-software/arm-trusted-firmware.git + => cd arm-trusted-firmware + + (export cross compiler path for Cortex-M0 MCU likely arm-none-eabi-) + => make realclean + => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 + + (copy bl31.elf into U-Boot root dir) + => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot + + - Compile PMU M0 firmware + + This is optional for most of the rk3399 boards and required only for Puma board. + + => git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git + => cd rk3399-cortex-m0 + + (export cross compiler path for Cortex-M0 PMU) + => make CROSS_COMPILE=arm-cortex_m0-eabi- + + (copy rk3399m0.bin into U-Boot root dir) + => cp rk3399m0.bin /path/to/u-boot + + - Compile U-Boot + + => cd /path/to/u-boot + => make orangepi-rk3399_defconfig + => make + => make u-boot.itb + + (Get spl/u-boot-spl-dtb.bin, u-boot.itb images and some boards would get + spl/u-boot-spl.bin since it doesn't enable CONFIG_SPL_OF_CONTROL) Writing to the board with USB ============================= @@ -225,6 +307,153 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out truncate -s %2048 u-boot.bin cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out +Booting from an SD card on RK3399 +================================= + +To write an image that boots from an SD card (assumed to be /dev/sdc): + +Option 1: Package the image with Rockchip miniloader: + + - Create idbloader.img + + => cd /path/to/u-boot + => ./tools/mkimage -n rk3399 -T rksd -d /path/to/rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin idbloader.img + => cat /path/to/rkbin/bin/rk33/rk3399_miniloader_v1.19.bin >> idbloader.img + + - Write idbloader.img at 64 sector + + => sudo dd if=idbloader.img of=/dev/sdc seek=64 + + - Write trust.img at 24576 + + => sudo dd if=trust.img of=/dev/sdc seek=24576 + + - Write uboot.img at 16384 sector + + => sudo dd if=uboot.img of=/dev/sdc seek=16384 + => sync + +Put this SD (or micro-SD) card into your board and reset it. You should see +something like: + +DDR Version 1.20 20190314 +In +Channel 0: DDR3, 933MHz +Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB +no stride +ch 0 ddrconfig = 0x101, ddrsize = 0x20 +pmugrf_os_reg[2] = 0x10006281, stride = 0x17 +OUT +Boot1: 2019-03-14, version: 1.19 +CPUId = 0x0 +ChipType = 0x10, 239 +mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000 +mmc: ERROR: Card did not respond to voltage select! +emmc reinit +mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000 +mmc: ERROR: Card did not respond to voltage select! +emmc reinit +mmc: ERROR: SDHCI ERR:cmd:0x102,stat:0x18000 +mmc: ERROR: Card did not respond to voltage select! +SdmmcInit=2 1 +mmc0:cmd5,20 +SdmmcInit=0 0 +BootCapSize=0 +UserCapSize=60543MB +FwPartOffset=2000 , 0 +StorageInit ok = 45266 +SecureMode = 0 +SecureInit read PBA: 0x4 +SecureInit read PBA: 0x404 +SecureInit read PBA: 0x804 +SecureInit read PBA: 0xc04 +SecureInit read PBA: 0x1004 +SecureInit read PBA: 0x1404 +SecureInit read PBA: 0x1804 +SecureInit read PBA: 0x1c04 +SecureInit ret = 0, SecureMode = 0 +atags_set_bootdev: ret:(0) +GPT 0x3380ec0 signature is wrong +recovery gpt... +GPT 0x3380ec0 signature is wrong +recovery gpt fail! +LoadTrust Addr:0x4000 +No find bl30.bin +Load uboot, ReadLba = 2000 +hdr 0000000003380880 + 0x0:0x88,0x41,0x3e,0x97,0xe6,0x61,0x54,0x23,0xe9,0x5a,0xd1,0x2b,0xdc,0x2f,0xf9,0x35, + +Load OK, addr=0x200000, size=0x9c9c0 +RunBL31 0x10000 +NOTICE: BL31: v1.3(debug):370ab80 +NOTICE: BL31: Built : 09:23:41, Mar 4 2019 +NOTICE: BL31: Rockchip release version: v1.1 +INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 +INFO: Using opteed sec cpu_context! +INFO: boot cpu mask: 0 +INFO: plat_rockchip_pmu_init(1181): pd status 3e +INFO: BL31: Initializing runtime services +INFO: BL31: Initializing BL32 +INF [0x0] TEE-CORE:init_primary_helper:337: Initializing (1.1.0-195-g8f090d20 #6 Fri Dec 7 06:11:20 UTC 2018 aarch64) + +INF [0x0] TEE-CORE:init_primary_helper:338: Release version: 1.2 + +INF [0x0] TEE-CORE:init_teecore:83: teecore inits done +INFO: BL31: Preparing for EL3 exit to normal world +INFO: Entry point address = 0x200000 +INFO: SPSR = 0x3c9 + + +U-Boot 2019.04-rc4-00136-gfd121f9641-dirty (Apr 16 2019 - 14:02:47 +0530) + +Model: FriendlyARM NanoPi NEO4 +DRAM: 1022 MiB +MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0 +Loading Environment from MMC... *** Warning - bad CRC, using default environment + +In: serial@ff1a0000 +Out: serial@ff1a0000 +Err: serial@ff1a0000 +Model: FriendlyARM NanoPi NEO4 +Net: eth0: ethernet@fe300000 +Hit any key to stop autoboot: 0 +=> + +Option 2: Package the image with SPL: + + - Prefix rk3399 header to SPL image + + => cd /path/to/u-boot + => ./tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl-dtb.bin out + + - Write prefixed SPL at 64th sector + + => sudo dd if=out of=/dev/sdc seek=64 + + - Write U-Boot proper at 16384 sector + + => sudo dd if=u-boot.itb of=/dev/sdc seek=16384 + => sync + +Put this SD (or micro-SD) card into your board and reset it. You should see +something like: + +U-Boot SPL board init +Trying to boot from MMC1 + + +U-Boot 2019.01-00004-g14db5ee998 (Mar 11 2019 - 13:18:41 +0530) + +Model: Orange Pi RK3399 Board +DRAM: 2 GiB +MMC: dwmmc@fe310000: 2, dwmmc@fe320000: 1, sdhci@fe330000: 0 +Loading Environment from MMC... OK +In: serial@ff1a0000 +Out: serial@ff1a0000 +Err: serial@ff1a0000 +Model: Orange Pi RK3399 Board +Net: eth0: ethernet@fe300000 +Hit any key to stop autoboot: 0 +=> Using fastboot on rk3288 ======================== @@ -385,5 +614,7 @@ There are some documents about partitions in the links below. http://rockchip.wikidot.com/partitions -- +Jagan Teki +27 Mar 2019 Simon Glass 24 June 2015