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powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT
When ECC is enabled, DDR controller needs to initialize the data and ecc. The wait time can be calcuated with total memory size, bus width, bus speed and interleaving mode. If it went wrong, it is bettert to timeout than waiting for D_INIT to clear, where it probably hangs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun
Andy Fleming
parent
123922b1e5
commit
f31cfd1925
4 changed files with 71 additions and 27 deletions
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@ -18,12 +18,13 @@
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void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num)
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{
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unsigned int i;
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unsigned int i, bus_width;
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volatile ccsr_ddr_t *ddr;
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u32 temp_sdram_cfg;
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u32 total_gb_size_per_controller;
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int timeout, timeout_save;
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
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u32 total_gb_size_per_controller;
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unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
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int csn = -1;
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#endif
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@ -52,8 +53,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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return;
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}
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out_be32(&ddr->eor, regs->ddr_eor);
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if (regs->ddr_eor)
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out_be32(&ddr->eor, regs->ddr_eor);
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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debug("Workaround for ERRATUM_DDR111_DDR134\n");
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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@ -275,9 +276,46 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
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asm volatile("sync;isync");
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total_gb_size_per_controller = 0;
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (!(regs->cs[i].config & 0x80000000))
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continue;
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total_gb_size_per_controller += 1 << (
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((regs->cs[i].config >> 14) & 0x3) + 2 +
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((regs->cs[i].config >> 8) & 0x7) + 12 +
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((regs->cs[i].config >> 0) & 0x7) + 8 +
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3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
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26); /* minus 26 (count of 64M) */
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}
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if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
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total_gb_size_per_controller *= 3;
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else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
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total_gb_size_per_controller <<= 1;
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/*
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* total memory / bus width = transactions needed
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* transactions needed / data rate = seconds
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* to add plenty of buffer, double the time
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* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
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* Let's wait for 800ms
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*/
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bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
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>> SDRAM_CFG_DBW_SHIFT);
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timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
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(get_ddr_freq(0) >> 20)) << 1;
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timeout_save = timeout;
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total_gb_size_per_controller >>= 4; /* shift down to gb size */
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debug("total %d GB\n", total_gb_size_per_controller);
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debug("Need to wait up to %d * 10ms\n", timeout);
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/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
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while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
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while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
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(timeout >= 0)) {
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udelay(10000); /* throttle polling rate */
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timeout--;
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}
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if (timeout <= 0)
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printf("Waiting for D_INIT timeout. Memory may not work.\n");
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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/* continue this workaround */
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@ -335,23 +373,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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while (in_be32(&ddr->debug[1]) & 0x400)
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udelay(10000); /* throttle polling rate */
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/* 7. Wait for 400ms/GB */
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total_gb_size_per_controller = 0;
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i == csn) {
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total_gb_size_per_controller +=
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((csn_bnds_backup & 0xFFFF) >> 6)
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- (csn_bnds_backup >> 22) + 1;
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} else {
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total_gb_size_per_controller +=
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((regs->cs[i].bnds & 0xFFFF) >> 6)
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- (regs->cs[i].bnds >> 22) + 1;
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}
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}
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if (in_be32(&ddr->sdram_cfg) & 0x80000)
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total_gb_size_per_controller <<= 1;
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debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
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udelay(total_gb_size_per_controller * 400000);
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/* 7. Wait for state machine 2nd run, roughly 400ms/GB */
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debug("Wait for %d * 10ms\n", timeout_save);
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udelay(timeout_save * 10000);
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/* 8. Set sdram_cfg_2[dinit] if options requires */
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setbits_be32(&ddr->sdram_cfg_2,
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@ -359,8 +383,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
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/* 9. Poll until dinit is cleared */
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while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
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udelay(10000);
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timeout = timeout_save;
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debug("Need to wait up to %d * 10ms\n", timeout);
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while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
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(timeout >= 0)) {
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udelay(10000); /* throttle polling rate */
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timeout--;
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}
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if (timeout <= 0)
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printf("Waiting for D_INIT timeout. Memory may not work.\n");
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/* 10. Clear EEBACR[3] */
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clrbits_be32(&ecm->eebacr, 10000000);
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@ -526,6 +526,17 @@ phys_size_t fsl_ddr_sdram(void)
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#endif
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total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
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/* setup 3-way interleaving before enabling DDRC */
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switch (info.memctl_opts[0].memctl_interleaving_mode) {
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case FSL_DDR_3WAY_1KB_INTERLEAVING:
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case FSL_DDR_3WAY_4KB_INTERLEAVING:
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case FSL_DDR_3WAY_8KB_INTERLEAVING:
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fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode);
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break;
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default:
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break;
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}
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/* Program configuration registers. */
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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debug("Programming controller %u\n", i);
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@ -561,7 +572,6 @@ phys_size_t fsl_ddr_sdram(void)
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case FSL_DDR_3WAY_8KB_INTERLEAVING:
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law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
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if (i == 0) {
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fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode);
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fsl_ddr_set_lawbar(&info.common_timing_params[i],
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law_memctl, i);
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}
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@ -142,13 +142,13 @@ void board_add_ram_info(int use_default)
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#if CONFIG_NUM_DDR_CONTROLLERS >= 2
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if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
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ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
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ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
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sdram_cfg = in_be32(&ddr->sdram_cfg);
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}
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#endif
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#if CONFIG_NUM_DDR_CONTROLLERS >= 3
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if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
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ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
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ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
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sdram_cfg = in_be32(&ddr->sdram_cfg);
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}
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#endif
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@ -98,6 +98,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
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#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
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#define SDRAM_CFG_DYN_PWR 0x00200000
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#define SDRAM_CFG_DBW_MASK 0x00180000
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#define SDRAM_CFG_DBW_SHIFT 19
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#define SDRAM_CFG_32_BE 0x00080000
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#define SDRAM_CFG_16_BE 0x00100000
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#define SDRAM_CFG_8_BE 0x00040000
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@ -330,6 +331,7 @@ extern phys_size_t fsl_ddr_sdram_size(void);
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extern int fsl_use_spd(void);
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extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num);
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u32 fsl_ddr_get_intl3r(void);
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/*
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* The 85xx boards have a common prototype for fixed_sdram so put the
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